A power supply device

Abstract

A power supply device includes: a first switch control circuit for generating an output voltage signal based on a first voltage signal and an input voltage signal; wherein the first switch control circuit further includes: a first switch, a first terminal of which is used to receive the input voltage signal; a first resistor, one end of which is coupled to an input node and the other end of which is coupled to a first node; a second resistor, one end of which is coupled to a second terminal of the first switch at a control node and the other end of which is coupled to the first node; and a first capacitor, one end of which is coupled to the control node and the other end of which is coupled to the input node, the first capacitor being used to charge or discharge based on the first voltage signal, wherein the first switch adjusts the voltage level of the output voltage signal according to the voltage level of the control node. In this invention, the power supply device can output switch control signals to a DC power switch circuit via a multi-stage switch to adjust the rise / fall period of the power output signal.

Description

Technical Field

[0001] This utility model relates to a power supply device, and more particularly to a power supply device having a DC power switching circuit. Background Technology

[0002] When controlling a DC switch, the rise / fall time of the output signal needs to be adjusted to meet specific power supply timing requirements, and the rise time of the output signal needs to be extended to suppress the peak value of the pulse current signal generated in the circuit. Traditional DC switch circuits are designed to directly input the switch control signal to the gate of the DC power switch to control the power output signal, and traditional DC switch circuits are designed to turn on the DC switch only at a high potential. Therefore, designing a DC switch circuit that allows adjustment of the rise / fall period of the power output signal through capacitors and resistors, and designing a DC switch circuit that turns on the DC switch at a low potential to ensure the availability of the output signal in the initial timing, are important issues in this field. Utility Model Content

[0003] In some embodiments, a power supply device includes: a first switch control circuit for generating an output voltage signal based on a first voltage signal and an input voltage signal; wherein the first switch control circuit further includes: a first switch, a first terminal of which is used to receive the input voltage signal at an input node; a first resistor, one end of which is coupled to the input node and the other end of which is coupled to a first node; a second resistor, one end of which is coupled to a second terminal of the first switch at a control node and the other end of which is coupled to the first node; and a first capacitor, one end of which is coupled to the control node and the other end of which is coupled to the input node, the first capacitor being used to charge or discharge according to the first voltage signal to adjust the voltage level of the control node, wherein the first switch adjusts the voltage level of the output voltage signal according to the voltage level of the control node.

[0004] In some embodiments, the power supply device further includes: a second switch control circuit for receiving a second voltage signal to output the first voltage signal, wherein the second switch control circuit includes: a second switch, a first terminal of the second switch for outputting the first voltage signal to the first switch control circuit, and a second terminal of the second switch for receiving the second voltage signal; and a third resistor, one end of the third resistor being coupled to the input voltage signal, and the other end of the third resistor being coupled to the second terminal of the second switch.

[0005] In some embodiments, in the power supply device, when the second switch is turned on, the voltage level of the first node decreases according to the resistance values ​​of the first resistor and a fourth resistor, wherein one end of the fourth resistor is coupled to the first node and the other end of the fourth resistor is coupled to the first terminal of the second switch.

[0006] In some embodiments, a power supply device further includes: a third switch control circuit for receiving a third voltage signal to output the second voltage signal, wherein the third switch control circuit includes: a third switch, a first terminal of the third switch for outputting the second voltage signal to the second switch control circuit, and a second terminal of the third switch for receiving the third voltage signal; and a fourth resistor, one end of the fourth resistor being coupled to the input voltage signal, and the other end of the fourth resistor being coupled to the second terminal of the third switch.

[0007] In some embodiments, when the third switch is turned off in the power supply device, the second switch is turned on and the voltage level of the first node decreases, and the first capacitor discharges according to the voltage level of the first node to turn on the first switch.

[0008] In some embodiments, when the first switch in a power supply device is turned on, the voltage level of the output voltage signal continuously rises during a first period.

[0009] In some embodiments, in a power supply device, the duration of the first period increases when at least one of the capacitance value of the first capacitor and the resistance value of the second resistor increases.

[0010] In some embodiments, when the third switch in a power supply device is turned on, the second switch is turned off and the voltage level of the first node rises, and the first capacitor is charged according to the voltage level of the first node to turn off the first switch.

[0011] In some embodiments, when the first switch in a power supply device begins to turn off, the voltage level of the output voltage signal continuously decreases during a second period.

[0012] In some embodiments, in a power supply device, the duration of the second period increases when at least one of the capacitance value of the first capacitor and the resistance value of the second resistor increases. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a power supply device illustrated according to some embodiments of this case;

[0014] Figure 2 This is an operation timing diagram of a power supply device illustrated according to some embodiments of this case;

[0015] Figure 3 This is an operation timing diagram of a power supply device illustrated according to some embodiments of this case;

[0016] Figure 4 This is a schematic diagram of a power supply device illustrated according to some embodiments of this case.

[0017] [Symbol Explanation]

[0018] 100: Power supply device

[0019] 110: DC power supply switching circuit

[0020] 111, 120, 130: Switch control circuit

[0021] 112: Value-taking circuit

[0022] FB1: Conductive structure

[0023] QM1, QB1, QB2: Switches

[0024] VIN, EN, RV1, GV1, CV1~CV3, VOUT: Signals

[0025] NI, NC, N1~N3: Nodes

[0026] R1~R9: Resistors

[0027] C1~C4: Capacitors

[0028] T21~T24, T31~T33: Time

[0029] RDT, RT, FDT, FT: period

[0030] V21~V29, V210~V211, V31~V38: Voltage values Detailed Implementation

[0031] In this document, when an element is referred to as a "connection" or "coupled," it may mean an "electrical connection" or "electrical coupling." "Connection" or "coupled" can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as "first," "second," etc., are used herein to describe different elements, these terms are merely used to distinguish elements or operations described using the same technical terms. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply order or sequence, nor are they intended to limit the scope of this invention.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as they have in the context of the relevant technology and this invention, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined herein.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0034] The following describes several embodiments of this invention with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the invention. That is, these practical details are not essential in some embodiments of this disclosure. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner.

[0035] Figure 1 This is a schematic diagram of a power supply device 100 according to some embodiments of the present invention. In some embodiments, the power supply device 100 is used to generate a power output signal VOUT based on an enable signal EN and a power input signal VIN. Please refer to... Figure 1 The power supply device 100 includes a DC power switch circuit 110, a switch control circuit 120, a switch control circuit 130, and a resistor R7.

[0036] like Figure 1 As shown, the DC power switch circuit 110 is used to receive the switch control signal CV1 and the power input signal VIN to generate the power output signal VOUT.

[0037] The switch control circuit 120 is used to receive the switch control signal CV2 and output the switch control signal CV1.

[0038] The switch control circuit 130 is used to receive the switch control signal CV3 and output the switch control signal CV2.

[0039] Resistor R7 is used to limit the current level of the enable signal EN in order to output the switch control signal CV3.

[0040] The DC power supply switching circuit 110 includes a switching control circuit 111 and a value retrieval circuit 112.

[0041] The switch control circuit 111 is used to receive the switch control signal CV1 to generate the power output signal VOUT.

[0042] The switch control circuit 111 includes a conductive structure FB1, resistors R1 to R3, capacitor C1, and switch QM1.

[0043] In some embodiments, the conductive structure FB1 can be implemented using ferrite beads.

[0044] In some embodiments, the resistance value RV1 of resistor R1, the resistance value RV2 of resistor R2, the voltage level VL1 of the power input signal VIN, and the gate threshold voltage VGSTH satisfy the following relationship:

[0045]

[0046] In some embodiments, the resistance value of resistor R3 is between 0 and 2.2 MOhm.

[0047] In some embodiments, the capacitance value of capacitor C1 is between 10pF and 47uF.

[0048] One end of the conductive structure FB1 is coupled to the source terminal of the switch QM1 at the input node NI, and the other end of the conductive structure FB1 is used to receive the power input signal VIN.

[0049] One end of resistor R1 is coupled to node NI, and the other end of resistor R1 is coupled to resistors R2 and R3 at node N1.

[0050] One end of resistor R2 is coupled to node N1, and the other end of resistor R2 is coupled to switch control circuit 120.

[0051] One end of resistor R3 is coupled to node N1, and the other end of resistor R3 is coupled to capacitor C1 and the gate terminal of switch QM1 at node NC.

[0052] In some embodiments, the voltage level of node N1 is the voltage level after the voltage level VL1 of the power input signal VIN is divided by resistors R1 and R2.

[0053] In some embodiments, the voltage level of node N1 is the same as the voltage level VL1 of the power input signal VIN.

[0054] One end of capacitor C1 is coupled to node NI, and the other end of capacitor C1 is coupled to node NC.

[0055] The drain terminal of switch QM1 is coupled to the value-taking circuit 112, the source terminal of switch QM1 is coupled to node N1, and the gate terminal of switch QM1 is coupled to node NC.

[0056] The value acquisition circuit 112 is used to acquire the value of the power supply output signal VOUT. The value acquisition circuit 112 includes capacitor C2, capacitor C3 and resistor R4.

[0057] One end of capacitor C2 is coupled to switch control circuit 111, and the other end of capacitor C2 is grounded. One end of capacitor C3 is coupled to switch control circuit 111, and the other end of capacitor C3 is grounded. One end of resistor R4 is coupled to switch control circuit 111, and the other end of resistor R4 is grounded.

[0058] The switch control circuit 120 includes switch QB1, capacitor C4, resistor R5 and resistor R6.

[0059] In some embodiments, the resistance values ​​RV5 of resistor R5, RV6 of resistor R6, the voltage level VL1 of the power input signal VIN, and the base threshold voltage VBETH satisfy the following relationship:

[0060]

[0061] The collector of switch QB1 is coupled to switch control circuit 111, the emitter of switch QB1 is grounded, and the base of switch QB1 is coupled to node N2. One end of capacitor C4 is coupled to node N2, and the other end of capacitor C4 is grounded. One end of resistor R5 is coupled to node N2, and the other end of resistor R5 is used to receive the power input signal VIN. One end of resistor R6 is coupled to node N2, and the other end of resistor R6 is grounded.

[0062] In some embodiments, the voltage level of node N2 is the voltage level after voltage division of the power input signal VIN by resistors R5 and R6 using the voltage level VL1.

[0063] In some embodiments, the voltage level of node N2 is zero.

[0064] The switch control circuit 130 includes switch QB2, resistor R8, and resistor R9.

[0065] In some embodiments, the resistance values ​​of resistor R8 (RV8), R9 (RV9), the voltage level of the power input signal VIN (VL1), and the base threshold voltage (VBETH) satisfy the following relationship:

[0066]

[0067] The collector of switch QB2 is coupled to the switch control circuit 120 at node N2, the emitter of switch QB2 is grounded, the base of switch QB2 is coupled to node N3, and switch QB2 is used to receive the switch control signal CV3.

[0068] In some embodiments, the voltage level at node N3 is the voltage level after voltage division of the power input signal VIN by resistors R8 and R9 using the voltage level VL1.

[0069] One end of resistor R7 is coupled to the switch control circuit 130 at node N3, and the other end of resistor R7 is used to receive the enable signal EN.

[0070] Figure 2 This is an operational timing diagram illustrating the discharge of capacitor C1 in a power supply device 100 according to some embodiments of the present invention. In some embodiments, the power supply device 100 generates a voltage signal RV1 at node N1 and a voltage signal GV1 at node NC based on an enable signal EN, and switch QM1 generates a power output signal VOUT based on the voltage signal GV1.

[0071] Please refer to Figure 2 The timing diagram 200 includes voltage signal GV1, enable signal EN, voltage signal RV1 and power output signal VOUT.

[0072] At time T21, the voltage level of the enable signal EN is reduced from voltage value V21 to voltage value V22 to reduce the voltage level of the switch control signal CV3, and the switch QB2 is turned off according to the voltage level of node N3.

[0073] When switch QB2 is turned off, the voltage level of switch control signal CV2 increases, and switch QB1 is turned on according to the voltage level of node N2.

[0074] When switch QB1 is turned on, the voltage levels of switch control signal CV1 and voltage signal RV1 decrease.

[0075] In some embodiments, when switch QB1 is turned on, the voltage level at node N1 decreases according to the resistance value RV2 of resistors R1 and R2.

[0076] When switch QB1 is turned on, capacitor C1 discharges according to the voltage level at node N1. When capacitor C1 discharges, the voltage level of switch control signal GV1 decreases.

[0077] During RDT, the voltage level of the enable signal EN remains at voltage value V22. The voltage level of voltage signal RV1 decreases from voltage value V23 to voltage value V25. The voltage level of voltage signal GV1 decreases from voltage value V24 to voltage value V26.

[0078] In some embodiments, the duration of the RDT is determined based on the rate of decrease of the voltage levels of voltage signals RV1 and GV1.

[0079] The rate at which the voltage levels of voltage signals RV1 and GV1 decrease depends on the discharge rate of capacitor C1.

[0080] The discharge rate of capacitor C1 depends on the capacitance of capacitor C1, the resistance of resistor R3, and the resistance of resistor R2 (RV2).

[0081] When at least one of the capacitance value of capacitor C1, the resistance value of resistor R3, and the resistance value of resistor R2 RV2 increases, the duration of the RDT period increases.

[0082] For example, when the capacitance of capacitor C1 increases and the resistance of resistor R3 increases or remains constant, the duration of RDT increases.

[0083] To give another example, if the capacitance of capacitor C1 increases and the resistance of resistor R2 increases or remains constant, the duration of RDT increases.

[0084] When at least one of the capacitance value of capacitor C1, the resistance value of resistor R3, and the resistance value of resistor R2 RV2 decreases, the duration of RDT decreases.

[0085] For example, when the capacitance of capacitor C1 decreases and the resistance of resistor R3 decreases or remains constant, the duration of RDT decreases.

[0086] To give another example, the capacitance of capacitor C1 decreases, and the resistance of resistor R2 decreases or remains constant, during which the duration of RDT decreases.

[0087] In some embodiments, the duration of the RDT is determined based on the voltage value V24, and the voltage value V23 is determined based on the voltage value V24.

[0088] For example, as the voltage value V24 increases, the duration of the RDT increases.

[0089] In some embodiments, voltage value V23 is the same as voltage value V24.

[0090] At time T22, the voltage level of voltage signal GV1 is less than the gate threshold voltage value VGSTH, and switch QM1 starts to turn on to increase the voltage level of power supply output signal VOUT.

[0091] During the period RT, the voltage level of the power supply output signal VOUT continuously rises from the voltage value V27 to the voltage value V28.

[0092] In some embodiments, the duration of RT depends on the rate of rise of the voltage level of the power output signal VOUT.

[0093] The rate at which the voltage level of the power output signal VOUT rises depends on the rate at which the voltage level of the voltage signal GV1 falls.

[0094] The rate at which the voltage level of voltage signal GV1 decreases depends on the discharge rate of capacitor C1.

[0095] When at least one of the capacitance value of capacitor C1, the resistance value of resistor R3, and the resistance value of resistor R2 RV2 increases, the duration of the RT period increases.

[0096] For example, when the capacitance of capacitor C1 increases and the resistance of resistor R3 increases or remains constant, the duration of RT increases.

[0097] To give another example, the capacitance of capacitor C1 increases, and the resistance of resistor R2 increases or remains constant, while the duration of RT increases.

[0098] When at least one of the capacitance value of capacitor C1, the resistance value of resistor R3, and the resistance value of resistor R2 RV2 decreases, the duration of the RT period decreases.

[0099] For example, when the capacitance of capacitor C1 decreases and the resistance of resistor R3 decreases or remains constant, the duration of RT during this period decreases.

[0100] To give another example, the capacitance of capacitor C1 decreases, and the resistance of resistor R2 decreases or remains constant, during which the duration of RT decreases.

[0101] At time T23, the voltage level of the power supply output signal VOUT begins to be maintained at the voltage value V28.

[0102] Figure 3 This is an operational timing diagram illustrating the charging of capacitor C1 in a power supply device 100 according to some embodiments of the present invention. In some embodiments, the power supply device 100 generates a voltage signal RV1 at node N1 and a voltage signal GV1 at node NC based on an enable signal EN, and switch QM1 generates a power output signal VOUT based on the voltage signal GV1.

[0103] At time T24, the voltage level of voltage signal RV1 is voltage value V210, and the voltage level of voltage signal GV1 is voltage value V211. Voltage values ​​V210 and V211 are determined by the ratio formed by the resistance value RV1 of resistor R1 and the resistance value RV2 of resistor R2.

[0104] Please refer to Figure 3 The timing diagram 300 includes voltage signal GV1, enable signal EN, voltage signal RV1 and power output signal VOUT.

[0105] At time T31, the voltage level of the enable signal EN increases from voltage value V32 to voltage value V31 to increase the voltage level of the switch control signal CV3, and switch QB2 is turned on according to the voltage level of node N3.

[0106] When switch QB2 is turned on, the voltage level of switch control signal CV2 decreases, and switch QB1 is turned off according to the voltage level of node N2.

[0107] When switch QB1 is turned off, the voltage level of switch control signal CV1 and the voltage level of voltage signal RV1 increase.

[0108] In some embodiments, when switch QB1 is turned on, the voltage level at node N1 increases according to the voltage level at node NI.

[0109] When switch QB1 is turned on, capacitor C1 charges according to the voltage level at node N1. While capacitor C1 is charging, the voltage level of the switch control signal GV1 increases.

[0110] In some embodiments, the voltage level of voltage signal RV1 at time T31 is voltage value V33, and the voltage level of voltage signal GV1 at time T31 is voltage value V34. Both voltage values ​​V33 and V34 are determined based on the ratio formed by the resistance value RV1 of resistor R1 and the resistance value RV2 of resistor R2.

[0111] In some embodiments, the voltage level of voltage signal RV1 at time T31 is the same as the voltage level of voltage signal GV1 at time T31.

[0112] In some embodiments, voltage value V32 is the same as voltage value V29 at time T24 in timing diagram 200. Voltage value V33 is the same as voltage value V210 at time T24 in timing diagram 200. Voltage value V34 is the same as voltage value V211 at time T24 in timing diagram 200.

[0113] During FDT, the voltage level of voltage signal RV1 rises from voltage value V33 to voltage value V35. The voltage level of voltage signal GV1 rises from voltage value V34 to voltage value V36.

[0114] In some embodiments, the duration of the FDT depends on the rise rate of the voltage levels of voltage signals RV1 and GV1.

[0115] The rate of rise of the voltage levels of voltage signals RV1 and GV1 depends on the charging rate of capacitor C1.

[0116] The charging speed of capacitor C1 depends on the capacitance value of capacitor C1, the resistance value of resistor R1 (RV1), and the resistance value of resistor R3.

[0117] When at least one of the capacitance value of capacitor C1, the resistance value of resistor R1, and the resistance value of resistor R3 increases, the duration of FDT increases.

[0118] For example, when the capacitance of capacitor C1 increases and the resistance of resistor R3 increases or remains constant, the duration of FDT increases.

[0119] To give another example, the capacitance of capacitor C1 increases, and the resistance of resistor R1 increases or remains constant, during which the duration of FDT increases.

[0120] When one of the capacitance value of capacitor C1, the resistance value of resistor R1, and the resistance value of resistor R3 decreases, while the other two remain constant, the duration of FDT decreases.

[0121] For example, when the capacitance of capacitor C1 decreases and the resistance of resistor R3 decreases or remains constant, the duration of FDT decreases.

[0122] To give another example, if the capacitance of capacitor C1 increases and the resistance of resistor R1 decreases or remains constant, the duration of FDT decreases.

[0123] In some embodiments, the duration of the FDT is determined based on voltage values ​​V33 and V44.

[0124] For example, when voltage values ​​V33 and V44 decrease, the duration of FDT increases.

[0125] At time T32, switch QM1 begins to turn off to reduce the voltage level of the power supply output signal VOUT.

[0126] In some embodiments, the voltage value V37 is the same as the voltage value V28 at time T23 in timing diagram 200.

[0127] During the FT period, the voltage level of the power output signal VOUT continuously decreases from voltage value V37 to voltage value V38.

[0128] In some embodiments, the duration of the FT period is determined by the rate at which the voltage level of the power supply output signal VOUT decreases.

[0129] The rate at which the voltage level of the power output signal VOUT decreases depends on the rate at which the voltage level of the voltage signal GV1 increases.

[0130] The rate at which the voltage level of voltage signal GV1 rises depends on the charging rate of capacitor C1.

[0131] When at least one of the capacitance value of capacitor C1, the resistance value of resistor R1, and the resistance value of resistor R3 increases, the duration of the FT period increases.

[0132] For example, when the capacitance of capacitor C1 increases and the resistance of resistor R3 increases or remains constant, the duration of FT increases.

[0133] To give another example, the capacitance of capacitor C1 increases, and the resistance of resistor R1 increases or remains constant, during which the time length of FT increases.

[0134] When at least one of the capacitance value of capacitor C1, the resistance value of resistor R1, and the resistance value of resistor R3 decreases, the duration of the FT period decreases.

[0135] For example, when the capacitance of capacitor C1 decreases and the resistance of resistor R3 decreases or remains constant, the duration of FT decreases.

[0136] To give another example, the capacitance of capacitor C1 decreases, and the resistance of resistor R1 decreases or remains constant, during which the duration of FT decreases.

[0137] At time T33, the voltage level of the power supply output signal VOUT begins to be maintained at the voltage value V38.

[0138] In some practices, the DC switching circuit is designed only to directly input the switching control signal to the gate of the DC power switch to control the power output signal, and the DC switching circuit is designed only to turn on the DC switch at a high potential.

[0139] Compared to the above approach, in this embodiment of the present invention, the power supply device 100 can output a switch control signal CV1 to the DC power switch circuit 110 through a multi-stage switch, such as switches QB1 and QB2, to adjust the rise / fall period of the power output signal VOUT. Furthermore, the power supply device 100 can design the DC switch circuit 110 to conduct the DC switch at a low potential, such as switch QM1, so that the voltage level of the power output signal VOUT remains stable in the initial timing sequence.

[0140] Figure 4 This is a schematic diagram of a power supply device 100 according to some embodiments of the present invention. In some embodiments, the power supply device 100 is used to generate a power output signal VOUT based on an enable signal EN and a power input signal VIN. Please refer to... Figure 4The power supply device 100 includes a DC power switch circuit 110, a switch control circuit 120, and a resistor R7.

[0141] like Figure 4 As shown, the functions and operations of each of the DC power supply switching circuit 110 and the switching control circuit 120 are as follows: Figure 1 The functions and connections are the same, so they will not be described in detail.

[0142] Compared to Figure 1 ,exist Figure 4 In the illustrated embodiment, one end of resistor R7 is coupled to switch control circuit 120 at node N2, and the other end of resistor R7 is used to receive enable signal EN. The base terminal of switch QB1 is used to receive switch control signal CV3 at node N2.

[0143] The aforementioned operating methods of various power switch circuits are for illustrative purposes only; the operating methods of other power switch circuits are all within the scope of this case.

[0144] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A power supply device characterized by comprising: Include: A first switch control circuit is used to generate an output voltage signal based on a first voltage signal and an input voltage signal; The first switch control circuit includes: A first switch, wherein a first terminal of the first switch is used to receive the input voltage signal at an input node; A first resistor, one end of which is coupled to the input node, and the other end of which is coupled to a first node; A second resistor, one end of which is coupled to a second terminal of the first switch to a control node, and the other end of which is coupled to the first node; as well as A first capacitor, one end of which is coupled to the control node and the other end of which is coupled to the input node, is used to charge or discharge according to the first voltage signal to adjust the voltage level of the control node, wherein the first switch adjusts the voltage level of the output voltage signal according to the voltage level of the control node.

2. The power supply apparatus according to claim 1, wherein Also includes: A second switch control circuit is used to receive a second voltage signal and output the first voltage signal. The second switch control circuit includes: A second switch, wherein a first terminal of the second switch is used to output the first voltage signal to the first switch control circuit, and a second terminal of the second switch is used to receive the second voltage signal; and A third resistor, one end of which is coupled to the input voltage signal, and the other end of which is coupled to the second terminal of the second switch.

3. The power supply device as described in claim 2, characterized in that, in When the second switch is turned on, the voltage level of the first node decreases according to the resistance values ​​of the first resistor and a fourth resistor, wherein one end of the fourth resistor is coupled to the first node and the other end of the fourth resistor is coupled to the first terminal of the second switch.

4. The power supply device as claimed in claim 2, characterized in that, Also includes: A third switch control circuit is used to receive a third voltage signal and output the second voltage signal, wherein the third switch control circuit includes: A third switch, wherein a first terminal of the third switch is used to output the second voltage signal to the second switch control circuit, and a second terminal of the third switch is used to receive the third voltage signal; and A fourth resistor, one end of which is coupled to the input voltage signal, and the other end of which is coupled to the second terminal of the third switch.

5. The power supply device as claimed in claim 4, characterized in that, When the third switch is turned off The second switch is turned on and the voltage level of the first node decreases, and The first capacitor discharges according to the voltage level of the first node to turn on the first switch.

6. The power supply device as claimed in claim 5, characterized in that, When the first switch is turned on, the voltage level of the output voltage signal continuously rises during a first period.

7. The power supply device as claimed in claim 6, characterized in that, When at least one of the capacitance value of the first capacitor and the resistance value of the second resistor increases, the duration of the first period increases.

8. The power supply device as claimed in claim 4, characterized in that, When the third switch is turned on The second switch is turned off and the voltage level of the first node rises, and The first capacitor is charged according to the voltage level of the first node to turn off the first switch.

9. The power supply device as claimed in claim 8, characterized in that, When the first switch begins to turn off, the voltage level of the output voltage signal continuously decreases during a second period.

10. The power supply device as claimed in claim 9, characterized in that, When at least one of the capacitance value of the first capacitor and the resistance value of the second resistor increases, the duration of the second period increases.

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