Control equipment

Abstract

This utility model discloses a control device and a vehicle. The control device may include: a controller, a control circuit, a first bridge arm, and a second bridge arm, which are respectively deployed at different positions within the control device. The controller is used to send an initial electrical signal; the control circuit, connected to the controller, is used to convert the initial electrical signal into a target electrical signal; the first bridge arm, connected to the control circuit, is used to respond to a first target electrical signal in the target electrical signal to trigger and complete the drive; the second bridge arm, connected to the control circuit, is used to respond to a second target electrical signal in the target electrical signal to trigger and complete the drive; wherein the first target electrical signal and the second target electrical signal are interlocked. This utility model solves the technical problem of high risk of circuit failure.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuits, and more specifically, to a control device and a vehicle. Background Technology

[0002] Since silicon carbide (SIC) and insulated-gate bipolar transistors (IGBTs) have different turn-on and turn-off times, required dead times, and turn-on and turn-off voltages, two pulse width modulation (PWM) waves are usually used to drive the parallel SIC and IGBTs respectively.

[0003] However, the above driving method may lead to untimely PWM control when the microcontroller unit (MCU) is under excessive load, which could result in a high risk of circuit failure.

[0004] There is currently no effective solution to the technical problem of the high risk of device explosion caused by the aforementioned circuit. Utility Model Content

[0005] This utility model provides a control device and vehicle to at least solve the technical problem of high risk of circuit failure.

[0006] According to one aspect of the present invention, a control device is provided, which may include: a controller, a control circuit, a first bridge arm, and a second bridge arm, wherein the first bridge arm and the second bridge arm are respectively deployed at different positions in the control device, wherein the controller is used to send an initial electrical signal; the control circuit is connected to the controller and is used to convert the initial electrical signal into a target electrical signal; the first bridge arm is connected to the control circuit and is used to respond to a first target electrical signal in the target electrical signal to trigger and complete the drive; the second bridge arm is connected to the control circuit and is used to respond to a second target electrical signal in the target electrical signal to trigger and complete the drive; wherein the first target electrical signal and the second target electrical signal are interlocked.

[0007] Optionally, the control circuit includes a delay sub-circuit, a NOT gate, and a first AND gate. The delay sub-circuit, connected to the NOT gate, is used to perform delay operations on the first initial electrical signal and the second initial electrical signal in the initial electrical signal, respectively. The first initial electrical signal is an electrical signal that allows action on the semiconductor chip in the second bridge arm, and the second initial electrical signal is an electrical signal that allows action on the bipolar chip in the second bridge arm. The NOT gate, connected to the first AND gate, is used to perform inversion operations on the delayed first initial electrical signal and the delayed second initial electrical signal, respectively. The first AND gate, connected to the first bridge arm, is used to perform AND operations on the inverted first initial electrical signal, the inverted second initial electrical signal, and the third initial electrical signal in the initial electrical signal, respectively, to obtain the first driving electrical signal in the first target electrical signal. The third initial electrical signal is an electrical signal that allows action on the semiconductor chip in the first bridge arm, and the first driving electrical signal is used to drive the semiconductor chip in the first bridge arm.

[0008] Optionally, the delay sub-circuit is configured to perform delay operations on the first initial electrical signal and the second initial electrical signal respectively in response to the current dead time of the controller being greater than the preset dead time; and to perform delay operations on the first initial electrical signal and the second initial electrical signal respectively after performing a hardware dead time insertion operation on the first initial electrical signal and the second initial electrical signal in response to the current dead time being less than or equal to the preset dead time.

[0009] Optionally, the delay sub-circuit includes a first delay sub-circuit and a second delay sub-circuit, wherein the first delay sub-circuit is connected to the controller and is used to perform a delay operation on the first initial electrical signal; the second delay sub-circuit is connected to the controller and is used to perform a delay operation on the second initial electrical signal.

[0010] Optionally, the NOT gate includes a first NOT gate and a second NOT gate, wherein the first NOT gate is connected to the first delay sub-circuit and is used to perform an inversion operation on the delayed first initial electrical signal; the second NOT gate is connected to the second delay sub-circuit and is used to perform an inversion operation on the delayed second initial electrical signal.

[0011] Optionally, the control circuit further includes a second AND gate, wherein a delay sub-circuit, connected to a NAND gate, is used to perform delay operations on the third initial electrical signal and the fourth initial electrical signal in the initial electrical signal, respectively, wherein the fourth initial electrical signal is an electrical signal that allows the bipolar chip in the first bridge arm to act; a NOT gate, connected to the second AND gate, is used to perform inversion operations on the delayed third initial electrical signal and the delayed fourth initial electrical signal, respectively; and a second AND gate, connected to the second bridge arm, is used to perform a bitwise AND operation on the inverted third initial electrical signal, the inverted fourth initial electrical signal, and the first initial electrical signal to obtain the second driving electrical signal in the second target electrical signal, wherein the second driving electrical signal is used to drive the semiconductor chip in the second bridge arm.

[0012] Optionally, the delay sub-circuit is used to perform delay operations on the third initial electrical signal and the fourth initial electrical signal respectively in response to the current dead time of the controller being greater than the preset dead time; and to perform delay operations on the third initial electrical signal and the fourth initial electrical signal respectively after performing a hardware dead time insertion operation on the third initial electrical signal and the fourth initial electrical signal in response to the current dead time being less than or equal to the preset dead time.

[0013] Optionally, the delay sub-circuit includes a third delay sub-circuit and a fourth delay sub-circuit, wherein the third delay sub-circuit is connected to the controller and is used to acquire a third initial electrical signal and perform a delay operation on the third initial electrical signal; the fourth delay sub-circuit is connected to the controller and is used to acquire a fourth initial electrical signal and perform a delay operation on the fourth initial electrical signal.

[0014] Optionally, the NOT gate includes a third NOT gate and a fourth NOT gate, wherein the third NOT gate is connected to the third delay sub-circuit and is used to perform an inversion operation on the delayed third initial electrical signal; the fourth NOT gate is connected to the fourth delay sub-circuit and is used to perform an inversion operation on the delayed fourth initial electrical signal.

[0015] Optionally, the control circuit further includes a third AND gate, wherein a delay sub-circuit, connected to a NAND gate, is used to perform delay operations on the third initial electrical signal and the fourth initial electrical signal respectively; a NOT gate, connected to the third AND gate, is used to perform inversion operations on the delayed third initial electrical signal and the delayed fourth initial electrical signal respectively; and a third AND gate, connected to the second bridge arm, is used to perform AND operations on the inverted third initial electrical signal, the inverted fourth initial electrical signal, and the second initial electrical signal to obtain the third driving electrical signal in the second target electrical signal, wherein the third driving electrical signal is used to drive the bipolar chip in the second bridge arm.

[0016] Optionally, the second bridge arm is used to respond to the second drive electrical signal and the third drive electrical signal in the second target electrical signal to complete the drive.

[0017] Optionally, the control circuit further includes a fourth AND gate, wherein the delay sub-circuit is connected to the NAND gate and is used to perform delay operations on the first initial electrical signal and the second initial electrical signal respectively; the NOT gate is connected to the fourth AND gate and is used to perform inversion operations on the delayed first initial electrical signal and the delayed second initial electrical signal respectively; the fourth AND gate is connected to the first bridge arm and is used to perform AND operations on the inverted first initial electrical signal, the inverted second initial electrical signal and the fourth initial electrical signal to obtain the fourth driving electrical signal in the first target electrical signal, wherein the fourth driving electrical signal is used to drive the bipolar chip in the first bridge arm.

[0018] Optionally, the first bridge arm is used to respond to the first drive signal and the fourth drive signal in the first target electrical signal to complete the drive.

[0019] According to another aspect of the present invention, a vehicle is also provided, comprising: a memory storing an executable program; and a processor for running the program, wherein the program controls the control device of any of the above-mentioned items when it is running.

[0020] In this embodiment of the invention, when the bridge arm is driven using a control device, the controller can send an initial electrical signal, and the control circuit connected to the controller can convert the initial electrical signal into a target electrical signal. The first bridge arm connected to the control circuit can be triggered by the first target electrical signal in the target electrical signal to complete the drive, and the second bridge arm connected to the control circuit can be triggered by the second target electrical signal in the target electrical signal to complete the drive. Because in this embodiment of the invention, after the control circuit converts the initial electrical signal sent by the controller into a target electrical signal, the first bridge arm can be triggered by the first target electrical signal in the target electrical signal to complete the drive, and the second bridge arm can be triggered by the second target electrical signal in the target electrical signal to complete the drive, the purpose of avoiding untimely PWM control is achieved, thereby solving the technical problem of high risk of circuit failure and realizing the technical effect of reducing the risk of circuit failure. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of the present invention and constitute a part of this invention, illustrate exemplary embodiments of the present invention and, together with the description thereof, serve to explain the present invention and do not constitute an undue limitation thereof. In the drawings:

[0022] Figure 1 This is a schematic diagram of a control device according to an embodiment of the present utility model;

[0023] Figure 2(a) is a schematic diagram of a half-bridge structure according to the related art;

[0024] Figure 2(b) is a schematic diagram of a hardware shoot-through protection circuit for driving a hybrid switch of SI IGBT and SiC MOSFET according to an embodiment of the present invention;

[0025] Figure 2(c) is a schematic diagram of a waveform transmitted by an MCU according to an embodiment of the present invention;

[0026] Figure 2(d) is a schematic diagram of a waveform after delay processing according to an embodiment of the present invention;

[0027] Figure 2(e) is a schematic diagram of a waveform obtained by taking the AND operation according to an embodiment of the present invention;

[0028] Figure 2(f) is a schematic diagram of an abnormal waveform of MCU transmission dead zone according to an embodiment of the present invention;

[0029] Figure 2(g) is a schematic diagram of an abnormal waveform after delay processing according to an embodiment of the present invention;

[0030] Figure 2(h) is a schematic diagram of an abnormal waveform after taking an AND operation according to an embodiment of the present invention;

[0031] Figure 2(i) is a schematic diagram of data interaction between a vehicle and a server according to an embodiment of the present invention;

[0032] Figure 3 This is a structural block diagram of a vehicle according to an embodiment of the present utility model. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a system, product, or device comprising a series of units is not necessarily limited to those explicitly listed, but may include other units not explicitly listed or inherent to such products or devices.

[0035] Figure 1 This is a schematic diagram of a control device according to an embodiment of the present utility model. The control device 100 may include: a controller 101, a control circuit 102, a first bridge arm 103 and a second bridge arm 104, wherein the first bridge arm 103 and the second bridge arm 104 are respectively deployed in different positions in the control device.

[0036] Controller 101 is used to send an initial electrical signal.

[0037] In the technical solution provided by the controller 101 of this utility model, the controller 101 can be represented by an MCU.

[0038] In this embodiment, the initial electrical signal may include: an electrical signal that allows action on the semiconductor chip in the bridge arm, and an electrical signal that allows action on the bipolar chip in the bridge arm. For example, the semiconductor chip may be a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) chip, and the bipolar chip may be a silicon insulated gate bipolar transistor (SI IGBT) chip. This is only an example and is not a specific limitation.

[0039] In this embodiment, in the control device described above, a controller connected to the control circuit can send an initial electrical signal generated by the controller to the control circuit. That is, the controller can send an electrical signal that allows action on the semiconductor chip in the bridge arm to the control circuit, and the controller can also send an electrical signal that allows action on the bipolar chip in the bridge arm to the control circuit.

[0040] The control circuit 102, connected to the controller, is used to convert the initial electrical signal into the target electrical signal.

[0041] In the technical solution provided by the control circuit 102 of this utility model, the control circuit 102 may include: a delay sub-circuit, a NOT gate, and an AND gate, etc.

[0042] In this embodiment, the target electrical signal can be used to represent the electrical signals output from the AND gate of the control circuit.

[0043] In this embodiment, after the controller sends an initial electrical signal, a control circuit connected to the controller can receive the initial electrical signal sent by the controller. After receiving the initial electrical signal sent by the controller, the control circuit connected to the controller can convert the received initial electrical signal into a target electrical signal. That is, by performing a signal conversion operation on the initial electrical signal received from the controller through the control circuit connected to the controller, the target electrical signal can be obtained. The conversion operation can include: a turn-off delay operation, an inversion operation, and an AND operation.

[0044] The first bridge arm 103 is connected to the control circuit and is used to respond to the first target electrical signal in the target electrical signal to complete the drive.

[0045] In the technical solution provided by the first bridge arm 103 of this utility model, the first bridge arm 103 can be used to represent the upper bridge arm in the control device.

[0046] In this embodiment, the aforementioned first target electrical signal can be used to represent a signal driving the first bridge arm. The first target electrical signal may include a driving electrical signal for driving a semiconductor chip in the first bridge arm, and a driving electrical signal for driving a bipolar chip in the first bridge arm.

[0047] In this embodiment, after the control circuit converts the initial electrical signal into a target electrical signal, the first target electrical signal is input to the first bridge arm connected to the control circuit. The first bridge arm connected to the control circuit can be triggered by the first target electrical signal to complete the drive. That is, the semiconductor chip in the first bridge arm can be triggered by the drive electrical signal driving the semiconductor chip in the first bridge arm to complete the drive, and the bipolar chip in the first bridge arm can be triggered by the drive electrical signal driving the bipolar chip in the first bridge arm to complete the drive.

[0048] The second bridge arm 104 is connected to the control circuit and is used to respond to the triggering of the second target electrical signal in the target electrical signal to complete the drive.

[0049] In the technical solution provided by the second bridge arm 104 of this utility model, the second bridge arm 104 can be used to represent the lower half bridge arm in the control device.

[0050] In this embodiment, the aforementioned second target electrical signal can be used to represent a signal driving the second bridge arm. The second target electrical signal may include a driving electrical signal for driving the semiconductor chip in the second bridge arm, and a driving electrical signal for driving the bipolar chip in the second bridge arm.

[0051] In this embodiment, the first target electrical signal can be interlocked with the second target electrical signal. That is, the driving electrical signal of the semiconductor chip in the first bridge arm of the first target electrical signal can be interlocked with the driving electrical signal of the semiconductor chip in the second bridge arm of the second target electrical signal, and the driving electrical signal of the bipolar chip in the first bridge arm of the first target electrical signal can be interlocked with the driving electrical signal of the bipolar chip in the second bridge arm of the second target electrical signal.

[0052] In this embodiment, after the control circuit converts the initial electrical signal into a target electrical signal, a second target electrical signal from the target electrical signal is input to the second bridge arm connected to the control circuit. The second bridge arm connected to the control circuit can be triggered in response to the second target electrical signal to complete the drive. That is, the semiconductor chip in the second bridge arm can be triggered in response to the drive electrical signal of the semiconductor chip in the second bridge arm to complete the drive, and the bipolar chip in the second bridge arm can be triggered in response to the drive electrical signal of the bipolar chip in the second bridge arm to complete the drive.

[0053] In the control device of this utility model, when the control device is used to drive the bridge arms, the controller can be used to send an initial electrical signal, and the control circuit connected to the controller can be used to convert the initial electrical signal into a target electrical signal. The first bridge arm connected to the control circuit can be triggered by the first target electrical signal in the target electrical signal to complete the drive, and the second bridge arm connected to the control circuit can be triggered by the second target electrical signal in the target electrical signal to complete the drive. Since in this embodiment of the utility model, after the control circuit converts the initial electrical signal sent by the controller into a target electrical signal, the first bridge arm can be triggered by the first target electrical signal in the target electrical signal to complete the drive, and the second bridge arm can be triggered by the second target electrical signal in the target electrical signal to complete the drive, the purpose of avoiding untimely PWM control is achieved, thereby solving the technical problem of high risk of circuit failure and realizing the technical effect of reducing the risk of circuit failure.

[0054] The control device described in this embodiment will be further described below.

[0055] As an optional embodiment, the control circuit includes a delay sub-circuit, a NOT gate, and a first AND gate. The delay sub-circuit is connected to the NOT gate and is used to perform delay operations on the first initial electrical signal and the second initial electrical signal in the initial electrical signal, respectively. The NOT gate is connected to the first AND gate and is used to perform inversion operations on the delayed first initial electrical signal and the delayed second initial electrical signal, respectively. The first AND gate is connected to the first bridge arm and is used to perform AND operations on the inverted first initial electrical signal, the inverted second initial electrical signal, and the third initial electrical signal in the initial electrical signal, respectively, to obtain the first driving electrical signal in the first target electrical signal.

[0056] In this embodiment, the control circuit may include a delay sub-circuit, a NOT gate, and a first AND gate. The delay sub-circuit may be a turn-off delay circuit, which can be used to perform a turn-off delay operation on the initial electrical signal received from the controller. The first AND gate may be connected to a semiconductor chip in the first bridge arm; for example, the first AND gate may be connected to an SI MOSFET chip in the upper bridge arm.

[0057] In this embodiment, the first initial electrical signal can be an electrical signal that allows the semiconductor chip in the second bridge arm to act. For example, the first initial electrical signal can be represented by PWM_SIC_L. This is only an example and is not a specific limitation.

[0058] In this embodiment, the second initial electrical signal can be an electrical signal that allows the bipolar chip in the second bridge arm to operate. For example, the second initial electrical signal can be represented by PWM_IGBT_L. This is only an example and is not specifically limited.

[0059] In this embodiment, after the controller sends the initial electrical signal, the delay sub-circuit connected to the NAND gate can receive the initial electrical signal sent by the controller, and can perform a turn-off delay operation on the first initial electrical signal and the second initial electrical signal in the received initial electrical signal respectively, thereby achieving the purpose of delaying the initial electrical signal and realizing the technical effect of delaying the conduction time of the circuit.

[0060] In this embodiment, after the delay sub-circuit performs delay operations on the first and second initial electrical signals in the initial electrical signals respectively, the delayed first and second initial electrical signals are input to the NOT gate connected to the first AND gate. Then, the NOT gate connected to the first AND gate can perform inversion operations on the delayed first and second initial electrical signals respectively, thereby achieving the purpose of inverting the initial electrical signals and realizing the technical effect of improving the effectiveness of signal conversion operations.

[0061] In this embodiment, the aforementioned third initial electrical signal can be an electrical signal that allows action on the semiconductor chip in the first bridge arm. For example, the aforementioned third initial electrical signal can be represented by PWM_SIC_H. This is only an example and is not a specific limitation.

[0062] In this embodiment, the first driving electrical signal can be used to drive the semiconductor chip in the first bridge arm. For example, the first driving electrical signal can be used to drive the SiC MOSFET chip in the upper bridge arm. The first driving electrical signal can be represented by DRIVE_PWM_SIC_H, which is only an example and not a specific limitation.

[0063] In this embodiment, after the NOT gate performs inversion operations on the delayed first initial electrical signal and the delayed second initial electrical signal respectively, the inverted first initial electrical signal, the inverted second initial electrical signal, and the third initial electrical signal in the initial electrical signal are input to the first AND gate connected to the first bridge arm. The first AND gate connected to the first bridge arm performs AND operations on the inverted first initial electrical signal, the inverted second initial electrical signal, and the third initial electrical signal in the initial electrical signal respectively, and the first driving electrical signal in the first target electrical signal can be obtained. This achieves the purpose of converting the initial electrical signal into the target electrical signal and realizes the technical effect of improving the accuracy of the signal conversion operation.

[0064] The delay sub-circuit described in this embodiment will be further explained below.

[0065] As an optional embodiment, a delay sub-circuit is used to perform delay operations on the first initial electrical signal and the second initial electrical signal respectively in response to the current dead time of the controller being greater than a preset dead time; and to perform delay operations on the first initial electrical signal and the second initial electrical signal respectively after performing a hardware dead time insertion operation on the first initial electrical signal and the second initial electrical signal in response to the current dead time being less than or equal to the preset dead time.

[0066] In this embodiment, the aforementioned current dead time can be used to represent the dead time of the PWM signal issued by the software through the controller. The aforementioned preset dead time can be used to represent the dead time set by the hardware, and the dead time set by the hardware is adjustable.

[0067] In this embodiment, after the controller sends the initial electrical signal, the relationship between the current dead time of the controller and the preset dead time is determined. If it is determined that the current dead time of the controller is longer than the preset dead time, the delay sub-circuit can perform a turn-off delay operation on the first initial electrical signal and the second initial electrical signal respectively, thereby achieving the purpose of delaying the initial electrical signal and realizing the technical effect of delaying the conduction time of the circuit.

[0068] In this embodiment, after the controller sends the initial electrical signal, the relationship between the controller's current dead time and the preset dead time is determined. If the controller's current dead time is less than or equal to the preset dead time, a hardware dead time insertion operation is performed on the first and second initial electrical signals. After the hardware dead time insertion operation is completed, the delay sub-circuit performs a turn-off delay operation on the inserted first and second initial electrical signals, respectively. This achieves the purpose of delaying the initial electrical signal and realizes the technical effect of delaying the circuit's conduction time.

[0069] The delay sub-circuit described in this embodiment will be further explained below.

[0070] As an optional embodiment, the delay sub-circuit includes a first delay sub-circuit and a second delay sub-circuit, wherein the first delay sub-circuit is connected to the controller and is used to perform a delay operation on a first initial electrical signal; the second delay sub-circuit is connected to the controller and is used to perform a delay operation on a second initial electrical signal.

[0071] In this embodiment, the aforementioned delay sub-circuit may include a first delay sub-circuit and a second delay sub-circuit. The first delay sub-circuit can be used to represent a circuit that delays a first initial electrical signal, and the second delay sub-circuit can be used to represent a circuit that delays a second initial electrical signal.

[0072] In this embodiment, after the controller sends the initial electrical signal, the first delay sub-circuit connected to the controller receives the first initial electrical signal in the initial electrical signal and performs a turn-off delay operation on the received first initial electrical signal, thereby achieving the purpose of delaying the first initial electrical signal and realizing the technical effect of delaying the conduction time of the circuit.

[0073] In this embodiment, after the controller sends the initial electrical signal, the second delay sub-circuit connected to the controller receives the second initial electrical signal in the initial electrical signal and performs a turn-off delay operation on the received second initial electrical signal, thereby achieving the purpose of delaying the second initial electrical signal and realizing the technical effect of delaying the conduction time of the circuit.

[0074] The NOT gate described in this embodiment will be further explained below.

[0075] As an optional embodiment, the NOT gate includes a first NOT gate and a second NOT gate, wherein the first NOT gate is connected to a first delay sub-circuit and is used to perform an inversion operation on the delayed first initial electrical signal; the second NOT gate is connected to a second delay sub-circuit and is used to perform an inversion operation on the delayed second initial electrical signal.

[0076] In this embodiment, the aforementioned NOT gate may include a first NOT gate and a second NOT gate, wherein the first NOT gate is the NOT gate through which the first initial electrical signal needs to pass, and the second NOT gate is the NOT gate through which the second initial electrical signal needs to pass.

[0077] In this embodiment, after the delay sub-circuit performs delay operations on the first initial electrical signal and the second initial electrical signal in the initial electrical signal respectively, the delayed first initial electrical signal is input to the first NOT gate connected to the first delay sub-circuit. After the first NOT gate connected to the first delay sub-circuit receives the delayed first initial electrical signal, it performs an inversion operation on the delayed first initial electrical signal, thereby achieving the purpose of inverting the first initial electrical signal and realizing the technical effect of delaying the conduction time of the circuit.

[0078] In this embodiment, after the delay sub-circuit performs delay operations on the first initial electrical signal and the second initial electrical signal in the initial electrical signal respectively, the delayed second initial electrical signal is input to the second NOT gate connected to the second delay sub-circuit. After the second NOT gate connected to the second delay sub-circuit receives the delayed second initial electrical signal, it performs an inversion operation on the delayed second initial electrical signal, thereby achieving the purpose of inverting the second initial electrical signal and realizing the technical effect of delaying the conduction time of the circuit.

[0079] The control circuit described in this embodiment will be further explained below.

[0080] As an optional embodiment, the control circuit further includes a second AND gate, wherein the delay sub-circuit is connected to the NAND gate and is used to perform delay operations on the third initial electrical signal and the fourth initial electrical signal in the initial electrical signal, respectively; the NOT gate is connected to the second AND gate and is used to perform inversion operations on the delayed third initial electrical signal and the delayed fourth initial electrical signal, respectively; the second AND gate is connected to the second bridge arm and is used to perform AND operations on the inverted third initial electrical signal, the inverted fourth initial electrical signal and the first initial electrical signal to obtain the second driving electrical signal in the second target electrical signal.

[0081] In this embodiment, the control circuit may further include a second AND gate, wherein the second AND gate may be connected to a semiconductor chip in the second bridge arm, for example, the second AND gate may be connected to a SiC MOSFET chip in the lower half-bridge arm.

[0082] In this embodiment, the aforementioned fourth initial electrical signal can be an electrical signal that allows the bipolar chip in the first bridge arm to operate. For example, the aforementioned fourth initial electrical signal can be represented by PWM_IGBT_H. This is only an example and is not specifically limited.

[0083] In this embodiment, after the controller sends the initial electrical signal, the delay sub-circuit connected to the NAND gate can receive the initial electrical signal sent by the controller, and can perform turn-off delay operations on the third and fourth initial electrical signals in the received initial electrical signal respectively, thereby achieving the purpose of delaying the initial electrical signal and realizing the technical effect of delaying the conduction time of the circuit.

[0084] In this embodiment, after the delay sub-circuit performs delay operations on the third and fourth initial electrical signals in the initial electrical signal, the delayed third and fourth initial electrical signals are input to the NOT gate connected to the second AND gate. Then, the NOT gate connected to the second AND gate can perform inversion operations on the delayed third and fourth initial electrical signals, thereby achieving the purpose of inverting the initial electrical signals and realizing the technical effect of improving the effectiveness of signal conversion operations.

[0085] In this embodiment, the second driving signal can be used to drive the semiconductor chip in the second bridge arm. For example, the second driving signal can be used to drive the SiC MOSFET chip in the lower half-bridge arm. The second driving signal can be represented by DRIVE_PWM_SIC_L, which is only an example and not a specific limitation.

[0086] In this embodiment, after the NOT gate performs inversion operations on the delayed third initial electrical signal and the delayed fourth initial electrical signal respectively, the inverted third initial electrical signal, the inverted fourth initial electrical signal, and the first initial electrical signal in the initial electrical signal are input to the second AND gate connected to the second bridge arm. The second AND gate connected to the second bridge arm performs AND operations on the inverted third initial electrical signal, the inverted fourth initial electrical signal, and the first initial electrical signal in the initial electrical signal respectively, so as to obtain the second driving electrical signal in the second target electrical signal. This achieves the purpose of converting the initial electrical signal into the target electrical signal and realizes the technical effect of improving the accuracy of the signal conversion operation.

[0087] The delay sub-circuit described in this embodiment will be further explained below.

[0088] As an optional embodiment, a delay sub-circuit is used to perform delay operations on the third initial electrical signal and the fourth initial electrical signal respectively in response to the current dead time of the controller being greater than the preset dead time; and to perform delay operations on the third initial electrical signal and the fourth initial electrical signal respectively after performing a hardware dead time insertion operation on the third initial electrical signal and the fourth initial electrical signal in response to the current dead time being less than or equal to the preset dead time.

[0089] In this embodiment, after the controller sends the initial electrical signal, the relationship between the current dead time of the controller and the preset dead time is determined. If it is determined that the current dead time of the controller is longer than the preset dead time, the delay sub-circuit can perform a turn-off delay operation on the third initial electrical signal and the fourth initial electrical signal respectively, thereby achieving the purpose of delaying the initial electrical signal and realizing the technical effect of delaying the conduction time of the circuit.

[0090] In this embodiment, after the controller sends the initial electrical signal, the relationship between the controller's current dead time and the preset dead time is determined. If the controller's current dead time is less than or equal to the preset dead time, a hardware dead time insertion operation is performed on the third and fourth initial electrical signals. After the hardware dead time insertion operation is completed, the delay sub-circuit performs a turn-off delay operation on the inserted third and fourth initial electrical signals, respectively. This achieves the purpose of delaying the initial electrical signals and realizes the technical effect of delaying the circuit's conduction time.

[0091] The delay sub-circuit described in this embodiment will be further explained below.

[0092] As an optional embodiment, the delay sub-circuit includes a third delay sub-circuit and a fourth delay sub-circuit. The third delay sub-circuit is connected to the controller and is used to acquire a third initial electrical signal and perform a delay operation on the third initial electrical signal. The fourth delay sub-circuit is connected to the controller and is used to acquire a fourth initial electrical signal and perform a delay operation on the fourth initial electrical signal.

[0093] In this embodiment, the aforementioned delay sub-circuit includes a third delay sub-circuit and a fourth delay sub-circuit. The third delay sub-circuit can be used to represent a circuit that delays a third initial electrical signal, and the fourth delay sub-circuit can be used to represent a circuit that delays a fourth initial electrical signal.

[0094] In this embodiment, after the controller sends the initial electrical signal, the third delay sub-circuit connected to the controller receives the third initial electrical signal in the initial electrical signal and performs a turn-off delay operation on the received third initial electrical signal, thereby achieving the purpose of delaying the third initial electrical signal and realizing the technical effect of delaying the conduction time of the circuit.

[0095] In this embodiment, after the controller sends the initial electrical signal, the fourth delay sub-circuit connected to the controller receives the fourth initial electrical signal in the initial electrical signal and performs a turn-off delay operation on the received fourth initial electrical signal, thereby achieving the purpose of delaying the fourth initial electrical signal and realizing the technical effect of delaying the conduction time of the circuit.

[0096] The NOT gate described in this embodiment will be further explained below.

[0097] As an optional embodiment, the NOT gate includes a third NOT gate and a fourth NOT gate, wherein the third NOT gate is connected to the third delay sub-circuit and is used to perform an inversion operation on the delayed third initial electrical signal; the fourth NOT gate is connected to the fourth delay sub-circuit and is used to perform an inversion operation on the delayed fourth initial electrical signal.

[0098] In this embodiment, the aforementioned NOT gate may include a third NOT gate and a fourth NOT gate, wherein the third NOT gate is the NOT gate through which the third initial electrical signal needs to pass, and the fourth NOT gate is the NOT gate through which the fourth initial electrical signal needs to pass.

[0099] In this embodiment, after the delay sub-circuit performs delay operations on the third initial electrical signal and the fourth initial electrical signal in the initial electrical signal respectively, the delayed third initial electrical signal is input to the third NOT gate connected to the third delay sub-circuit. After the third NOT gate connected to the third delay sub-circuit receives the delayed third initial electrical signal, it performs an inversion operation on the delayed third initial electrical signal, thereby achieving the purpose of inverting the third initial electrical signal and realizing the technical effect of delaying the conduction time of the circuit.

[0100] In this embodiment, after the delay sub-circuit performs delay operations on the third and fourth initial electrical signals in the initial electrical signal respectively, the delayed fourth initial electrical signal is input to the fourth NOT gate connected to the fourth delay sub-circuit. After the fourth NOT gate connected to the fourth delay sub-circuit receives the delayed fourth initial electrical signal, it performs an inversion operation on the delayed fourth initial electrical signal, thereby achieving the purpose of inverting the fourth initial electrical signal and realizing the technical effect of delaying the conduction time of the circuit.

[0101] The control circuit described in this embodiment will be further explained below.

[0102] As an optional embodiment, the control circuit further includes a third AND gate, wherein a delay sub-circuit, connected to a NAND gate, is used to perform delay operations on the third initial electrical signal and the fourth initial electrical signal respectively; a NOT gate, connected to the third AND gate, is used to perform inversion operations on the delayed third initial electrical signal and the delayed fourth initial electrical signal respectively; and a third AND gate, connected to the second bridge arm, is used to perform AND operations on the inverted third initial electrical signal, the inverted fourth initial electrical signal, and the second initial electrical signal to obtain a third driving electrical signal in the second target electrical signal, wherein the third driving electrical signal is used to drive the bipolar chip in the second bridge arm.

[0103] In this embodiment, the control circuit may further include a third AND gate, which may be connected to a bipolar chip in the second bridge arm. For example, the third AND gate may be connected to a SI IGBT chip in the lower half-bridge arm.

[0104] In this embodiment, after the controller sends the initial electrical signal, the delay sub-circuit connected to the NAND gate can receive the initial electrical signal sent by the controller, and can perform turn-off delay operations on the third and fourth initial electrical signals in the received initial electrical signal respectively, thereby achieving the purpose of delaying the initial electrical signal and realizing the technical effect of delaying the conduction time of the circuit.

[0105] In this embodiment, after the delay sub-circuit performs delay operations on the third and fourth initial electrical signals in the initial electrical signal, the delayed third and fourth initial electrical signals are input to the NOT gate connected to the third AND gate. Then, the NOT gate connected to the third AND gate can perform inversion operations on the delayed third and fourth initial electrical signals, thereby achieving the purpose of inverting the initial electrical signals and realizing the technical effect of improving the effectiveness of signal conversion operations.

[0106] In this embodiment, the aforementioned third driving electrical signal can be used to drive the bipolar chip in the second bridge arm. For example, the aforementioned third driving electrical signal can be used to drive the SI IGBT chip in the lower half-bridge arm. The aforementioned third driving electrical signal can be represented by DRIVE_PWM_IGBT_L, which is only an example and not a specific limitation.

[0107] In this embodiment, after the NOT gate performs inversion operations on the delayed third initial electrical signal and the delayed fourth initial electrical signal respectively, the inverted third initial electrical signal, the inverted fourth initial electrical signal, and the second initial electrical signal in the initial electrical signal are input to the third AND gate connected to the second bridge arm. The third AND gate connected to the second bridge arm performs AND operations on the inverted third initial electrical signal, the inverted fourth initial electrical signal, and the second initial electrical signal in the initial electrical signal respectively, and the third driving electrical signal in the second target electrical signal can be obtained. This achieves the purpose of converting the initial electrical signal into the target electrical signal and realizes the technical effect of improving the accuracy of the signal conversion operation.

[0108] The second bridge arm of this embodiment will now be further described.

[0109] As an optional embodiment, the second bridge arm is used to respond to the second drive signal and the third drive signal in the second target electrical signal to complete the drive.

[0110] In this embodiment, after the control circuit converts the initial electrical signal into a target electrical signal, the second and third driving electrical signals from the second target electrical signal are input to the second bridge arm connected to the control circuit. The second bridge arm connected to the control circuit can be triggered by the second and third driving electrical signals to complete the driving. That is, the semiconductor chip of the second bridge arm can be triggered by the second driving electrical signal to complete the driving, and the bipolar chip of the second bridge arm can be triggered by the third driving electrical signal to complete the driving. This achieves the goal of driving the second bridge arm and realizes the technical effect of reducing the risk of circuit failure.

[0111] The control device described in this embodiment will be further described below.

[0112] As an optional embodiment, the control circuit further includes a fourth AND gate, wherein a delay sub-circuit, connected to a NAND gate, is used to perform delay operations on the first initial electrical signal and the second initial electrical signal respectively; a NOT gate, connected to the fourth AND gate, is used to perform inversion operations on the delayed first initial electrical signal and the delayed second initial electrical signal respectively; and a fourth AND gate, connected to the first bridge arm, is used to perform an AND operation on the inverted first initial electrical signal, the inverted second initial electrical signal, and the fourth initial electrical signal to obtain a fourth driving electrical signal in the first target electrical signal, wherein the fourth driving electrical signal is used to drive the bipolar chip in the first bridge arm.

[0113] In this embodiment, the control circuit further includes a fourth AND gate, which can be connected to a bipolar chip in the first bridge arm. For example, the fourth AND gate can be connected to a SI IGBT chip in the upper bridge arm.

[0114] In this embodiment, after the controller sends the initial electrical signal, the delay sub-circuit connected to the NAND gate can receive the initial electrical signal sent by the controller, and can perform a turn-off delay operation on the first initial electrical signal and the second initial electrical signal in the received initial electrical signal respectively, thereby achieving the purpose of delaying the initial electrical signal and realizing the technical effect of delaying the conduction time of the circuit.

[0115] In this embodiment, after the delay sub-circuit performs delay operations on the first and second initial electrical signals in the initial electrical signals respectively, the delayed first and second initial electrical signals are input to the NOT gate connected to the fourth AND gate. Then, the NOT gate connected to the fourth AND gate can perform inversion operations on the delayed first and second initial electrical signals respectively, thereby achieving the purpose of inverting the initial electrical signals and realizing the technical effect of improving the effectiveness of signal conversion operations.

[0116] In this embodiment, the aforementioned fourth driving electrical signal can be used to drive the bipolar chip in the first bridge arm. For example, the aforementioned fourth driving electrical signal can be used to drive the SI IGBT chip in the upper half of the bridge arm. The aforementioned first driving electrical signal can be represented by DRIVE_PWM_IGBT_H, which is only an example and not a specific limitation.

[0117] In this embodiment, after the NOT gate performs inversion operations on the delayed first initial electrical signal and the delayed second initial electrical signal respectively, the inverted first initial electrical signal, the inverted second initial electrical signal, and the fourth initial electrical signal in the initial electrical signal are input to the fourth AND gate connected to the first bridge arm. The fourth AND gate connected to the first bridge arm performs AND operations on the inverted first initial electrical signal, the inverted second initial electrical signal, and the fourth initial electrical signal in the initial electrical signal respectively, and the fourth driving electrical signal in the first target electrical signal can be obtained. This achieves the purpose of converting the initial electrical signal into the target electrical signal and realizes the technical effect of improving the accuracy of the signal conversion operation.

[0118] The first bridge arm of this embodiment will be further described below.

[0119] As an optional embodiment, the first bridge arm is used to respond to the first drive signal and the fourth drive signal in the first target electrical signal to complete the drive.

[0120] In this embodiment, after the control circuit converts the initial electrical signal into a target electrical signal, the first driving electrical signal and the fourth driving electrical signal from the first target electrical signal are input to the second bridge arm connected to the control circuit. The second bridge arm connected to the control circuit can be triggered by the first driving electrical signal and the fourth driving electrical signal to complete the driving. That is, the semiconductor chip of the first bridge arm can be triggered by the first driving electrical signal to complete the driving, and the bipolar chip of the first bridge arm can be triggered by the second driving electrical signal to complete the driving. This achieves the purpose of driving the first bridge arm and realizes the technical effect of reducing the risk of circuit failure.

[0121] In this embodiment of the invention, when the bridge arm is driven using a control device, the controller can send an initial electrical signal, and the control circuit connected to the controller can convert the initial electrical signal into a target electrical signal. The first bridge arm connected to the control circuit can be triggered by the first target electrical signal in the target electrical signal to complete the drive, and the second bridge arm connected to the control circuit can be triggered by the second target electrical signal in the target electrical signal to complete the drive. Because in this embodiment of the invention, after the control circuit converts the initial electrical signal sent by the controller into a target electrical signal, the first bridge arm can be triggered by the first target electrical signal in the target electrical signal to complete the drive, and the second bridge arm can be triggered by the second target electrical signal in the target electrical signal to complete the drive, the purpose of avoiding untimely PWM control is achieved, thereby solving the technical problem of high risk of circuit failure and realizing the technical effect of reducing the risk of circuit failure.

[0122] For example, the control device in this invention can be used to provide data interaction functions for preset application scenarios. These preset application scenarios can include the following scenarios in the vehicle field: autonomous driving scenarios for commuting, artificial intelligence (AI) assisted driving scenarios for family cars, automatic parking assistance (APA) scenarios (such as memory parking for self-owned parking spaces in garages, intelligent parking for designated parking spaces in parking lots, etc.), and intelligent navigation assistance (NGP) scenarios in urban or highway areas. Furthermore, the preset application scenarios may also include, but are not limited to: intelligent transportation scenarios for intelligent driving trucks or unmanned trucks in the logistics and transportation field, and intelligent farming scenarios for autonomous agricultural vehicles in the agricultural machinery field.

[0123] When the above-mentioned preset application scenario is a scenario in a field other than the vehicle field, those skilled in the art should be able to understand that the vehicle in this utility model can be replaced with other objects (e.g., agricultural machinery, drones, and robots), and correspondingly, the various devices and systems included in the vehicle can be replaced with devices and systems related to other objects.

[0124] The technical solutions of the present invention will be illustrated below with reference to preferred embodiments.

[0125] Since the turn-on and turn-off times, required dead times, and turn-on and turn-off voltages of SiC and IGBT are different, two PWM waves are usually used to drive the parallel SiC and IGBT respectively. For example, Figure 2(a) is a schematic diagram of a half-bridge structure according to related technologies. As shown in Figure 2(a), the PWM_SIC_H signal and the PWM_IGBT_H signal are used to drive the upper half-bridge arm SiC MOSFET and SI IGBT respectively, and the PWM_SIC_L signal and the PWM_IGBT_L signal are used to drive the lower half-bridge arm SiC MOSFET and SI IGBT respectively.

[0126] However, the above driving method may lead to untimely PWM control when the MCU load rate is too high, which may result in a high risk of circuit failure.

[0127] However, this utility model embodiment proposes a control device. When the control device is used to drive the bridge arm, the controller can be used to send an initial electrical signal, and the control circuit connected to the controller can be used to convert the initial electrical signal into a target electrical signal. The first bridge arm connected to the control circuit can be used to respond to the first target electrical signal in the target electrical signal to trigger and complete the drive. The second bridge arm connected to the control circuit can be used to respond to the second target electrical signal in the target electrical signal to trigger and complete the drive. This achieves the purpose of avoiding untimely PWM control, thereby solving the technical problem of high risk of circuit failure and achieving the technical effect of reducing the risk of circuit failure.

[0128] In this embodiment, a hardware shoot-through protection circuit for driving a hybrid SI IGBT and SiC MOSFET switch is deployed in the control device. This hardware shoot-through protection circuit prevents untimely PWM control. For example, Figure 2(b) is a schematic diagram of a hardware shoot-through protection circuit for driving a hybrid SI IGBT and SiC MOSFET switch according to an embodiment of the present invention. As shown in Figure 2(b), the circuit includes the following components: diodes D1 to D4, resistors R1 to R4, capacitors C1 to C4, a NOT gate, and an AND gate.

[0129] For example, taking DRIVE_PWM_SIC_H as an example, PWM_SIC_L and PWM_IGBT_L are passed through a turn-off delay circuit (e.g., this turn-off delay circuit includes diode D1 and resistor R1) to perform a turn-off delay operation on PWM_SIC_L and PWM_IGBT_L. Then, the delayed PWM_SIC_L and PWM_IGBT_L are inverted by a NOT gate. Finally, the inverted PWM_SIC_L and PWM_IGBT_L, along with the initial PWM_SIC_H, are ANDed by an AND gate to perform a bitwise AND operation (also called a bitwise AND operation). This yields the signal that drives the SI MOSFET chip in the upper half-bridge arm.

[0130] For another example, taking DRIVE_PWM_SIC_H as an example, when the dead time of the PWM wave issued by the software is normal, the waveform of the MCU can be as shown in Figure 2(c). Figure 2(c) is a schematic diagram of the waveform of an MCU according to an embodiment of the present invention. The initial waveforms of the PWM_SIC_L, PWM_IGBT_L and PWM_SIC_H signals are shown in Figure 2(c). The interval indicated by the arrow can represent the dead time t1.

[0131] Figure 2(d) is a schematic diagram of a waveform after delay processing according to an embodiment of the present invention. As shown in Figure 2(d), the waveforms of PWM_SIC_L and PWM_IGBT_L after delay processing, as well as the initial waveform of the PWM_SIC_H signal, are shown. The interval indicated by the arrow to the right of the dead time can represent the delay time t2.

[0132] Figure 2(e) is a schematic diagram of an AND-based waveform according to an embodiment of the present invention. As shown in Figure 2(e), the waveforms of the inverted PWM_SIC_L and PWM_IGBT_L, as well as the initial waveform of the PWM_SIC_H signal, are shown. The AND-based waveform is also shown, that is, the waveform obtained by performing an AND logic operation on the inverted PWM_SIC_L and PWM_IGBT_L, as well as the initial PWM_SIC_H, through an AND gate.

[0133] For another example, taking DRIVE_PWM_SIC_L, PWM_SIC_H and PWM_IGBT_H are passed through a turn-off delay circuit (e.g., this turn-off delay circuit includes diode D2 and resistor R2) to perform a turn-off delay operation on PWM_SIC_H and PWM_IGBT_H. Then, the delayed PWM_SIC_H and PWM_IGBT_H are inverted by a NOT gate. Finally, the inverted PWM_SIC_H and PWM_IGBT_H, along with the initial PWM_SIC_L, are ANDed by an AND gate to perform a logical AND operation. This yields the signal that drives the SI MOSFET chip in the lower half-bridge arm.

[0134] For example, taking DRIVE_PWM_IGBT_L as an example, PWM_SIC_H and PWM_IGBT_H are passed through a turn-off delay circuit (for example, this turn-off delay circuit includes diode D3 and resistor R3) to perform a turn-off delay operation on PWM_SIC_H and PWM_IGBT_H. Then, the delayed PWM_SIC_H and PWM_IGBT_H are inverted by a NOT gate. Then, the inverted PWM_SIC_H and PWM_IGBT_H, along with the initial PWM_IGBT_L, are ANDed by an AND gate to perform a logical AND operation. This yields the signal that drives the SI IGBT chip in the lower half-bridge arm.

[0135] For example, taking DRIVE_PWM_IGBT_H, PWM_SIC_L and PWM_IGBT_L are passed through a turn-off delay circuit (e.g., this turn-off delay circuit includes diode D4 and resistor R4) to perform a turn-off delay operation on PWM_SIC_L and PWM_IGBT_L. Then, the delayed PWM_SIC_L and PWM_IGBT_L are inverted by a NOT gate. Finally, the inverted PWM_SIC_L and PWM_IGBT_L, along with the initial PWM_SIC_H, are ANDed by an AND gate to perform a logical AND operation. This yields the signal that drives the SI MOSFET chip in the upper half-bridge arm.

[0136] Furthermore, Figure 2(f) is a schematic diagram of an abnormal waveform of MCU waveform dead time according to an embodiment of the present invention. As shown in Figure 2(f), taking DRIVE_PWM_SIC_H as an example, when the dead time of the PWM waveform sent by the software is abnormal, the waveforms of the PWM_SIC_L, PWM_IGBT_L and PWM_SIC_H signals are shown.

[0137] Figure 2(g) is a schematic diagram of an abnormal waveform after delay processing according to an embodiment of the present invention. As shown in Figure 2(g), the waveforms of the PWM_SIC_L, PWM_IGBT_L and PWM_SIC_H signals after delay processing are shown when the dead time of the PWM wave issued by the software is abnormal, taking DRIVE_PWM_SIC_H as an example.

[0138] Figure 2(h) is a schematic diagram of an abnormal waveform after AND operation according to an embodiment of the present invention. As shown in Figure 2(h), when the dead time of the PWM wave issued by the software is abnormal, taking DRIVE_PWM_SIC_H as an example, the waveforms of the inverted PWM_SIC_L and PWM_IGBT_L, as well as the waveform of the PWM_SIC_H signal, are shown. The waveform after AND operation is also shown, that is, the waveform obtained by performing an AND logic operation on the inverted PWM_SIC_L and PWM_IGBT_L, and the initial PWM_SIC_H through an AND gate.

[0139] It should be noted that when the dead time of the software waveform is normal (e.g., the current dead time is longer than the preset dead time), this circuit has no effect on the software waveform. When the dead time of the software waveform is abnormal (e.g., the current dead time is less than or equal to the preset dead time), this circuit inserts a hardware dead time into the output waveform, that is, sets a hardware delay duration, which is adjustable, thereby preventing the PWM waveform from shooting through.

[0140] In this embodiment, the vehicle can upload the current driving status of the first and second axle arms to the server so that the server can record whether the first and second axle arms have been successfully driven. Figure 2(i) is a schematic diagram of data interaction between a vehicle and a server according to an embodiment of the present invention. As shown in Figure 2(i), the vehicle 220 can upload the current driving status to the server 221, and the server 221 can send the historical driving status to the vehicle 220. The current driving status can be used to represent the driving progress of the first and second axle arms at the current moment, and the historical driving status can be used to represent the driving progress of the first and second axle arms at a historical moment.

[0141] In this embodiment, when the control device is used to drive the bridge arm, the controller can be used to send an initial electrical signal, and the control circuit connected to the controller can be used to convert the initial electrical signal into a target electrical signal. The first bridge arm connected to the control circuit can be used to respond to the first target electrical signal in the target electrical signal to trigger and complete the drive. The second bridge arm connected to the control circuit can be used to respond to the second target electrical signal in the target electrical signal to trigger and complete the drive. This achieves the goal of avoiding untimely PWM control, thereby solving the technical problem of high risk of circuit failure and achieving the technical effect of reducing the risk of circuit failure.

[0142] According to another aspect of the present invention, a vehicle is also provided, comprising: a memory storing an executable program; and a processor running the program, wherein the program, when running, controls the control device of any of the above-mentioned items.

[0143] Figure 3 This is a structural block diagram of a vehicle according to an embodiment of the present utility model, such as... Figure 3 As shown, the components of the vehicle 300 include, but are not limited to, a memory 310 and a processor 320. The processor 320 is connected to the memory 310 via a bus 330, and the database 350 is used to store data.

[0144] Vehicle 300 may also include access device 340, which enables vehicle 300 to communicate via one or more networks 360. Examples of these networks include Public Switched Telephone Network (PSTN), Local Area Network (LAN), Wide Area Network (WAN), Personal Area Network (PAN), or combinations of communication networks such as the Internet. Access device 340 may include one or more of any type of wired or wireless network interface (e.g., network interface controller (NIC)), such as an IEEE 802.11 Wireless Local Area Network (WLAN) wireless interface, a Worldwide Interoperability for Microwave Access (Wi-MAX) interface, an Ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth interface, a Near Field Communication (NFC) interface, and so on.

[0145] In one embodiment of this disclosure, the aforementioned components of vehicle 300 and Figure 3 Other components, not shown, can also be connected to each other, for example, via a bus. It should be understood that... Figure 3 The vehicle structure diagram shown is for illustrative purposes only and is not intended to limit the scope of this disclosure. Those skilled in the art can add or replace other components as needed.

[0146] It should be noted that the sequence numbers of the above-mentioned embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0147] In the above embodiments of this utility model, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0148] In the several embodiments provided by this utility model, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection can be through some interfaces; the indirect coupling or communication connection of units or modules can be electrical or other forms.

[0149] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0150] Furthermore, in the various embodiments of this utility model, the functional units can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0151] The above are merely preferred embodiments of this utility model. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications should also be considered within the scope of protection of this utility model.

Claims

1. A control device, characterized in that, The control device includes: a controller, a control circuit, a first bridge arm, and a second bridge arm, wherein the first bridge arm and the second bridge arm are respectively deployed at different positions within the control device. The controller is used to send an initial electrical signal; The control circuit, connected to the controller, is used to convert the initial electrical signal into a target electrical signal; The first bridge arm is connected to the control circuit and is used to respond to the triggering of the first target electrical signal in the target electrical signal to complete the drive; The second bridge arm is connected to the control circuit and is used to respond to the triggering of the second target electrical signal in the target electrical signal to complete the drive; The first target electrical signal is interlocked with the second target electrical signal.

2. The control device according to claim 1, characterized in that, The control circuit includes a delay sub-circuit, a NOT gate, and a first AND gate, wherein... The delay sub-circuit, connected to the NOT gate, is used to perform delay operations on the first initial electrical signal and the second initial electrical signal in the initial electrical signal, respectively, wherein the first initial electrical signal is an electrical signal that allows action on the semiconductor chip in the second bridge arm, and the second initial electrical signal is an electrical signal that allows action on the bipolar chip in the second bridge arm; The NOT gate, connected to the first AND gate, is used to perform inversion operations on the delayed first initial electrical signal and the delayed second initial electrical signal, respectively. The first AND gate, connected to the first bridge arm, is used to perform AND operations on the inverted first initial electrical signal, the inverted second initial electrical signal, and the third initial electrical signal in the initial electrical signal to obtain the first driving electrical signal in the first target electrical signal. The third initial electrical signal is an electrical signal that allows the semiconductor chip in the first bridge arm to be acted upon, and the first driving electrical signal is used to drive the semiconductor chip in the first bridge arm.

3. The control device according to claim 2, characterized in that, The delay sub-circuit is configured to perform delay operations on the first initial electrical signal and the second initial electrical signal respectively in response to the current dead time of the controller being greater than the preset dead time; and to perform delay operations on the first initial electrical signal and the second initial electrical signal respectively after performing a hardware dead time insertion operation on the first initial electrical signal and the second initial electrical signal in response to the current dead time being less than or equal to the preset dead time.

4. The control device according to claim 2, characterized in that, The delay sub-circuit includes a first delay sub-circuit and a second delay sub-circuit, wherein, The first delay sub-circuit is connected to the controller and is used to perform a delay operation on the first initial electrical signal; The second delay sub-circuit, connected to the controller, is used to perform a delay operation on the second initial electrical signal.

5. The control device according to claim 4, characterized in that, The NOT gate includes a first NOT gate and a second NOT gate, wherein, The first NOT gate is connected to the first delay sub-circuit and is used to perform an inversion operation on the delayed first initial electrical signal; The second NOT gate is connected to the second delay sub-circuit and is used to perform an inversion operation on the delayed second initial electrical signal.

6. The control device according to claim 2, characterized in that, The control circuit further includes a second AND gate, wherein... The delay sub-circuit, connected to the NOT gate, is used to perform delay operations on the third initial electrical signal and the fourth initial electrical signal among the initial electrical signals, respectively, wherein the fourth initial electrical signal is an electrical signal that allows the bipolar chip in the first bridge arm to act; The NOT gate, connected to the second AND gate, is used to perform inversion operations on the delayed third initial electrical signal and the delayed fourth initial electrical signal, respectively. The second AND gate, connected to the second bridge arm, is used to perform an AND operation on the inverted third initial electrical signal, the inverted fourth initial electrical signal, and the first initial electrical signal to obtain the second driving electrical signal in the second target electrical signal, wherein the second driving electrical signal is used to drive the semiconductor chip in the second bridge arm.

7. The control device according to claim 6, characterized in that, The delay sub-circuit is configured to perform delay operations on the third initial electrical signal and the fourth initial electrical signal respectively in response to the current dead time of the controller being greater than the preset dead time; and to perform delay operations on the third initial electrical signal and the fourth initial electrical signal respectively after performing a hardware dead time insertion operation on the third initial electrical signal and the fourth initial electrical signal in response to the current dead time being less than or equal to the preset dead time.

8. The control device according to claim 6, characterized in that, The delay sub-circuit includes a third delay sub-circuit and a fourth delay sub-circuit, wherein, The third delay sub-circuit is connected to the controller and is used to acquire the third initial electrical signal and perform a delay operation on the third initial electrical signal; The fourth delay sub-circuit is connected to the controller and is used to acquire the fourth initial electrical signal and perform a delay operation on the fourth initial electrical signal.

9. The control device according to claim 8, characterized in that, The NOT gates include a third NOT gate and a fourth NOT gate, wherein, The third NOT gate is connected to the third delay sub-circuit and is used to perform an inversion operation on the delayed third initial electrical signal; The fourth NOT gate is connected to the fourth delay sub-circuit and is used to invert the delayed fourth initial electrical signal.

10. The control device according to claim 6, characterized in that, The control circuit also includes a third AND gate, wherein... The delay sub-circuit is connected to the NOT gate and is used to perform delay operations on the third initial electrical signal and the fourth initial electrical signal, respectively. The NOT gate is connected to the third AND gate and is used to perform inversion operations on the delayed third initial electrical signal and the delayed fourth initial electrical signal, respectively. The third AND gate, connected to the second bridge arm, is used to perform an AND operation on the inverted third initial electrical signal, the inverted fourth initial electrical signal, and the second initial electrical signal to obtain the third driving electrical signal in the second target electrical signal. The third driving electrical signal is used to drive the bipolar chip in the second bridge arm.

11. The control device according to claim 10, characterized in that, The second bridge arm is used to respond to the second driving electrical signal and the third driving electrical signal in the second target electrical signal to complete the driving.

12. The control device according to claim 10, characterized in that, The control circuit also includes a fourth AND gate, wherein... The delay sub-circuit is connected to the NOT gate and is used to perform delay operations on the first initial electrical signal and the second initial electrical signal, respectively. The NOT gate, connected to the fourth AND gate, is used to perform inversion operations on the delayed first initial electrical signal and the delayed second initial electrical signal, respectively. The fourth AND gate, connected to the first bridge arm, is used to perform an AND operation on the inverted first initial electrical signal, the inverted second initial electrical signal, and the fourth initial electrical signal to obtain the fourth driving electrical signal in the first target electrical signal. The fourth driving electrical signal is used to drive the bipolar chip in the first bridge arm.

13. The control device according to claim 12, characterized in that, The first bridge arm is used to respond to the first driving electrical signal and the fourth driving electrical signal in the first target electrical signal to complete the driving.

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