A reset circuit

Abstract

This invention discloses a reset circuit, including a dual-switch trigger module and a reset module. The dual-switch trigger module includes a first switch module, a second switch module, and a semiconductor switching device. The dual-switch trigger module is configured to conduct the semiconductor switching device and output a high level when the first switch module and the second switch module are simultaneously activated. The reset module includes a DC power supply connected to the MCU reset pin and an NMOS transistor. The drain of the NMOS transistor is connected between the MCU reset pin and the DC power supply, the gate of the NMOS transistor is connected to the output terminal of the semiconductor switching device, and the source of the NMOS transistor is grounded. This invention provides two independent inputs to control the conduction state of the semiconductor switching device, enabling users to actively trigger a reset, thereby significantly improving reliability and effectively reducing the probability of false resets. It is convenient for users to operate without complex operations or adjustments.

Description

Technical Field

[0001] This utility model relates to the field of reset control circuit technology, and in particular to a reset circuit. Background Technology

[0002] With the widespread application of embedded systems, reliable MCU reset is crucial for system security and stability. Traditional reset circuits often rely on dedicated chips or complex auxiliary circuits, which suffer from drawbacks such as high cost, large size, inaccurate reset time control, non-complete square wave reset waveform, inconvenient adjustment, and insufficient anti-interference capability. Especially in space-constrained portable and automotive devices, there is a need for compact, low-cost reset solutions with high adjustment accuracy.

[0003] Existing reset circuit designs typically employ an RC network combined with a transistor to achieve delayed reset. However, this traditional approach suffers from drawbacks such as cumbersome and difficult parameter adjustments, large errors (above ±10%), susceptibility to electromagnetic interference (EMI) and noise, and weak anti-interference capabilities. Furthermore, its use of multiple components or large packages results in significant space consumption, making it difficult to meet the design requirements of space-constrained environments.

[0004] In addition, there are some existing reset circuit designs that use reset chips. Although this method provides accurate and long-term reset, it is costly and cannot meet the requirements of high reliability, low cost, and multi-functional reset control. Utility Model Content

[0005] This utility model provides a reset circuit to solve at least one of the problems of low reliability, low accuracy, and insufficient anti-interference ability in the prior art.

[0006] According to one aspect of the present invention, a reset circuit is provided, comprising a dual-switch trigger module and a reset module; The dual-switch trigger module includes a first switch module, a second switch module, and a semiconductor switch device. The dual-switch trigger module is configured to turn on the semiconductor switch device and output a high level when the first switch module and the second switch module are started simultaneously. The reset module includes a DC power supply and an NMOS transistor connected to the MCU reset pin. The drain of the NMOS transistor is connected between the MCU reset pin and the DC power supply. The gate of the NMOS transistor is connected to the output terminal of the semiconductor switching device. The source of the NMOS transistor is grounded.

[0007] This invention's reset circuit employs a dual-switch trigger module to ensure that the semiconductor switching devices output a high level only when both the first and second switch modules are simultaneously activated. Furthermore, the addition of an NMOS transistor allows the NMOS to conduct simultaneously when the semiconductor switching devices output a high level, creating a drain-source connection that short-circuits the MCU reset pin to a low level, pulling the MCU reset pin low. The overall reset circuit uses two independent inputs (the first and second switch modules) to control the conduction state of the semiconductor switching devices, enabling users to actively trigger a reset, while the chip system can also force a reset via the MCU's reset pin, forming a dual trigger. Because the reset requires simultaneous activation of both the first and second switch modules, reliability is significantly improved, and the probability of false resets is effectively reduced. User operation is convenient, requiring no complex procedures or adjustments.

[0008] In some embodiments, the semiconductor switching device is configured as a PNP transistor. The first switch module includes a first switch, which outputs a low level when the first switch is open and a high level when the first switch is closed and connected to a DC power supply. The second switch module includes a second switch. When the second switch is open, it is connected to a DC power supply and outputs a high level. When the second switch is closed, it outputs a low level. The emitter of the PNP transistor is connected to the first switching module, the base of the PNP transistor is connected to the second switching module, and the collector of the PNP transistor is connected to the gate of the NMOS transistor.

[0009] Therefore, through the design of the first switch module, the second switch module, and the PNP transistor, the emitter and collector of the PNP transistor can only conduct when both the first and second switches are closed simultaneously, thus enabling the PNP transistor's collector to output a high level. Furthermore, this design utilizes low-leakage transistors and optimized circuit layout to ensure minimal power consumption in standby mode. Simultaneously, the entire system can employ SOT-23 packaged transistors and miniature surface-mount components, reducing the overall area by more than 60%, making it suitable for space-constrained environments.

[0010] In some embodiments, the first switch module further includes a DC power supply, a resistor R1, and a resistor R3. One end of the DC power supply is grounded, and the other end is connected to the first switch and the resistor R3 in sequence. The other end of the resistor R3 is connected to the emitter of the PNP transistor. One end of the resistor R1 is connected between the first switch and the resistor R3, and the other end of the resistor R1 is grounded.

[0011] Therefore, by setting it up in this way, the first switch module can output a low level when the first switch is open and output a high level when connected to a DC power supply when the first switch is closed.

[0012] In some embodiments, the first switching module further includes a capacitor C1, which is connected in parallel across the resistor R1.

[0013] Therefore, by setting it up in this way, capacitor C1 can be used to filter the circuit, enhance the circuit's anti-interference ability, and avoid system abnormalities caused by misoperation.

[0014] In some embodiments, the second switch module further includes a DC power supply and a resistor R2. One end of the DC power supply is grounded, and the other end is connected to the resistor R2. The other end of the resistor R2 is connected to the base of the PNP transistor. One end of the second switch is connected between the base of the PNP transistor and the resistor R2, and the other end of the second switch is grounded.

[0015] Therefore, by setting it up in this way, the second switch module can be connected to the DC power supply to output a high level when the second switch is open, and output a low level when the second switch is closed.

[0016] In some embodiments, the second switch module further includes a resistor R9, a capacitor C2, and a capacitor C3. The two ends of the resistor R9 are connected between the second switch and the base of the PNP transistor. One end of capacitor C2 is connected between resistors R2 and R9, and the other end is grounded. One end of the capacitor C3 is connected between the resistor R9 and the base of the PNP transistor, and the other end is grounded.

[0017] Therefore, by setting it up in this way, capacitors C2 and C3 can be used to filter the circuit, while resistor R9 can limit current and buffer signals, thereby further enhancing the circuit's anti-interference ability and stability, and avoiding system abnormalities caused by misoperation.

[0018] In some embodiments, the reset module further includes resistors R7 and R4, which are connected in series between the DC power supply and the drain of the NMOS transistor, and the MCU reset pin is connected between resistors R7 and R4.

[0019] Therefore, this setting enables the pull-up level function, ensuring the normal and reliable operation of the MCU reset function.

[0020] In some embodiments, the reset module further includes a diode D2, the cathode of which is connected between a DC power supply and a resistor R7, the anode of which is connected between resistor R7 and resistor R4, and the anode of which is also connected to the MCU reset pin.

[0021] Therefore, by using this configuration, diode D2 can be used to prevent the piezoelectric current of the MCU reset pin from exceeding the chip's withstand threshold, thereby improving the system's reliability and ability to prevent accidental touches.

[0022] In some embodiments, a delay module is also included, which is connected between the output of the semiconductor switching device and the gate of the NMOS transistor.

[0023] Therefore, by using this setting, the reset signal can be maintained for a preset time and then automatically triggered using a delay module, eliminating the need for a dedicated chip and effectively reducing costs.

[0024] In some embodiments, the delay module includes a resistor R5 and a capacitor C4. The two ends of the resistor R5 are connected between the output terminal of the semiconductor switching device and the gate of the NMOS transistor. One end of the capacitor C4 is connected between the resistor R5 and the gate of the NMOS transistor, and the other end is grounded.

[0025] Therefore, by setting it up in this way, an RC delay circuit can be formed using resistor R5 and capacitor C4. The delay time can be adjusted from 0.1 seconds to 5 seconds by adjusting the parameters of resistor R5 or capacitor C4, with an overall delay error of <5%, meeting the requirements for high-precision reset.

[0026] In some embodiments, the delay module further includes a resistor R6 and a diode D1. One end of resistor R6 is connected between resistor R5 and the output terminal of the semiconductor switching device, and the other end is grounded. The anode of diode D1 is connected between resistor R5 and the gate of NMOS transistor, and the cathode of diode D1 is connected between resistor R5 and the output terminal of semiconductor switching device.

[0027] Therefore, by setting it up in this way, diode D1 can be used to accelerate the discharge speed in the non-reset state, improve the accuracy of the delay reset time and the anti-interference ability. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a block diagram illustrating the overall principle of the reset circuit according to one embodiment of the present invention. Figure 2 This is an overall principle block diagram of the reset circuit according to another embodiment of the present invention; Figure 3 This is a block diagram illustrating the overall principle of the reset circuit according to another embodiment of the present invention. Figure 4 This is a circuit diagram of a reset circuit according to one embodiment of the present invention; Explanation of reference numerals in the attached diagram: 1. Dual-switch trigger module; 11. First switch module; 12. Second switch module; 13. Semiconductor switching device; 2. Reset module; 3. Delay module. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0031] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0032] In the description of this application, it should be understood that the use of terms such as "center," "middle," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential" to indicate orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings is solely for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Features defined with "first" and "second" are used to distinguish feature names and do not have special meanings. Furthermore, features defined with "first" and "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "multiple" means two or more.

[0033] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0034] It should also be noted that, in this document, the terms "comprising" or "including" include not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The terminology used herein is generally that commonly used by those skilled in the art; in case of any discrepancy with commonly used terminology, the terminology used herein shall prevail.

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0036] The present invention will now be described in further detail with reference to the accompanying drawings.

[0037] Figures 1 to 4 The schematic diagram illustrates the principle of the reset circuit according to one embodiment of this utility model. (Refer to...) Figure 1 and Figure 2 As shown, the reset circuit of this utility model includes a dual-switch trigger module 1 and a reset module 2. The dual-switch trigger module 1 includes a first switch module 11, a second switch module 12, and a semiconductor switching device 13. The overall dual-switch trigger module 1 is configured to turn on the semiconductor switching device 13 and cause its output terminal to output a high level when the first switch module 11 and the second switch module 12 are simultaneously activated. (Refer to...) Figure 4 As shown, the reset module 2 includes a DC power supply and an NMOS transistor (i.e., connected to the MCU reset pin) Figure 4 In section Q2), the drain of the NMOS transistor is connected between the MCU reset pin and the DC power supply, the gate of the NMOS transistor is connected to the output of semiconductor switching device 13, and the source of the NMOS transistor is grounded. Therefore, when semiconductor switching device 13 outputs a high level, it triggers the NMOS transistor, turning on its source and drain, pulling the output level low, thus grounding the MCU reset pin and resetting the MCU.

[0038] Specifically, the semiconductor switching device 13 in the dual-switch trigger module 1 can be configured as a transistor or a MOSFET. For example, taking a PNP transistor as the semiconductor switching device 13, refer to... Figure 4 As shown, in Figure 4 In the embodiment shown, the PNP transistor (i.e. Figure 4 The emitter of the PNP transistor (Q1) is connected to the first switching module 11, the base of the PNP transistor is connected to the second switching module 12, and the collector of the PNP transistor is connected to the gate of the NMOS transistor. At this time, the first switching module 11 outputs a high level upon startup, and the second switching module 12 outputs a low level upon startup, thereby pulling down the base of the PNP transistor and turning on the emitter and collector of the PNP transistor, causing the output terminal of the PNP transistor to output a high level. Specifically, the first switching module 11 includes a first switch (i.e.,...) Figure 4 The second switch module 12 includes a second switch (i.e., SW1), and is configured to output a low level when the first switch is open and to connect to a DC power supply to output a high level when the first switch is closed; Figure 4 (SW2), and set it to output a high level when the second switch is open and a low level when the second switch is closed.

[0039] Regarding the semiconductor switching device 13 used in the dual-switch trigger module 1, it is understood that it can also be configured as a PMOS transistor, with the source of the PMOS transistor connected to the first switching module 11, the gate of the PMOS transistor connected to the second switching module 12, and the drain of the PMOS transistor connected to the gate of the NMOS transistor. In this case, the first switching module 11 and the second switching module 12 can be reused. Figure 2 The circuit in the example can achieve the same function without adjustment. Furthermore, the semiconductor switching device 13 can also be set as other devices such as NPN transistors and NMOS transistors. Only adaptive adjustments to the circuits of the first switching module 11 and the second switching module 12 are needed based on the conduction characteristics of the corresponding semiconductor switching device 13. This embodiment will not elaborate on this further. Specifically, since transistors are relatively cheaper than MOS transistors, transistors are used as semiconductor switching devices in this embodiment. For ease of explanation, the implementation using a PNP transistor as the semiconductor switching device 13 will be used as an example in the following description.

[0040] In some embodiments, the first switch module 11 may further include a DC power supply, resistor R1, and resistor R3. Specifically, refer to... Figure 4 As shown, one end of the DC power supply is grounded, and the other end is connected sequentially to the first switch and resistor R3. The other end of resistor R3 is connected to the emitter of the PNP transistor. One end of resistor R1 is connected between the first switch and resistor R3, and the other end of resistor R1 is grounded. By configuring the first switch module 11 in this way, the DC power supply can be connected when the first switch is closed, thereby pulling the emitter level of the PNP transistor high. When the first switch is open, resistor R1 acts as a pull-down resistor, pulling the output of the first switch module 11 down to ground, i.e., outputting a low level. Furthermore, continue referring to... Figure 4 As shown, the first switch module 11 may also include a capacitor C1. Specifically, capacitor C1 is connected in parallel across resistor R1. Therefore, the added capacitor C1 can filter the circuit, enhance its anti-interference capability, and prevent system malfunctions caused by misoperation.

[0041] In some embodiments, the second switching module 12 may further include a DC power supply and a resistor R2. Specifically, refer to... Figure 4 As shown, one end of the DC power supply is grounded, and the other end is connected to resistor R2. The other end of resistor R2 is connected to the base of the PNP transistor. One end of the second switch is connected between the base of the PNP transistor and resistor R2, and the other end of the second switch is grounded. By configuring the second switch module 12 in this way, the DC power supply can be connected when the second switch is open, thereby pulling the base level of the PNP transistor high. When the second switch is closed, the base of the PNP transistor is grounded, resulting in a low output level. Furthermore, continue referring to... Figure 4As shown, the second switch module 12 may further include a resistor R9, a capacitor C2, and a capacitor C3. Specifically, the two ends of resistor R9 are connected between the second switch and the base of the PNP transistor; one end of capacitor C2 is connected between resistor R2 and resistor R9, and the other end is grounded; one end of capacitor C3 is connected between resistor R9 and the base of the PNP transistor, and the other end is grounded. Thus, capacitors C2 and C3 can be used to filter the circuit, while resistor R9 can act as a current limiter and signal buffer, further enhancing the circuit's anti-interference capability and stability, and preventing system abnormalities caused by misoperation.

[0042] In some embodiments, the reset module 2 may further include resistors R7 and R4. Specifically, refer to... Figure 4 As shown, resistors R7 and R4 are connected in series between the DC power supply and the drain of the NMOS transistor. The MCU reset pin is then connected between resistors R7 and R4. This configuration allows for pull-up and pull-down level functionality using resistors R7 and R4. Further details can be found in the following diagram. Figure 4 As shown, the reset module 2 may also include a diode D2. Specifically, the cathode of diode D2 is connected between the DC power supply and resistor R7, the anode of diode D2 is connected between resistor R7 and resistor R4, and the anode of diode D2 is also connected to the MCU reset pin. This configuration prevents the piezoelectric current of the MCU reset pin from exceeding its chip's withstand threshold, thus improving system reliability and preventing accidental touches.

[0043] Furthermore, refer to Figure 3 As shown, the reset circuit of this utility model can also be equipped with a delay module 3. The delay module 3 is connected between the collector of the PNP transistor and the gate of the NMOS transistor, and is used to maintain the reset signal. By setting the delay module 3, the reset signal can be maintained for a preset time before automatic triggering, thus eliminating the need for a dedicated chip and effectively reducing costs. Specifically, refer to... Figure 4 As shown, delay module 3 includes a resistor R5 and a capacitor C4. The two ends of resistor R5 are connected between the collector of the PNP transistor and the gate of the NMOS transistor. One end of capacitor C4 is connected between resistor R5 and the gate of the NMOS transistor, and the other end is grounded. In this delay module 3, resistor R5 and capacitor C4 form an RC delay circuit. In this delay circuit, the delay time τ = R × C. Therefore, by adjusting the parameters of resistor R5 and / or capacitor C4, a delay time of 0.1 seconds to 5 seconds can be achieved, while the overall delay error is <5%, meeting the high-precision reset requirements.

[0044] Additionally, delay module 3 may also include resistor R6 and diode D1. For details, please refer to... Figure 4As shown, one end of resistor R6 is connected between resistor R5 and the collector of the PNP transistor, and the other end is grounded. The anode of diode D1 is connected between resistor R5 and the gate of the NMOS transistor, and the cathode of diode D1 is connected between resistor R5 and the collector of the PNP transistor. This configuration allows diode D1 to accelerate the discharge speed in the non-reset state, improving the accuracy of the delay reset time and its anti-interference capability.

[0045] The reset circuit of this invention employs a dual-switch trigger module 1 to ensure that the semiconductor switching device 13 outputs a high level only when both the first switch module 11 and the second switch module 12 are simultaneously activated. Furthermore, the addition of an NMOS transistor allows the NMOS transistor to conduct simultaneously when the semiconductor switching device 13 outputs a high level, connecting its drain and source. This shorts the MCU reset pin to a low level, pulling the MCU reset pin low. The overall reset circuit uses two independent inputs (the first switch module 11 and the second switch module 12) to control the conduction state of the semiconductor switching device 13, enabling users to actively trigger a reset, while the chip system can also force a reset of the MCU's reset pin, forming a dual trigger. Because the simultaneous activation of both the first switch module 11 and the second switch module 12 is required to trigger a reset, reliability is significantly improved, and the probability of false resets is effectively reduced. User operation is convenient, requiring no complex operations or adjustments. The overall circuit uses mature and universal electronic components, effectively reducing overall cost, facilitating mass production and maintenance, and improving economic efficiency.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A reset circuit, characterized in that, It includes a dual-switch trigger module (1) and a reset module (2); The dual-switch trigger module (1) includes a first switch module (11), a second switch module (12), and a semiconductor switch device (13). The dual-switch trigger module (1) is configured to turn on the semiconductor switch device (13) and make its output terminal output a high level when the first switch module (11) and the second switch module (12) are started at the same time. The reset module (2) includes a DC power supply and an NMOS transistor connected to the MCU reset pin. The drain of the NMOS transistor is connected between the MCU reset pin and the DC power supply. The gate of the NMOS transistor is connected to the output terminal of the semiconductor switching device (13). The source of the NMOS transistor is grounded.

2. The reset circuit according to claim 1, characterized in that, The semiconductor switching device (13) is configured as a PNP transistor. The first switch module (11) includes a first switch. When the first switch is open, it outputs a low level, and when the first switch is closed, it is connected to a DC power supply and outputs a high level. The second switch module (12) includes a second switch. When the second switch is open, it is connected to a DC power supply and outputs a high level. When the second switch is closed, it outputs a low level. The emitter of the PNP transistor is connected to the first switching module (11), the base of the PNP transistor is connected to the second switching module (12), and the collector of the PNP transistor is connected to the gate of the NMOS transistor.

3. The reset circuit according to claim 2, characterized in that, The first switch module (11) also includes a DC power supply, a resistor R1 and a resistor R3. One end of the DC power supply is grounded, and the other end is connected to the first switch and the resistor R3 in sequence. The other end of the resistor R3 is connected to the emitter of the PNP transistor. One end of the resistor R1 is connected between the first switch and the resistor R3, and the other end of the resistor R1 is grounded.

4. The reset circuit according to claim 3, characterized in that, The first switch module (11) also includes a capacitor C1, which is connected in parallel across the resistor R1.

5. The reset circuit according to claim 2, characterized in that, The second switch module (12) also includes a DC power supply and a resistor R2. One end of the DC power supply is grounded and the other end is connected to the resistor R2. The other end of the resistor R2 is connected to the base of the PNP transistor. One end of the second switch is connected between the base of the PNP transistor and the resistor R2, and the other end of the second switch is grounded.

6. The reset circuit according to claim 5, characterized in that, The second switch module (12) also includes a resistor R9, a capacitor C2, and a capacitor C3. The two ends of the resistor R9 are connected between the second switch and the base of the PNP transistor. One end of capacitor C2 is connected between resistors R2 and R9, and the other end is grounded. One end of the capacitor C3 is connected between the resistor R9 and the base of the PNP transistor, and the other end is grounded.

7. The reset circuit according to claim 1, characterized in that, The reset module (2) also includes resistors R7 and R4, which are connected in series between the DC power supply and the drain of the NMOS transistor. The MCU reset pin is connected between resistors R7 and R4.

8. The reset circuit according to claim 6, characterized in that, The reset module (2) also includes a diode D2, the cathode of which is connected between the DC power supply and the resistor R7, the anode of which is connected between the resistor R7 and the resistor R4, and the anode of which is also connected to the MCU reset pin.

9. The reset circuit according to any one of claims 1 to 8, characterized in that, It also includes a delay module (3), which is connected between the output terminal of the semiconductor switching device (13) and the gate of the NMOS transistor.

10. The reset circuit according to claim 9, characterized in that, The delay module (3) includes a resistor R5 and a capacitor C4. The two ends of the resistor R5 are connected between the output terminal of the semiconductor switching device (13) and the gate of the NMOS transistor. One end of the capacitor C4 is connected between the resistor R5 and the gate of the NMOS transistor, and the other end is grounded.

11. The reset circuit according to claim 10, characterized in that, The delay module (3) also includes a resistor R6 and a diode D1. One end of the resistor R6 is connected between the resistor R5 and the output terminal of the semiconductor switching device (13), and the other end is grounded. The anode of the diode D1 is connected between the resistor R5 and the gate of the NMOS transistor, and the cathode of the diode D1 is connected between the resistor R5 and the output terminal of the semiconductor switching device (13).

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