Power-off retention circuits and electronic devices

Abstract

This application discloses a power-off retention circuit and an electronic device. The power-off retention circuit includes: an input detection circuit coupled to a power supply circuit; an optocoupler isolation circuit coupled to the input detection circuit and coupled to a signal processing circuit, triggering the signal processing circuit to save data when the power supply input signal is lower than a preset power supply threshold; a flyback control circuit coupled to the input detection circuit; an auxiliary power storage circuit coupled to the flyback control circuit and coupled to the signal processing circuit, discharging stored energy into the signal processing circuit when the flyback control circuit shuts off its output; a switch control circuit coupled to the optocoupler isolation circuit and the auxiliary power storage circuit; and a power supply output control circuit coupled to the optocoupler isolation circuit and the auxiliary power storage circuit, and coupled to a load circuit. Through the above methods, the power-off retention circuit of this application can effectively maintain power in any state, including power input failure, control signal shutdown, and switch failure.

Description

Technical Field

[0001] This application relates to the field of circuit signal processing technology, and in particular to a power-off retention circuit and electronic device. Background Technology

[0002] Nowadays, with the increasing variety of electronic products on the market, users have higher and higher requirements for the performance of power supplies for various electronic products, especially how to achieve power-off retention function to maintain the output voltage for a certain period of time, so as to complete necessary tasks such as data saving and signal transmission within the voltage retention time.

[0003] However, power supply circuits in related technologies can usually only effectively maintain power loss after the power input is cut off, but cannot effectively maintain power loss in any state of power input failure, control signal shutdown, or switch power failure. As a result, there are still risks such as loss of stored data and failure to send critical communication signals in a timely manner. Utility Model Content

[0004] The main technical problem addressed by this application is to provide a power-off retention circuit and electronic device that can solve the problem that existing power circuits cannot effectively maintain power-off in any state of power input failure, control signal shutdown, or switch power failure, thus still having the risk of data loss and failure to send critical communication signals in a timely manner.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a power-off retention circuit, wherein the power-off retention circuit includes: an input detection circuit, coupled to a power supply circuit, configured to acquire a power supply input signal from the power supply circuit; an optocoupler isolation circuit, coupled to the input detection circuit and coupled to a signal processing circuit, configured to trigger the signal processing circuit to save data when the power supply input signal is lower than a preset power supply threshold; a flyback control circuit, coupled to the input detection circuit, configured to delay and turn off the output for a preset time when the power supply input signal is lower than the preset power supply threshold; and an auxiliary power storage circuit, coupled to the flyback control circuit and coupled to the signal processing circuit. The energy storage power supply circuit is configured to discharge energy to the signal processing circuit when the flyback control circuit turns off its output. The switch control circuit, coupled to the optocoupler isolation circuit and the auxiliary energy storage power supply circuit, and used to couple with the signal processing circuit, is configured to control the optocoupler isolation circuit to trigger the signal processing circuit to save data and trigger the flyback control circuit to turn off its output when it is triggered to turn off. The power output control circuit, coupled to the optocoupler isolation circuit and the auxiliary energy storage power supply circuit, and used to couple with the load circuit, is configured to control the optocoupler isolation circuit to trigger the signal processing circuit to save data and trigger the auxiliary energy storage power supply circuit to discharge energy to the signal processing circuit when it receives the corresponding switch trigger signal sent by the load circuit.

[0006] The input detection circuit includes a sampling control circuit, a primary signal processing circuit, and a signal detection circuit. The sampling control circuit is coupled to the primary signal processing circuit and is used to couple with the power supply circuit. The primary signal processing circuit is coupled to an optocoupler isolation circuit. The signal detection circuit is coupled to a flyback control circuit and is used to couple with the power supply circuit.

[0007] The power failure holding circuit also includes a primary power supply output control circuit and a buck converter circuit. The primary power supply output control circuit is coupled to the power supply output control circuit and the buck converter circuit, and the buck converter circuit is coupled to the primary signal processing circuit.

[0008] The power-off retention circuit also includes an electromagnetic filter circuit, a rectifier boost circuit, and a voltage conversion circuit. The electromagnetic filter circuit is coupled to the sampling control circuit and the rectifier boost circuit, and is used to couple with the power supply circuit. The rectifier boost circuit is coupled to the primary signal processing circuit and the voltage conversion circuit. The voltage conversion circuit is coupled to the optocoupler isolation circuit, and is used to couple with the signal processing circuit and the load circuit.

[0009] The power failure holding circuit also includes a primary energy storage power supply circuit, a pulse width control circuit, an auxiliary power output rectifier circuit, and an optocoupler feedback circuit. The primary energy storage power supply circuit is coupled to the flyback control circuit and the auxiliary power output rectifier circuit. The pulse width control circuit is coupled to the flyback control circuit, the auxiliary power output rectifier circuit, and the optocoupler feedback circuit. The auxiliary power output rectifier circuit is coupled to the optocoupler feedback circuit and the power supply output control circuit. The optocoupler feedback circuit is coupled to the power supply output control circuit.

[0010] The optocoupler isolation circuit includes a first resistor, a second resistor, a first diode, a second diode, a third diode, a third resistor, a control chip, a fourth resistor, and a fifth resistor. The first end of the first resistor is coupled to the first end of the input detection circuit; the second end of the first resistor is coupled to the first end of the control chip; the first end of the second resistor is coupled to the second end of the input detection circuit; the second end of the second resistor is coupled to the first end of the first diode; the first end of the first diode is coupled to the second ends of the second diode, the second ends of the third diode, and the first end of the third resistor; the first end of the second diode is coupled to the first end of the switch control circuit; the first end of the third diode is grounded; the second end of the third resistor is coupled to the second end of the control chip; the third end of the control chip is coupled to the first end of the fourth resistor; the second end of the fourth resistor is used to couple to the first end of the signal processing circuit; the fourth end of the control chip is coupled to the first end of the fifth resistor; the second end of the fifth resistor is used to couple to the second end of the signal processing circuit; the first power supply terminal of the control chip is coupled to the first level providing terminal; the second power supply terminal of the control chip is coupled to the second level providing terminal; and the ground terminal of the control chip is grounded.

[0011] The auxiliary power storage circuit includes a first switching transistor, a first capacitor, a fourth diode, a fifth diode, a sixth resistor, and a first energy storage capacitor. The first terminal of the first switching transistor is coupled to the first terminal of the auxiliary power storage circuit. The second terminal of the first switching transistor is coupled to the first terminal of the fifth diode and the first terminal of the first energy storage capacitor, and is used to couple to the third terminal of the signal processing circuit. The third terminal of the first switching transistor is coupled to the second terminal of the auxiliary power storage circuit, the first terminal of the first capacitor, the second terminal of the fourth diode, the second terminal of the fifth diode, and the first terminal of the sixth resistor. The second terminal of the first capacitor is coupled to the first terminal of the fourth diode, the second terminal of the sixth resistor, and the second terminal of the first energy storage capacitor and is grounded.

[0012] The power supply output control circuit includes a seventh resistor, a sixth diode, an eighth resistor, a ninth resistor, a second switch, a tenth resistor, a second capacitor, a third switch, an eleventh resistor, a seventh diode, a fourth switch, a twelfth resistor, a thirteenth resistor, a fifth switch, a third capacitor, a fourth capacitor, and a fourteenth resistor. The first terminal of the seventh resistor is coupled to the first terminal of the first switch and the first terminal of the eighth resistor. The second terminal of the seventh resistor is coupled to the second terminal of the sixth diode, and the first terminal of the sixth diode is grounded. The second terminal of the eighth resistor is coupled to the first terminal of the ninth resistor and the first terminal of the second switch. The second terminal of the ninth resistor is coupled to the third terminal of the second switch. The first terminal of the tenth resistor is coupled to the first terminal of the second capacitor. The second terminal of the second switch is coupled to the third terminal of the first switch. The second terminal of the tenth resistor is coupled to the first terminal of the third switch. The second terminal of the second capacitor is grounded. The second terminal of the third switch is coupled to the second terminal of the fourth switch. The third terminal of the third switch is coupled to the first terminal of the eleventh resistor. The second terminal of the eleventh resistor is coupled to the first terminal of the seventh diode, the third terminal of the fourth switch, and the first terminal of the twelfth resistor. The second terminal of the seventh diode is coupled to the second terminal of the fourth resistor. The first terminal of the fourth switch is coupled to the second terminal of the thirteenth resistor, the first terminal of the fifth switch, and the first terminal of the third capacitor, and is used to couple with the load circuit. The second terminal of the twelfth resistor is coupled to the first terminal of the thirteenth resistor, the third terminal of the fifth switch, and the third level providing terminal. The second terminal of the third capacitor is grounded. The second terminal of the fifth switch is coupled to the first terminal of the fourth capacitor, the first terminal of the fourteenth resistor, and the fourth level providing terminal. The second terminal of the fourth capacitor is coupled to the second terminal of the fourteenth resistor and grounded.

[0013] The switching control circuit includes a control switch, a fifteenth resistor, a sixteenth resistor, an eighth diode, a seventeenth resistor, an eighteenth resistor, a sixth switching transistor, a fifth capacitor, a nineteenth resistor, and a twentieth resistor. The first terminal of the control switch is coupled to the first terminals of the fifteenth and sixteenth resistors, the second terminal of the eighth and seventeenth diodes, and the first terminal of the second diode. The second terminal of the control switch is coupled to the second terminal of the fifteenth resistor and grounded. The second terminal of the sixteenth resistor is coupled to the first terminals of the eighth diode, the eighteenth resistor, the sixth switching transistor, and the fifth capacitor. The second terminal of the seventeenth resistor is coupled to the first terminal of the flyback control circuit. The second terminal of the eighteenth resistor is coupled to the second terminals of the sixth switching transistor, the fifth capacitor, and the nineteenth resistor and grounded. The third terminal of the sixth switching transistor is coupled to the first terminal of the twentieth resistor. The second terminal of the nineteenth resistor is coupled to the second terminal of the twentieth resistor and the second terminal of the flyback control circuit.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide an electronic device, wherein the electronic device includes a housing and a power-off holding circuit connected to the housing; wherein the power-off holding circuit is the power-off holding circuit as described in any of the preceding claims.

[0015] The beneficial effects of this application are as follows: Unlike the prior art, the input detection circuit in the power-off retention circuit provided in this application is configured to acquire the power supply input signal of the power supply circuit. When the power supply input signal is lower than the preset power supply threshold, the optocoupler isolation circuit triggers the signal processing circuit to save data. When the power supply input signal is lower than the preset power supply threshold, that is, when the power input is cut off, the flyback control circuit delays the output for a preset time to shut down. When the flyback control circuit shuts down the output, the auxiliary power storage circuit stores and discharges energy for the signal processing circuit. When the switch control circuit is triggered to shut down, that is, when the switch is de-energized, the optocoupler isolation circuit is controlled to trigger the signal processing circuit to save data and triggers the flyback control circuit to shut down the output. When the power supply output control circuit receives the corresponding switch trigger signal sent by the load circuit, the optocoupler isolation circuit triggers the signal processing circuit to save data and triggers the auxiliary power storage circuit to store and discharge energy for the signal processing circuit. Thus, power-off retention can be effectively achieved in any state of power input failure, control signal shutdown, and switch de-energization, so as to effectively avoid risks such as loss of stored data and failure to send critical communication signals in a timely manner. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0017] Figure 1 This is a schematic diagram of the first embodiment of the power-off retention circuit of this application;

[0018] Figure 2 This is a schematic diagram of the second embodiment of the power-off retention circuit of this application;

[0019] Figure 3 This is a schematic diagram of the third embodiment of the power-off retention circuit of this application;

[0020] Figure 4 yes Figure 3 A schematic diagram of a specific embodiment of the optocoupler isolation circuit in the interruption-holding circuit;

[0021] Figure 5 yes Figure 3 A schematic diagram of a specific embodiment of the auxiliary power storage circuit in the interruptible power retention circuit;

[0022] Figure 6 yes Figure 3 A schematic diagram of a specific embodiment of the power supply output control circuit in an interruption-resistance circuit;

[0023] Figure 7 yes Figure 3 A schematic diagram of a specific embodiment of the flyback control circuit, switch control circuit, signal detection circuit, primary energy storage power supply circuit, pulse width control circuit, auxiliary power output rectifier circuit, and optocoupler feedback circuit in the interrupt power holding circuit.

[0024] Figure 8 yes Figure 3 A schematic diagram of a specific embodiment of the primary power supply output control circuit in an interruption-resistance circuit;

[0025] Figure 9 yes Figure 3 A schematic diagram of a specific embodiment of the sampling control circuit, electromagnetic filter circuit, and rectifier boost circuit in the interruption power-holding circuit;

[0026] Figure 10 This is a flowchart illustrating a specific embodiment of the voltage conversion circuit in the power-off retention circuit of this application;

[0027] Figure 11 This is a schematic diagram of one embodiment of the electronic device of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0030] In this document, the term "implementation" means that a specific feature, structure, or characteristic described in connection with an implementation may be included in at least one implementation of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same implementation, nor is it a separate or alternative implementation mutually exclusive with other implementations. It will be explicitly and implicitly understood by those skilled in the art that the implementations described herein can be combined with other implementations.

[0031] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] Please see Figure 1 , Figure 1 This is a schematic diagram of the first embodiment of the power-off retention circuit of this application. In this embodiment, the power-off retention circuit 10 includes an input detection circuit 11, an optocoupler isolation circuit 12, a flyback control circuit 13, an auxiliary power storage circuit 14, a switch control circuit 15, and a power output control circuit 16.

[0033] The power-off retention circuit 10 provided in this application is specifically applied to any reasonable electronic device with data storage needs, such as a server, computer, or tablet computer. It maintains power to the signal processing circuit 102 for a certain period of time when any of the following states occur: power input failure, control signal shutdown, or switch failure, effectively preventing data loss. Of course, in other embodiments, the power-off retention circuit 10 can also be applied to routers, walkie-talkies, or other reasonable electronic devices with communication needs; this embodiment does not limit this application.

[0034] It is worth noting that the term "coupled" in this article refers to any direct or indirect connection. Therefore, if the article describes a first circuit coupled to a second circuit, it means that the first circuit can be directly connected to the second circuit via electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly connected to the second circuit via other circuits or connection methods via electrical connection or signal connection.

[0035] Specifically, the input detection circuit 11 is used to couple with the power supply circuit 101 to monitor the power supply input signal of the power supply circuit 101 in real time, and when the power supply input signal is detected to be lower than the preset power supply threshold, it is also used to output a low level or interrupt signal.

[0036] The optocoupler isolation circuit 12 is coupled to the input detection circuit 11 and is also used to couple to the signal processing circuit 102 to achieve electrical isolation between the power supply circuit 101 and the signal processing circuit 102, preventing current disturbances in the power supply circuit 101 from affecting the signal processing circuit 102. Furthermore, the optocoupler isolation circuit 12 is also used to detect whether the power supply input signal is lower than a preset power supply threshold, or to receive a low-level or interrupt signal output by the input detection circuit 11 when it detects that the power supply input signal is lower than the preset power supply threshold, thereby triggering the signal processing circuit 102 to save data.

[0037] It is worth noting that the power supply circuit 101 refers to the power supply for the entire circuit, and can be any reasonable power source such as grid power supply, photovoltaic power supply or independent power supply, or a functional circuit that obtains the power input signal after power conversion and adjustment. This application does not limit it in this regard.

[0038] The signal processing circuit 102 refers to a circuit that has one or more of any reasonable signal functions such as data storage, program execution, data processing, and communication processing, and this application does not limit it.

[0039] In addition, the preset power supply threshold is the voltage or current threshold of the power supply input signal that is reduced to a level that cannot meet the normal operation of the signal processing circuit 102 when the power supply circuit 101 fails to operate. This application does not limit this.

[0040] The flyback control circuit 13 is coupled to the input detection circuit 11. The flyback control circuit 13 is used to detect whether the power supply input signal is lower than the preset power supply threshold, or to receive the low level or interrupt signal output by the input detection circuit 11 when the power supply input signal is lower than the preset power supply threshold. In response to the power supply input signal being lower than the preset power supply threshold, i.e., the power supply input is cut off, or a low level or interrupt signal is received, the output is turned off after a preset time delay. For example, it can be used with a delay logic circuit to achieve controllable shutdown of the signal output.

[0041] The auxiliary power storage circuit 14 is coupled to the flyback control circuit 13 and is used to couple to the signal processing circuit 102. The auxiliary power storage circuit 14 may specifically include one or more of the following energy storage elements: supercapacitor, large-capacity electrolytic capacitor, small lithium battery, etc. When the flyback control circuit 13 is turned off, the energy storage element can store and discharge energy to the signal processing circuit 102, thereby maintaining the operating voltage of the signal processing circuit 102 within the normal range for a period of time, so as to ensure the completion of one or more of any reasonable key tasks such as data writing, storage, and timely transmission of key communication signals. This application does not limit this.

[0042] The switch control circuit 15 is coupled to the optocoupler isolation circuit 12 and the auxiliary power storage circuit 14, and is also coupled to the signal processing circuit 102. The switch control circuit 15 is configured to be turned off when the switch button inside is triggered. That is, when the user triggers the switch to turn off the power, the optocoupler isolation circuit 12 controls the signal processing circuit 102 to output a high level or a data saving control command to trigger the signal processing circuit 102 to save data and trigger the flyback control circuit 13 to turn off the output so that the auxiliary power storage circuit 14 can store and discharge energy to the signal processing circuit 102, thereby maintaining the operating voltage of the signal processing circuit 102 within the normal range for a period of time, so as to complete the corresponding data saving task in a timely manner.

[0043] The power output control circuit 16 is coupled to the optocoupler isolation circuit 12 and the auxiliary power storage circuit 14, and is used to couple with the load circuit 103. When the power output control circuit 16 receives a switch trigger signal sent by the load circuit 103, such as a shutdown program command, a low level or a fault command, it controls the optocoupler isolation circuit 12 to trigger the signal processing circuit 102 to save data, and at the same time triggers the auxiliary power storage circuit 14 to discharge energy to the signal processing circuit 102, so as to maintain the operating voltage of the signal processing circuit 102 within the normal range for a period of time.

[0044] The above scheme effectively achieves power-off retention in any state of power input signal being lower than a preset power supply threshold, by triggering the signal processing circuit 102 to save data and causing the flyback control circuit 13 to shut down its output after a preset delay. Furthermore, when the flyback control circuit 13 shuts down its output, the auxiliary power storage circuit 14 discharges energy into the signal processing circuit 102. When the switch control circuit 15 triggers shutdown, it controls the optocoupler isolation circuit 12 to trigger the signal processing circuit 102 to save data and triggers the flyback control circuit 13 to shut down its output. When the power output control circuit 16 receives the corresponding switch trigger signal from the load circuit 103, it triggers the signal processing circuit 102 to save data and triggers the auxiliary power storage circuit 14 to discharge energy into the signal processing circuit 102. This effectively avoids risks such as data loss and failure to send critical communication signals in a timely manner.

[0045] Please see Figure 2 , Figure 2 This is a schematic diagram of the second embodiment of the power-off retention circuit of this application. The difference between the power-off retention circuit in this embodiment and the first embodiment of the power-off retention circuit provided in this application is that the input detection circuit 21 in this power-off retention circuit 20 specifically includes a sampling control circuit 211, a primary signal processing circuit 212, and a signal detection circuit 213.

[0046] The sampling control circuit 211 is coupled to the primary signal processing circuit 212 and is used to be coupled to the power supply circuit 101. The primary signal processing circuit 212 is coupled to the optocoupler isolation circuit 22. The sampling control circuit 211 is configured to sample and acquire the power supply input signal of the power supply circuit 101. When the power supply input signal is detected to be lower than a preset power supply threshold, it feeds back to the primary signal processing circuit 212 so that the primary signal processing circuit 212 outputs a low level or a data storage command to the optocoupler isolation circuit 22, thereby triggering the signal processing circuit 102 to save the data.

[0047] The signal detection circuit 213 is coupled to the flyback control circuit 23 and is used to be coupled to the power supply circuit 101. When the power supply input signal is detected to be lower than the preset power supply threshold, it feeds back to the flyback control circuit 23 so that the flyback control circuit 23 shuts off the output after a preset time delay, thereby triggering the auxiliary power storage circuit 24 signal processing circuit 102 to perform energy storage discharge.

[0048] In some embodiments, the power-off holding circuit 20 further includes a primary power supply output control circuit 27 and a buck converter circuit 28. The primary power supply output control circuit 27 is coupled to the power supply output control circuit 26 and the buck converter circuit 28. The buck converter circuit 28 is coupled to the primary signal processing circuit 212. When the primary power supply output control circuit 27 receives the switch trigger signal sent by the load circuit 103 synchronously with the power supply output control circuit 26, it is also used to maintain the power supply output to the primary signal processing circuit 212 for a certain period of time through the buck converter circuit 28, so as to ensure that the primary power supply output control circuit 27 can maintain the output of low level or data storage command to the optocoupler isolation circuit 22.

[0049] In some embodiments, the power-off holding circuit 20 further includes an electromagnetic filter circuit 29, a rectifier boost circuit 2101, and a voltage conversion circuit 2102. The electromagnetic filter circuit 29 is coupled to the sampling control circuit 211 and the rectifier boost circuit 2101, and is used to couple with the power supply circuit 101. The rectifier boost circuit 2101 is coupled to the primary signal processing circuit 212 and the voltage conversion circuit 2102. The voltage conversion circuit 2102 is coupled to the optocoupler isolation circuit 22, and is used to couple with the signal processing circuit 102 and the load circuit 103.

[0050] The electromagnetic filter circuit 29, the rectifier boost circuit 2101, and the voltage conversion circuit 2102 are configured to receive the power input signal from the power supply circuit 101, and then perform one or more of the following reasonable adjustments and controls, such as filtering, rectification, and voltage conversion, to supply power to the load circuit 103.

[0051] The sampling control circuit 211 actually performs sampling and detection of the filtered power input signal; and the primary signal processing circuit 212, optocoupler isolation circuit 22, and signal processing circuit 102 are also used to perform signal interaction on the power input signal during adjustment in order to achieve the corresponding signal function. This application does not limit this.

[0052] It is worth noting that the load circuit 103 can be understood as the circuit board in the electronic device that sets the power failure retention circuit 20, which integrates one or more of any reasonable functional electronic devices such as program instruction control chip, indicator light, and cooling fan, and can send a switch trigger signal to the power supply output control circuit 26 in response to program shutdown control command, fault shutdown command or fault power failure. This application does not limit this.

[0053] It is understood that the optocoupler isolation circuit 22, flyback control circuit 23, auxiliary power storage circuit 24, switch control circuit 25, and power output control circuit 26 in this embodiment are the same as the input detection circuit 11, optocoupler isolation circuit 12, flyback control circuit 13, auxiliary power storage circuit 14, switch control circuit 15, and power output control circuit 16, respectively. Please refer to the following for details. Figure 1 The relevant textual content will not be repeated here.

[0054] Please see Figure 3 , Figure 3 This is a schematic diagram of the third embodiment of the power-off retention circuit of this application. The difference between the power-off retention circuit in this embodiment and the second embodiment of the power-off retention circuit provided in this application is that the power-off retention circuit 30 specifically includes a primary energy storage power supply circuit 3104, a pulse width control circuit 3105, an auxiliary power output rectifier circuit 3106, and an optocoupler feedback circuit 3103.

[0055] The primary energy storage power supply circuit 3104 is coupled to the flyback control circuit 33 and the auxiliary power output rectifier circuit 3106. The pulse width control circuit 3105 is coupled to the flyback control circuit 33, the auxiliary power output rectifier circuit 3106 and the optocoupler feedback circuit 3103. The auxiliary power output rectifier circuit 3106 is coupled to the optocoupler feedback circuit 3103 and the power output control circuit 36. The optocoupler feedback circuit 3103 is coupled to the power output control circuit 36.

[0056] Understandably, when the flyback control circuit 33 shuts off its output, the pulse width control circuit 3105 is used to shut off the corresponding level outputs in the auxiliary power output rectifier circuit 3106 and the optocoupler feedback circuit 3103, so that the primary energy storage power supply circuit 3104 and the auxiliary energy storage power supply circuit 34 can discharge and output using their previous stored energy, thereby maintaining the signal processing circuit 102 to save data in a timely manner.

[0057] Please continue to refer to the following: Figure 4 , Figure 4 yes Figure 3 A schematic diagram of a specific embodiment of the optocoupler isolation circuit in the interrupted power-holding circuit.

[0058] In some embodiments, the optocoupler isolation circuit 32 includes a first resistor R1, a second resistor R2, a first diode D1, a second diode D2, a third diode D3, a third resistor R3, a control chip U1, a fourth resistor R4, and a fifth resistor R5.

[0059] Specifically, the first terminal of the first resistor R1 is coupled to the first terminal of the input detection circuit 31, and the second terminal of the first resistor R1 is coupled to the first terminal INA of the control chip U1. The first terminal of the second resistor R2 is coupled to the second terminal of the input detection circuit 31, and the second terminal of the second resistor R2 is coupled to the first terminal of the first diode D1. The first terminal of the first diode D1 is coupled to the second terminals of the second diode D2, the second terminals of the third diode D3, and the first terminal of the third resistor R3. The first terminal of the second diode D2 is coupled to the first terminal of the switch control circuit 35, and the first terminal of the third diode D3 is grounded. The second terminal of the third resistor R3 is coupled to the first terminal of the switch control circuit 35. The second terminal INB of the control chip U1 is coupled to the third terminal OUTA of the control chip U1, which is coupled to the first terminal of the fourth resistor R4. The second terminal of the fourth resistor R4 is used to couple to the first terminal of the signal processing circuit 102. The fourth terminal OUTB of the control chip U1 is coupled to the first terminal of the fifth resistor R5, which is used to couple to the second terminal of the signal processing circuit 102. The first power supply terminal VCC1 of the control chip U1 is coupled to the first level providing terminal Vcp1. The second power supply terminal VCC2 of the control chip U1 is coupled to the second level providing terminal Vcs1. The ground terminal of the control chip U1 is grounded.

[0060] In some embodiments, the control chip U1 may specifically include one or more of any reasonable circuit units with signal processing functions, such as a DSP (Digital Signal Processing) chip, an MCU (Micro Controller Unit) circuit, a CPU (Central Processing Unit), a microcontroller, a field-programmable gate array, a programmable logic device, discrete gate or transistor logic devices, or discrete hardware. This application does not limit the scope of the application.

[0061] Please continue to refer to the following: Figure 5 , Figure 5 yes Figure 3 A schematic diagram of a specific embodiment of the auxiliary power storage circuit in the interrupted power holding circuit.

[0062] In some embodiments, the auxiliary power storage circuit 34 further includes a first switching transistor Q1, a first capacitor C1, a fourth diode D4, a fifth diode D5, a sixth resistor R6, and a first energy storage capacitor EC1.

[0063] The first terminal of the first switching transistor Q1 is coupled to the first terminal of the auxiliary power storage circuit 34. The second terminal of the first switching transistor Q1 is coupled to the first terminal of the fifth diode D5 and the first terminal of the first energy storage capacitor EC1, and is used to couple to the third terminal of the signal processing circuit 102. The third terminal of the first switching transistor Q1 is coupled to the second terminal of the auxiliary power storage circuit 34, the first terminal of the first capacitor C1, the second terminal of the fourth diode D4, the second terminal of the fifth diode D5, and the first terminal of the sixth resistor R6. The second terminal of the first capacitor C1 is coupled to the first terminal of the fourth diode D4, the second terminal of the sixth resistor R6, and the second terminal of the first energy storage capacitor EC1 and is grounded.

[0064] In another embodiment, the first terminal of the first energy storage capacitor EC1 is specifically used to couple to a BUCK (step-down converter) circuit, so as to couple to the third terminal of the signal processing circuit 102 via the BUCK circuit; and the first terminal of the first energy storage capacitor EC1 is also used to couple to a voltage conversion circuit 3102, which is not limited in this application.

[0065] Please continue to refer to the following: Figure 6 , Figure 6 yes Figure 3 A schematic diagram of a specific embodiment of the power supply output control circuit in an interrupted power holding circuit.

[0066] In some embodiments, the power supply output control circuit 36 ​​includes a seventh resistor R7, a sixth diode D6, an eighth resistor R8, a ninth resistor R9, a second switch Q2, a tenth resistor R10, a second capacitor C2, a third switch Q3, an eleventh resistor R11, a seventh diode D7, a fourth switch Q4, a twelfth resistor R12, a thirteenth resistor R13, a fifth switch Q5, a third capacitor C3, a fourth capacitor C4, and a fourteenth resistor R14.

[0067] Among them, the first end of the seventh resistor R7 is coupled to the first end of the first switch Q1 and the first end of the eighth resistor R8; the second end of the seventh resistor R7 is coupled to the second end of the sixth diode D6, and the first end of the sixth diode D6 is grounded; the second end of the eighth resistor R8 is coupled to the first end of the ninth resistor R9 and the first end of the second switch Q2; the second end of the ninth resistor R9 is coupled to the third end of the second switch Q2; the first end of the tenth resistor R10 and the first end of the second capacitor C2; the second end of the second switch Q2 is coupled to the third end of the first switch Q1; the second end of the tenth resistor R10 is coupled to the first end of the third switch Q3; the second end of the second capacitor C2 is grounded; the second end of the third switch Q3 is coupled to the second end of the fourth switch Q4; and the third end of the third switch Q3 is coupled to the first end of the eleventh resistor R11. The second end of resistor eleven (R11) is coupled to the first end of diode seven (D7), the third end of switch four (Q4), and the first end of resistor twelfth (R12). The second end of diode seven (D7) is coupled to the second end of resistor four (R4). The first end of switch four (Q4) is coupled to the second end of resistor thirteen (R13), the first end of switch five (Q5), and the first end of capacitor three (C3), and is used to couple to load circuit 103. The second end of resistor twelfth (R12) is coupled to the first end of resistor thirteenth (R13), the third end of switch five (Q5), and the third level providing terminal. The second end of capacitor three (C3) is grounded. The second end of switch five (Q5) is coupled to the first end of capacitor fourteen (C4), the first end of resistor fourteen (R14), and the fourth level providing terminal. The second end of capacitor fourteen (C4) is coupled to the second end of resistor fourteen (R14) and grounded.

[0068] Please continue to refer to the following: Figure 7 , Figure 7 yes Figure 3 A schematic diagram of a specific embodiment of the flyback control circuit, switch control circuit, signal detection circuit, primary energy storage power supply circuit, pulse width control circuit, auxiliary power output rectifier circuit, and optocoupler feedback circuit in the interrupt power holding circuit.

[0069] In some embodiments, the switch control circuit 35 includes a control switch S1, a fifteenth resistor R15, a sixteenth resistor R16, an eighth diode D8, a seventeenth resistor R17, an eighteenth resistor R18, a sixth switch Q6, a fifth capacitor C5, a nineteenth resistor R19, and a twentieth resistor R20.

[0070] Specifically, the first terminal of control switch S1 is coupled to the first terminal of the fifteenth resistor R15, the first terminal of the sixteenth resistor R16, the second terminal of the eighth diode D8, the first terminal of the seventeenth resistor R17, and the first terminal of the second diode D2. The second terminal of control switch S1 is coupled to the second terminal of the fifteenth resistor R15 and grounded. The second terminal of the sixteenth resistor R16 is coupled to the first terminal of the eighth diode D8, the first terminal of the eighteenth resistor R18, the first terminal of the sixth switch Q6, and the first terminal of the fifth capacitor C5. The second terminal of the seventeenth resistor R17 is coupled to the first terminal of the flyback control circuit 33. The second terminal of the eighteenth resistor R18 is coupled to the second terminal of the sixth switch Q6, the second terminal of the fifth capacitor C5, and the first terminal of the nineteenth resistor R19 and grounded. The third terminal of the sixth switch Q6 is coupled to the first terminal of the twentieth resistor R20. The second terminal of the nineteenth resistor R19 is coupled to the second terminal of the twentieth resistor R20 and the second terminal of the flyback control circuit 33.

[0071] In some embodiments, the optocoupler isolation circuit 32 specifically further includes a twenty-first resistor R21, a twenty-second resistor R22, a sixth capacitor C6, a twenty-third resistor R23, a twenty-fourth resistor R24, a seventh capacitor C7, a grounding capacitor Cd, a twenty-sixth resistor R26, a twenty-seventh resistor R27, an eighth capacitor C8, a ninth capacitor C9, and a twenty-eighth resistor R28; wherein, the first end of the twenty-first resistor R21 is coupled to the third end of the input detection circuit 31, the second end of the twenty-first resistor R21 is coupled to the first end of the twenty-fourth resistor R24 ​​and the fifth end of the control chip U1, the first end of the twenty-second resistor R22 is coupled to the fourth end of the input detection circuit 31, the second end of the twenty-second resistor R22 is coupled to the sixth end of the control chip U1, the first end of the sixth capacitor C6 is coupled to the second end of the first resistor R1 and the first end of the twenty-third resistor R23, the second end of the sixth capacitor C6 is coupled to the second end of the twenty-third resistor R23, the first end of the third diode D3, the second end of the twenty-fourth resistor R24, and the seventh capacitor Cd; The second terminal of capacitor 7, the second terminal of grounding capacitor Cd, the first terminal of the seventh capacitor C7 are coupled to the first terminal of grounding capacitor Cd, the first level providing terminal Vcp1, the first power supply terminal VCC1 of control chip U1, the seventh terminal of control chip U1, control chip U1 has two mutually coupled first ground terminals, two mutually coupled second ground terminals, the two second ground terminals are coupled to the second terminal of eighth capacitor C8, the second terminal of ninth capacitor C9, the second terminal of twenty-eighth resistor R28 and grounded, the second power supply terminal VCC2 of control chip U1 is coupled to the first level providing terminal Vcp1, the first terminal of eighth capacitor C8, the first terminal of ninth capacitor C9, the eighth terminal of control chip U1 is coupled to the first terminal of twenty-sixth resistor R26, the eighth terminal of control chip U1 is coupled to the first terminal of twenty-seventh resistor R27, the second terminal of twenty-sixth resistor R26 is used to couple to the third terminal of signal processing circuit 102, the second terminal of twenty-seventh resistor R27 is coupled to the first terminal of twenty-eighth resistor R28 and is used to couple to the fourth terminal of signal processing circuit 102.

[0072] In some embodiments, the flyback control circuit 33 includes a flyback control chip U2 and a flyback resistor Rf0; the signal detection circuit 313 includes a ninth diode D9, a tenth diode D10, and a tenth capacitor C10; the primary energy storage power supply circuit 3104 includes an eleventh diode D11, a seventh switch Q7, a tenth diode D12, an eleventh capacitor C11, a twenty-ninth resistor R29, and a second energy storage capacitor EC2; the pulse width control circuit 3105 includes a sixteenth diode D16, a thirty-fourth resistor R34, a thirty-fifth resistor R35, an eighth switch Q8, a thirty-sixth resistor R36, a thirty-seventh resistor R37, a thirty-eighth resistor R38, and a thirty-ninth resistor R39; the power-off retention circuit 30 specifically also includes a flyback peripheral circuit 331, an energy storage power supply peripheral circuit 31041, and an auxiliary power output peripheral circuit. The circuit consists of circuit 31061, optocoupler feedback peripheral circuit 31031, flyback peripheral circuit 331 including fourteenth diode D14, thirteenth capacitor C13, fourteenth capacitor C14, thirty-first resistor R31, fifteenth capacitor C15, thirty-second resistor R32, fifteenth diode D15, and thirty-third resistor R33; energy storage power supply peripheral circuit 31041 including thirteenth diode D13, thirtieth resistor R30, and twelfth capacitor C12; auxiliary power output peripheral circuit 31061 including first isolation transformer T1, first isolation transformer T1 including first main winding N1, second main winding N2, first secondary winding N3, and second secondary winding N4; optocoupler feedback peripheral circuit 31031 including first optocoupler P1 and sixteenth capacitor C16; wherein, the connection method of the above circuit components is as follows: Figure 7 As shown, it will not be elaborated further here.

[0073] In some embodiments, the flyback control chip U2 may specifically include one or more of any reasonable circuit units with signal processing functions, such as a DSP (Digital Signal Processing) chip, an MCU (Micro Controller Unit) circuit, a CPU (Central Processing Unit), a microcontroller, a field-programmable gate array, a programmable logic device, discrete gate or transistor logic devices, or discrete hardware. This application does not limit the specific components in this regard.

[0074] Please continue to refer to the following: Figure 8 , Figure 9 , Figure 10 ,in, Figure 8 yes Figure 3 A schematic diagram of a specific embodiment of the primary power supply output control circuit in an interrupted power holding circuit. Figure 9 yes Figure 3A schematic diagram of a specific embodiment of the sampling control circuit, electromagnetic filter circuit, and rectifier boost circuit in the interruptible power-holding circuit; please refer to further details. Figure 10 , Figure 10 This is a flowchart illustrating a specific embodiment of the voltage conversion circuit in the power-off retention circuit of this application.

[0075] In some embodiments, the primary power supply output control circuit 37 includes a 40th resistor R40, a second optocoupler P2, a 17th capacitor C17, a 41st resistor R41, a 42nd resistor R42, and a 9th switch Q9; the sampling control circuit 311 includes a 42nd resistor R42, a 10th switch Q10, a 17th diode D17, a 43rd resistor R43, a 19th capacitor C19, a 45th resistor R45, a 46th resistor R46, a 47th resistor R47, a 21st capacitor C21, an 18th diode D18, an 11th switch Q11, a 45th resistor R45, a 49th resistor R49, a 48th resistor R48, a 50th resistor R50, a 19th diode D19, a 20th diode D22, a 51st resistor R51, a 22nd capacitor C22, a 23rd capacitor C23, a comparator BJ, a 24th capacitor C24, and a 52nd resistor R 52. The fifty-third resistor R53, the fifty-fourth resistor R54, the twenty-fifth capacitor C25, and the twenty-sixth capacitor C26; the power-off holding circuit 30 specifically also includes a rectifier peripheral circuit 31011, and the voltage conversion circuit 3102 also includes a voltage conversion switch circuit 31021, an output rectifier filter circuit 31022, and a step-down regulation conversion circuit 31023. The rectifier peripheral circuit 31011 includes a rectifier bridge Dq, an eighteenth capacitor C18, and a third energy storage capacitor EC3. The voltage conversion switch circuit 31021 includes a twelfth switch Q12, a thirteenth switch Q13, a twenty-seventh capacitor C27, a twenty-eighth capacitor C28, a twenty-ninth capacitor C29, a thirtieth capacitor C30, and a second isolation transformer T2. The second isolation transformer T2 includes a first main winding N11, a first side winding N12, and a second side winding N13; wherein, the connection method of the above circuit components is as follows: Figures 8-10 As shown, it will not be elaborated further here.

[0076] It is understood that the electromagnetic filter circuit 39, rectifier boost circuit 3101, optocoupler feedback circuit 3103, and auxiliary power output rectifier circuit 3106 in this embodiment are the same as the electromagnetic filter circuit 29, rectifier boost circuit 2101, optocoupler feedback circuit 2103, and auxiliary power output rectifier circuit 2106, respectively. Please refer to [link / reference] for details. Figure 2 The relevant textual content will not be repeated here.

[0077] In some embodiments, the first switch Q1 to the thirteenth switch Q13 may be a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), a transistor, a thin-film transistor, a field-effect transistor, or any other reasonable switch, and this application does not limit it.

[0078] It is worth noting that, to distinguish the two ends of each switching transistor except for the control terminal, one terminal is referred to as the first terminal and the other as the second terminal. When each switching transistor is a bipolar junction transistor (BJT), the control terminal, i.e., the third terminal, can specifically be the base, the first terminal as the collector, and the second terminal as the emitter; or, the third terminal can specifically be the base, the first terminal as the emitter, and the second terminal as the collector.

[0079] When the switching transistors mentioned above are MOSFETs, thin-film transistors, or field-effect transistors, the third terminal can be the gate, the first terminal is the drain, and the second terminal is the source; or, the third terminal can also be the gate, the first terminal is the source, and the second terminal is the drain.

[0080] In particular, when each switching transistor is a MOSFET, a thin film transistor, or a field-effect transistor, it can also be a composite transistor or a single transistor, which is not limited in this application.

[0081] It is worth noting that, such as Figures 4-10 The symbols x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, SBULK, SALERT, PSON#, DRV-AUX, A, and B shown are connection terminal markings given for the convenience of explaining the connection relationship between different circuits. Connection terminals with the same marking are connected to each other, or can be understood as the same connection terminal. VST-L and VST-N can be understood as two sampling terminals for the power supply input signal. Vcp1, Vcs1, Vcs2, PSON#-V1, Vsb1, Vcp2, and V-pfc correspond to different level providing terminals, which can be provided by the power supply circuit 101 or by another power supply regulation circuit to provide specific level outputs, such as 3.3V, 5V, 12V, 15V, etc., any reasonable level. This application does not limit this.

[0082] Understandably, when the power supply circuit 101 loses power, i.e., the power supply input signal is lower than the preset power supply threshold, the sampling control circuit 311 feeds back to the primary signal processing circuit 312. When the primary signal processing circuit 312 detects that the power supply input signal is lower than the preset power supply threshold, it pulls the level of node x1 low and sends the level of node SBULK low to the signal processing circuit 102 through the optocoupler isolation circuit 32. After receiving the low-level signal of node SBULK, the signal processing circuit 102 immediately begins to save data.

[0083] Simultaneously, when the power input fails, the signal detection circuit 313 detects that the power input signal is lower than the preset power supply threshold and feeds it back to the flyback control chip U2. The flyback control chip U2 has a voltage for detecting the power input signal. After a delay, it confirms that the power input signal is lower than the preset power supply threshold and then turns off the output, so that Vcs2 and Vsb1 are turned off. Meanwhile, the first energy storage capacitor EC1 in the auxiliary power storage circuit 34 continues to supply power to the signal processing circuit 102 using its current energy storage, so that it can continue to save data.

[0084] Additionally, when the control switch S1 in the switch control circuit 35 is triggered to turn off, node A is at a high level. The high-level signal is then fed to the second terminal INB of the control chip U1 through the first diode D1 and the third resistor R3. The control chip U1 then raises the level of the SALERT node to a high level and sends it to the signal processing circuit 102. When the signal processing circuit 102 detects the high level of the SALERT node, it immediately begins to save data. At the same time, when the control switch S1 is triggered to turn off, the flyback control chip U2 turns off its output and stops supplying power, so that the first energy storage capacitor EC1 in the auxiliary power storage circuit 34 can continue to supply power to the signal processing circuit 102 using its current energy storage, thereby enabling the signal processing circuit 102 to continue saving data.

[0085] When the load circuit 103 pulls the PSON# node high in response to a program shutdown command or fault shutdown, the B node goes low. When the signal processing circuit 102 receives the SBULK node as low, it immediately starts saving data. At the same time, when the PSON# node is high, the fifth switch Q5 in the power supply output control circuit 36 ​​is turned off, the fourth switch Q4 is turned on, and the second switch Q2 and the third switch Q3 are turned off. The first switch Q1 in the auxiliary power storage circuit 34 is turned off, and the first energy storage capacitor EC1 continues to provide energy to maintain the Vcs2 level output. The signal processing circuit 102 continues to save data.

[0086] Therefore, the power failure retention circuit 30 can effectively ensure that the signal processing circuit 102 saves data in a timely manner after power failure, thus providing users with a good experience.

[0087] This application also employs an electronic device; please refer to [link / reference needed]. Figure 11 , Figure 11 This is a schematic diagram of one embodiment of the electronic device of this application. In this embodiment, the electronic device 40 includes a housing 41 and a power-off retention circuit 42 connected to the housing 41.

[0088] It should be noted that the power-off retention circuit 42 described in this embodiment is any of the power-off retention circuits 10, 20, or 30 described in the above embodiments. Please refer to [link / reference] for details. Figures 1-10 The relevant textual content will not be elaborated upon here.

[0089] The beneficial effects of this application are as follows: Unlike the prior art, the input detection circuit in the power-off retention circuit provided in this application is configured to acquire the power supply input signal of the power supply circuit. When the power supply input signal is lower than the preset power supply threshold, the optocoupler isolation circuit triggers the signal processing circuit to save data. When the power supply input signal is lower than the preset power supply threshold, that is, when the power input is cut off, the flyback control circuit delays the output for a preset time to shut down. When the flyback control circuit shuts down the output, the auxiliary power storage circuit stores and discharges energy for the signal processing circuit. When the switch control circuit is triggered to shut down, that is, when the switch is de-energized, the optocoupler isolation circuit is controlled to trigger the signal processing circuit to save data and triggers the flyback control circuit to shut down the output. When the power supply output control circuit receives the corresponding switch trigger signal sent by the load circuit, the optocoupler isolation circuit triggers the signal processing circuit to save data and triggers the auxiliary power storage circuit to store and discharge energy for the signal processing circuit. Thus, power-off retention can be effectively achieved in any state of power input failure, control signal shutdown, and switch de-energization, so as to effectively avoid risks such as loss of stored data and failure to send critical communication signals in a timely manner.

[0090] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A power-off hold circuit, characterized by comprising: The power-off retention circuit includes: An input detection circuit is used to be coupled to a power supply circuit, the input detection circuit being configured to acquire a power supply input signal from the power supply circuit; An optocoupler isolation circuit is coupled to the input detection circuit and is used to couple to the signal processing circuit. The optocoupler isolation circuit is configured to trigger the signal processing circuit to save data when the power supply input signal is lower than a preset power supply threshold. A flyback control circuit is coupled to the input detection circuit, and the flyback control circuit is configured to turn off the output after a preset time when the power supply input signal is lower than the preset power supply threshold. An auxiliary power storage circuit is coupled to the flyback control circuit and is used to couple with the signal processing circuit. The auxiliary power storage circuit is configured to store and discharge energy to the signal processing circuit when the flyback control circuit turns off its output. A switch control circuit is coupled to the optocoupler isolation circuit and the auxiliary power storage circuit, and is used to be coupled to the signal processing circuit. The switch control circuit is configured to control the optocoupler isolation circuit to trigger the signal processing circuit to save data and trigger the flyback control circuit to turn off the output when the trigger shutdown occurs. A power supply output control circuit is coupled to the optocoupler isolation circuit and the auxiliary power storage circuit, and is used to be coupled to the load circuit. The power supply output control circuit is configured to control the optocoupler isolation circuit to trigger the signal processing circuit to save data when it receives the switch trigger signal sent by the load circuit, and to trigger the auxiliary power storage circuit to discharge energy to the signal processing circuit.

2. The power-off retention circuit according to claim 1, characterized in that, The input detection circuit includes a sampling control circuit, a primary signal processing circuit, and a signal detection circuit. The sampling control circuit is coupled to the primary signal processing circuit and is used to couple with the power supply circuit. The primary signal processing circuit is coupled to the optocoupler isolation circuit. The signal detection circuit is coupled to the flyback control circuit and is used to couple with the power supply circuit.

3. The power-off retention circuit according to claim 2, characterized in that, The power failure holding circuit further includes a primary power supply output control circuit and a buck converter circuit. The primary power supply output control circuit is coupled to the power supply output control circuit and the buck converter circuit, and the buck converter circuit is coupled to the primary signal processing circuit.

4. The power-off retention circuit according to claim 2, characterized in that, The power-off retention circuit further includes an electromagnetic filter circuit, a rectifier boost circuit, and a voltage conversion circuit. The electromagnetic filter circuit is coupled to the sampling control circuit and the rectifier boost circuit, and is used to couple with the power supply circuit. The rectifier boost circuit is coupled to the primary signal processing circuit and the voltage conversion circuit. The voltage conversion circuit is coupled to the optocoupler isolation circuit, and is used to couple with the signal processing circuit and the load circuit.

5. The power-off retention circuit according to claim 1, characterized in that, The power failure holding circuit further includes a primary energy storage power supply circuit, a pulse width control circuit, an auxiliary power output rectifier circuit, and an optocoupler feedback circuit. The primary energy storage power supply circuit is coupled to the flyback control circuit and the auxiliary power output rectifier circuit. The pulse width control circuit is coupled to the flyback control circuit, the auxiliary power output rectifier circuit, and the optocoupler feedback circuit. The auxiliary power output rectifier circuit is coupled to the optocoupler feedback circuit and the power supply output control circuit. The optocoupler feedback circuit is coupled to the power supply output control circuit.

6. The power-off retention circuit according to claim 1, characterized in that, The optocoupler isolation circuit includes a first resistor, a second resistor, a first diode, a second diode, a third diode, a third resistor, a control chip, a fourth resistor, and a fifth resistor; Wherein, the first end of the first resistor is coupled to the first end of the input detection circuit, the second end of the first resistor is coupled to the first end of the control chip, the first end of the second resistor is coupled to the second end of the input detection circuit, the second end of the second resistor is coupled to the first end of the first diode, the first end of the first diode is coupled to the second end of the second diode, the second end of the third diode, and the first end of the third resistor, the first end of the second diode is coupled to the first end of the switch control circuit, the first end of the third diode is grounded, the second end of the third resistor is coupled to the second end of the control chip, the third end of the control chip is coupled to the first end of the fourth resistor, the second end of the fourth resistor is used to couple to the first end of the signal processing circuit, the fourth end of the control chip is coupled to the first end of the fifth resistor, the second end of the fifth resistor is used to couple to the second end of the signal processing circuit, the first power supply terminal of the control chip is coupled to the first level providing terminal, the second power supply terminal of the control chip is coupled to the second level providing terminal, and the ground terminal of the control chip is grounded.

7. The power-off retention circuit according to claim 6, characterized in that, The auxiliary power storage circuit includes a first switching transistor, a first capacitor, a fourth diode, a fifth diode, a sixth resistor, and a first energy storage capacitor. Wherein, the first terminal of the first switching transistor is coupled to the first terminal of the auxiliary power storage circuit, the second terminal of the first switching transistor is coupled to the first terminal of the fifth diode and the first terminal of the first energy storage capacitor, and is used to couple to the third terminal of the signal processing circuit, the third terminal of the first switching transistor is coupled to the second terminal of the auxiliary power storage circuit, the first terminal of the first capacitor, the second terminal of the fourth diode, the second terminal of the fifth diode and the first terminal of the sixth resistor, and the second terminal of the first capacitor is coupled to the first terminal of the fourth diode, the second terminal of the sixth resistor and the second terminal of the first energy storage capacitor and grounded.

8. The power-off retention circuit according to claim 7, characterized in that, The power supply output control circuit includes a seventh resistor, a sixth diode, an eighth resistor, a ninth resistor, a second switch, a tenth resistor, a second capacitor, a third switch, an eleventh resistor, a seventh diode, a fourth switch, a twelfth resistor, a thirteenth resistor, a fifth switch, a third capacitor, a fourth capacitor, and a fourteenth resistor. Wherein, the first terminal of the seventh resistor is coupled to the first terminal of the first switching transistor and the first terminal of the eighth resistor; the second terminal of the seventh resistor is coupled to the second terminal of the sixth diode; the first terminal of the sixth diode is grounded; the second terminal of the eighth resistor is coupled to the first terminal of the ninth resistor and the first terminal of the second switching transistor; the second terminal of the ninth resistor is coupled to the third terminal of the second switching transistor; the first terminal of the tenth resistor and the first terminal of the second capacitor are coupled to the third terminal of the first switching transistor; the second terminal of the tenth resistor is coupled to the first terminal of the third switching transistor; the second terminal of the second capacitor is grounded; the second terminal of the third switching transistor is coupled to the second terminal of the fourth switching transistor; and the third terminal of the third switching transistor is coupled to the first terminal of the eleventh resistor. The second end of the eleventh resistor is coupled to the first end of the seventh diode, the third end of the fourth switch, and the first end of the twelfth resistor. The second end of the seventh diode is coupled to the second end of the fourth resistor. The first end of the fourth switch is coupled to the second end of the thirteenth resistor, the first end of the fifth switch, and the first end of the third capacitor, and is used to couple with the load circuit. The second end of the twelfth resistor is coupled to the first end of the thirteenth resistor, the third end of the fifth switch, and the third level providing terminal. The second end of the third capacitor is grounded. The second end of the fifth switch is coupled to the first end of the fourth capacitor, the first end of the fourteenth resistor, and the fourth level providing terminal. The second end of the fourth capacitor is coupled to the second end of the fourteenth resistor and grounded.

9. The power-off retention circuit according to claim 8, characterized in that, The switch control circuit includes a control switch, a fifteenth resistor, a sixteenth resistor, an eighth diode, a seventeenth resistor, an eighteenth resistor, a sixth switching transistor, a fifth capacitor, a nineteenth resistor, and a twentieth resistor; Wherein, the first terminal of the control switch is coupled to the first terminal of the fifteenth resistor, the first terminal of the sixteenth resistor, the second terminal of the eighth diode, the first terminal of the seventeenth resistor, and the first terminal of the second diode; the second terminal of the control switch is coupled to the second terminal of the fifteenth resistor and grounded; the second terminal of the sixteenth resistor is coupled to the first terminal of the eighth diode, the first terminal of the eighteenth resistor, the first terminal of the sixth switch, and the first terminal of the fifth capacitor; the second terminal of the seventeenth resistor is coupled to the first terminal of the flyback control circuit; the second terminal of the eighteenth resistor is coupled to the second terminal of the sixth switch, the second terminal of the fifth capacitor, and the first terminal of the nineteenth resistor and grounded; the third terminal of the sixth switch is coupled to the first terminal of the twentieth resistor; and the second terminal of the nineteenth resistor is coupled to the second terminal of the twentieth resistor and the second terminal of the flyback control circuit.

10. An electronic device, comprising: The electronic device includes a housing and a power-off retention circuit connected to the housing; The power-off retention circuit is the power-off retention circuit as described in any one of claims 1-9.

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