Switching circuits and electronic equipment

Abstract

This utility model discloses a power-on / off circuit and an electronic device. The power-on / off circuit includes a power-on circuit and a power-off circuit. The input terminal of the power-on circuit is connected to the PWR signal output terminal of the MCU chip, and the output terminal of the power-on circuit is connected to the CBL signal input terminal of the PMU chip. The power-on circuit is adapted to ground the CBL signal input terminal of the PMU chip when the PWR signal output terminal of the MCU chip is at a high level, thereby realizing the power-on operation of the CPU chip. The input terminal of the power-off circuit is connected to the PWR signal output terminal of the MCU chip, and the output terminal of the power-off circuit is connected to the GPIO signal input terminal of the CPU chip. The power-off circuit is adapted to change the level of the GPIO signal input terminal of the CPU chip from low to high when the PWR signal output terminal of the MCU chip is at a low level, thereby realizing the power-off operation of the CPU chip. Thus, the power-on / off of the CPU chip is achieved through the MCU chip, making the power-on / off of the CPU chip independent of human-computer interaction.

Description

Technical Field

[0001] This utility model relates to the field of power on / off circuit technology, and more particularly to a power on / off circuit and electronic device. Background Technology

[0002] On Qualcomm's intelligent platform, the power-on, power-off, and restart operations of the CPU (Central Processing Unit) chip are typically achieved by the user pressing and holding the power button to lower the POWERKEY level for a certain period of time. Specifically, when the CPU chip is in the power-off state, the user presses and holds the power button to lower the POWERKEY level for 1.6 seconds to power on the CPU chip. Alternatively, when the CPU chip is in the power-on state, the user presses and holds the power button to lower the POWERKEY level for 1.6 seconds to bring up the power-off options interface. After the user selects the power-off or restart option on the power-off options interface, the CPU chip begins the power-off or restart process. In addition, Qualcomm's intelligent platform may be used in non-human-computer interaction scenarios. Related technologies also use the MCU (Microcontroller Unit) to control the duration of lowering the POWERKEY level to achieve the power-on and power-off operations of the CPU chip.

[0003] However, the problem with this technology is that when the Qualcomm Smart Platform is applied to non-human-computer interaction scenarios, the inability to select a shutdown option through human interaction during power-off means that controlling the POWERKEY level to be low via the MCU can only achieve forced shutdown. Specifically, in the Qualcomm Smart Platform, when the POWERKEY level is low for 8.7 seconds, the CPU chip will be forced to power down. Long-term use of forced shutdown may damage the device. On the other hand, if the CPU chip is in a power-off state, controlling the POWERKEY level to be low for 8.7 seconds via the MCU may result in the CPU chip being powered on and then forced to shut down again, or it may be powered on but not forced to shut down. Therefore, using the MCU to control the POWERKEY level to be low for 8.7 seconds to achieve power-on and power-off may lead to chaotic power-on and power-off states of the CPU chip, and this method also makes the circuit more complex and more expensive. Utility Model Content

[0004] This utility model aims to at least partially solve one of the technical problems in the related art. Therefore, the first objective of this utility model is to provide a power-on / off circuit that enables the CPU chip to power on / off without human-computer interaction, avoids CPU chip damage or inconsistent power-on / off states, and simultaneously ensures that the power-on / off states of the CPU chip and the MCU are consistent, thus simplifying circuit design.

[0005] The second objective of this invention is to provide an electronic device.

[0006] To achieve the above objectives, the first aspect of this utility model proposes a power-on / off circuit, comprising a power-on circuit and a power-off circuit. The input terminal of the power-on circuit is connected to the PWR signal output terminal of the MCU chip, and the output terminal of the power-on circuit is connected to the CBL signal input terminal of the PMU (Power Management Unit) chip. The power-on circuit is adapted to ground the CBL signal input terminal of the PMU chip when the PWR signal output terminal of the MCU chip is at a high level, thereby enabling the CPU chip to power on. The input terminal of the power-off circuit is connected to the PWR signal output terminal of the MCU chip, and the output terminal of the power-off circuit is connected to the GPIO signal input terminal of the CPU chip. The power-off circuit is adapted to change the level of the GPIO signal input terminal of the CPU chip from low to high when the PWR signal output terminal of the MCU chip is at a low level, thereby enabling the CPU chip to power off.

[0007] According to the power-on / off circuit of this utility model, the power-on circuit controls the CBL signal input terminal of the PMU chip to be grounded when the level signal of the PWR signal output terminal of the MCU chip is high, thereby realizing the power-on operation of the CPU chip. The power-off circuit controls the level signal of the GPIO signal input terminal of the CPU chip to change from low to high when the level signal of the PWR signal output terminal of the MCU chip is low, thereby realizing the power-off operation of the CPU chip. Thus, the power-on and power-off of the CPU chip does not depend on human-computer interaction, avoids damage to the CPU chip or chaotic power-on / off state, and keeps the power-on / off state of the CPU chip consistent with that of the MCU, simplifying circuit design.

[0008] In addition, the power-on / off circuit according to the present invention may also have the following additional technical features: In some examples of this utility model, the power-on circuit includes: a first switching transistor, the gate of which is connected to the PWR signal output terminal of the MCU chip, the source of which is connected to the CBL signal input terminal of the PMU chip, and the drain of which is grounded, wherein the CBL signal input terminal of the PMU chip is grounded after the first switching transistor is turned on; and a first voltage divider circuit, the input terminal of which is connected to the PWR signal output terminal of the MCU chip, and the output terminal of which is connected to the gate of the first switching transistor.

[0009] In some examples of this utility model, the first voltage divider circuit includes: a first voltage divider resistor, one end of which is connected to the PWR signal output terminal of the MCU chip, and the other end of which is connected to the gate of the first switching transistor; a second voltage divider resistor, one end of which is connected to both the first voltage divider resistor and the gate of the first switching transistor, and the other end of which is grounded; and a first voltage stabilizing capacitor, one end of which is connected between the first voltage divider resistor and the second voltage divider resistor, and the other end of which is connected between the second voltage divider resistor and the ground wire.

[0010] In some examples of this utility model, the power-on circuit further includes: a fifth voltage divider resistor, one end of which is connected to the source of the first switching transistor, and the other end of which is connected to the CBL signal input terminal of the PMU chip.

[0011] In some examples of this utility model, the power-off circuit includes: a second switching transistor, the gate of which is connected to the PWR signal output terminal of the MCU chip, the source of which is connected to the power supply and the GPIO signal input terminal of the CPU chip respectively, and the drain of which is grounded, wherein the GPIO signal input terminal of the CPU chip is grounded after the second switching transistor is turned on; and a second voltage divider circuit, the input terminal of which is connected to the PWR signal output terminal of the MCU chip, and the output terminal of which is connected to the gate of the second switching transistor.

[0012] In some examples of this utility model, the second voltage divider circuit includes: a third voltage divider resistor, one end of which is connected to the PWR signal output terminal of the MCU chip, and the other end of which is connected to the gate of the second switching transistor; a fourth voltage divider resistor, one end of which is connected to the gate of the third voltage divider resistor and the second switching transistor respectively, and the other end of which is grounded; and a second voltage stabilizing capacitor, one end of which is connected between the third voltage divider resistor and the fourth voltage divider resistor, and the other end of which is connected between the fourth voltage divider resistor and the ground wire.

[0013] In some examples of this utility model, the power-off circuit further includes: a sixth voltage divider resistor, one end of which is connected to the power supply, and the other end of which is connected to the GPIO signal input terminal of the CPU chip and the source of the second switching transistor; and a seventh voltage divider resistor, one end of which is connected to the GPIO signal input terminal of the CPU chip, and the other end of which is connected to the source of the sixth voltage divider resistor and the second switching transistor.

[0014] In some examples of this invention, when the level signal at the PWR signal output terminal of the MCU chip is high, both the first and second switching transistors are in the on state.

[0015] In some examples of this invention, when the level signal at the PWR signal output terminal of the MCU chip is low, both the first and second switching transistors are in the off state.

[0016] To achieve the above objectives, a second aspect of this utility model provides an electronic device including the aforementioned power-on / off circuit of this utility model.

[0017] According to the present invention, by adopting the aforementioned power-on / off circuit, the power-on / off of the CPU chip can be made independent of human-computer interaction, and damage to the CPU chip or confusion in the power-on / off state can be avoided. At the same time, the power-on / off state of the CPU chip and the power-on / off state of the MCU are kept consistent, simplifying the circuit design.

[0018] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0019] Figure 1 This is an electrical schematic diagram of a power-on / off circuit according to an embodiment of the present invention; Figure 2 This is a block diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0020] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.

[0021] The following description, with reference to the accompanying drawings, describes the power-on / off circuit and electronic equipment proposed in the embodiments of this utility model.

[0022] Figure 1 This is an electrical schematic diagram of a power-on / off circuit according to an embodiment of the present invention.

[0023] Specifically, in some examples of this utility model, reference is made to... Figure 1As shown, the power-on / off circuit 100 includes a power-on circuit 110 and a power-off circuit 120. The input terminal of the power-on circuit 110 is connected to the PWR signal output terminal MUC_PWR of the MCU chip, and the output terminal of the power-on circuit 110 is connected to the CBL signal input terminal PMU_CBL of the PMU chip. The power-on circuit 110 is adapted to ground the CBL signal input terminal PMU_CBL of the PMU chip when the level signal of the PWR signal output terminal MUC_PWR of the MCU chip is high, thereby realizing the power-on operation of the CPU chip. The input terminal of the power-off circuit 120 is connected to the PWR signal output terminal MUC_PWR of the MCU chip, and the output terminal of the power-off circuit 120 is connected to the GPIO signal input terminal CPU_GPIO of the CPU chip. The power-off circuit 120 is adapted to change the level signal of the GPIO signal input terminal CPU_GPIO of the CPU chip from low to high when the level signal of the PWR signal output terminal MUC_PWR of the MCU chip is low, thereby realizing the power-off operation of the CPU chip.

[0024] It should be understood that the CBL signal is a unique signal on the PMU chip of the Qualcomm intelligent platform. When the CBL signal is grounded and the CPU chip is powered on, the PMU chip can control the CPU chip to automatically power on. Specifically, in this example of the present invention, the power-on circuit 110 controls the PMU chip's CBL signal input terminal PMU_CBL to be grounded when the level signal of the MCU chip's PWR signal output terminal MUC_PWR is high, thereby realizing the power-on operation of the CPU chip.

[0025] In addition, the GPIO signal is a GPIO (General-Purpose Input / Output) on the CPU chip, which can detect changes in the level of the signal. Therefore, by continuously querying the CPU core for the level signal of the GPIO signal through the upper-level software of the CPU core, and when the level signal of the GPIO signal changes from low to high, the CPU chip can be automatically shut down. Specifically, in this example of the present invention, the shutdown circuit 120 controls the level signal of the GPIO signal input terminal CPU_GPIO of the CPU chip to change from low to high when the level signal of the PWR signal output terminal MUC_PWR of the MCU chip is low, thereby realizing the shutdown operation of the CPU chip.

[0026] Therefore, based on the power-on / off circuit 100 in this example, the power-on circuit 110 controls the PMU chip's CBL signal input terminal PMU_CBL to be grounded when the MCU chip's PWR signal output terminal MCU_PWR is at a high level, thus realizing the power-on operation of the CPU chip. Conversely, the power-off circuit 120 controls the CPU chip's GPIO signal input terminal CPU_GPIO to change from low to high when the MCU chip's PWR signal output terminal MCU_PWR is at a low level, thus realizing the power-off operation of the CPU chip. This allows the CPU chip's power-on / off to be independent of human-computer interaction, expanding the application scenarios of the CPU chip. At the same time, it prevents the CPU chip's power-on / off from relying on a single POWERKEY power-on / off logic, avoiding CPU chip damage or chaotic power-on / off states. Furthermore, it ensures that the power-on / off states of the CPU chip and the MCU are consistent, simplifying circuit design and facilitating unified control of the CPU chip and the MCU chip.

[0027] Furthermore, in some examples of this utility model, reference is made to... Figure 1 As shown, the power-on circuit 110 includes: a first switching transistor Q1, the gate of which is connected to the PWR signal output terminal MCU_PWR of the MCU chip, the source of which is connected to the CBL signal input terminal PMU_CBL of the PMU chip, and the drain of which is grounded. The CBL signal input terminal PMU_CBL of the PMU chip is grounded after the first switching transistor Q1 is turned on; and a first voltage divider circuit 111, the input of which is connected to the PWR signal output terminal MCU_PWR of the MCU chip, and the output of which is connected to the gate of the first switching transistor Q1.

[0028] Specifically, in this example of the present invention, when the level signal of the PWR signal output terminal MCU_PWR of the MCU chip is high, the first switch Q1 is turned on, so that the CBL signal input terminal PMU_CBL of the PMU chip is grounded, thereby realizing the power-on operation of the CPU chip. In addition, the first voltage divider circuit 111 ensures that the output voltage of the PWR signal output terminal MCU_PWR of the MCU chip matches the operating voltage of the first switch Q1, so that the first switch Q1 can work normally.

[0029] Furthermore, in some examples of this utility model, reference is made to... Figure 1As shown, the first voltage divider circuit 111 includes: a first voltage divider resistor R1, one end of which is connected to the PWR signal output terminal MCU_PWR of the MCU chip, and the other end of which is connected to the gate of the first switching transistor Q1; a second voltage divider resistor R2, one end of which is connected to both the first voltage divider resistor R1 and the gate of the first switching transistor Q1, and the other end of which is grounded; and a first voltage regulator capacitor C1, one end of which is connected between the first voltage divider resistor R1 and the second voltage divider resistor R2, and the other end of which is connected between the second voltage divider resistor R2 and the ground wire.

[0030] Specifically, in this example of the present invention, the output voltage of the PWR signal output terminal MCU_PWR of the MCU chip is distributed by the first voltage divider resistor R1 and the second voltage divider resistor R2 to avoid overvoltage damage to the first switching transistor Q1, and the output voltage of the PWR signal output terminal MCU_PWR of the MCU chip is stabilized by the first voltage regulator capacitor C1 to ensure that the first switching transistor Q1 works normally.

[0031] Furthermore, in some examples of this utility model, reference is made to... Figure 1 As shown, the power-on circuit 110 also includes: a fifth voltage divider resistor R5, one end of which is connected to the source of the first switching transistor Q1, and the other end of which is connected to the CBL signal input terminal PMU_CBL of the PMU chip.

[0032] Specifically, in this example of the present invention, the output voltage of the PMU_CBL signal input terminal of the PMU chip is distributed by the fifth voltage divider resistor R5 to avoid overvoltage damage to the first switching transistor Q1.

[0033] Furthermore, in some examples of this utility model, reference is made to... Figure 1 As shown, the power-off circuit 120 includes: a second switching transistor Q2, the gate of which is connected to the PWR signal output terminal MCU_PWR of the MCU chip, the source of which is connected to the power supply and the GPIO signal input terminal CPU_GPIO of the CPU chip, and the drain of which is grounded. The GPIO signal input terminal CPU_GPIO of the CPU chip is grounded after the second switching transistor Q2 is turned on; and a second voltage divider circuit 121, the input of which is connected to the PWR signal MCU_PWR output terminal of the MCU chip, and the output of which is connected to the gate of the second switching transistor Q2.

[0034] Specifically, in this example of the present invention, when the level signal of the PWR signal output terminal MCU_PWR of the MCU chip is high, the power-on circuit 110 controls the CBL signal input terminal PMU_CBL of the PMU chip to be grounded, enabling the CPU chip to perform a power-on operation. At this time, the second switch Q2 is turned on, grounding the GPIO signal input terminal CPU_GPIO of the CPU chip, that is, the level signal of the GPIO signal input terminal CPU_GPIO of the CPU chip is low. Then, when the level signal of the PWR signal output terminal MCU_PWR of the MCU chip is low, the second switch Q2 is turned off, disconnecting the grounding of the GPIO signal input terminal CPU_GPIO of the CPU chip. At this time, the GPIO signal input terminal CPU_GPIO of the CPU chip is only connected to the power supply, and the level signal of the GPIO signal input terminal CPU_GPIO of the CPU chip changes from low to high, realizing the power-off operation of the CPU chip.

[0035] In addition, the second voltage divider circuit 121 ensures that the output voltage of the PWR signal output terminal MCU_PWR of the MCU chip matches the operating voltage of the second switching transistor Q2, so that the second switching transistor Q2 can work normally.

[0036] It should be noted that, in the above examples of this utility model, the level change of the GPIO signal input terminal CPU_GPIO of the CPU chip will not affect the PMU chip's control of the CPU chip to perform the power-on operation, and whether or not the CBL signal input terminal PMU_CBL of the PMU chip is grounded will not affect the level change of the GPIO signal input terminal CPU_GPIO of the CPU chip to control the CPU chip to perform the power-off operation.

[0037] Furthermore, in some examples of this utility model, reference is made to... Figure 1 As shown, the second voltage divider circuit 121 includes: a third voltage divider resistor R3, one end of which is connected to the PWR signal output terminal MCU_PWR of the MCU chip, and the other end of which is connected to the gate of the second switching transistor Q2; a fourth voltage divider resistor R4, one end of which is connected to the gate of the third voltage divider resistor R3 and the gate of the second switching transistor Q2, and the other end of which is grounded; and a second voltage regulator capacitor C2, one end of which is connected between the third voltage divider resistor R3 and the fourth voltage divider resistor R4, and the other end of which is connected between the fourth voltage divider resistor R4 and the ground wire.

[0038] Specifically, in this example of the present invention, the output voltage of the PWR signal output terminal MCU_PWR of the MCU chip is distributed by the third voltage divider resistor R3 and the fourth voltage divider resistor R4 to avoid overvoltage damage to the second switch Q2, and the output voltage of the PWR signal output terminal MCU_PWR of the MCU chip is stabilized by the second voltage regulator capacitor C2 to ensure that the second switch Q2 works normally.

[0039] Furthermore, in some examples of this utility model, reference is made to... Figure 1 As shown, the power-off circuit 120 also includes: a sixth voltage divider resistor R6, one end of which is connected to the power supply, and the other end of which is connected to the GPIO signal input terminal CPU_GPIO of the CPU chip and the source of the second switching transistor Q2; and a seventh voltage divider resistor R7, one end of which is connected to the GPIO signal input terminal CPU_GPIO of the CPU chip, and the other end of which is connected to the sixth voltage divider resistor R6 and the source of the second switching transistor Q2.

[0040] Specifically, in this example of the present invention, the power supply voltage and the CPU_GPIO signal input terminal of the CPU chip are distributed by the sixth voltage divider resistor R6 and the seventh voltage divider resistor R7 to avoid overvoltage damage to the second switching transistor Q2 or the CPU chip.

[0041] Furthermore, in some examples of this utility model, reference is made to... Figure 1 As shown, when the PWR signal output terminal MCU_PWR of the MCU chip is at a high level, both the first switch Q1 and the second switch Q2 are in the on state.

[0042] Specifically, in this example of the present invention, when the level signal of the PWR signal output terminal MCU_PWR of the MCU chip is high, both the first switch Q1 and the second switch Q2 are in the conducting state, so as to ground the CBL signal input terminal PMU_CBL of the PMU chip, thereby realizing the power-on operation of the CPU chip. At the same time, the GPIO signal input terminal CPU_GPIO of the CPU chip is grounded to prepare for the power-off of the CPU chip.

[0043] Furthermore, in some examples of this utility model, reference is made to... Figure 1 As shown, when the PWR signal output terminal MCU_PWR of the MCU chip is at a low level, both the first switch Q1 and the second switch Q2 are in the off state.

[0044] Specifically, in this example of the present invention, when the level signal of the PWR signal output terminal MCU_PWR of the MCU chip is low, both the first switch Q1 and the second switch Q2 are in the off state, so that the GPIO signal input terminal CPU_GPIO of the CPU chip is disconnected from ground and connected only to the power supply, thereby realizing the shutdown operation of the CPU chip. At the same time, the CBL signal input terminal PMU_CBL of the PMU chip is disconnected from ground, preparing for the power-on of the CPU chip.

[0045] In summary, the power-on / off circuit of this utility model controls the CBL signal input terminal of the PMU chip to be grounded when the level signal of the PWR signal output terminal of the MCU chip is high, thereby realizing the power-on operation of the CPU chip. Conversely, the power-off circuit controls the level signal of the GPIO signal input terminal of the CPU chip to change from low to high when the level signal of the PWR signal output terminal of the MCU chip is low, thereby realizing the power-off operation of the CPU chip. Thus, the power-on / off of the CPU chip does not depend on human-computer interaction, avoids damage to the CPU chip or chaotic power-on / off states, and ensures that the power-on / off states of the CPU chip and the MCU are consistent, simplifying circuit design.

[0046] Figure 2 This is a block diagram of an electronic device according to an embodiment of the present invention.

[0047] Specifically, in some examples of this utility model, reference is made to... Figure 2 As shown, the electronic device 1000 includes the power-on / off circuit 100 of the aforementioned example of this utility model.

[0048] It should be understood that the specific implementation of the electronic device 1000 of this utility model can be referred to the specific implementation of the power-on / off circuit 100 in the above-mentioned example of this utility model. In order to reduce redundancy, it will not be described again here.

[0049] In summary, the electronic device according to this utility model, by adopting the aforementioned power-on / off circuit, enables the power-on / off of the CPU chip to be independent of human-computer interaction, avoids damage to the CPU chip or confusion in the power-on / off state, and at the same time ensures that the power-on / off state of the CPU chip is consistent with that of the MCU, thus simplifying circuit design.

[0050] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0051] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0053] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0054] In this utility model, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0055] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A power on / off circuit, characterized in that, The power-on / off circuit includes a power-on circuit and a power-off circuit. The input terminal of the power-on circuit is connected to the PWR signal output terminal of the MCU chip, and the output terminal of the power-on circuit is connected to the CBL signal input terminal of the PMU chip. The power-on circuit is adapted to ground the CBL signal input terminal of the PMU chip when the PWR signal output terminal of the MCU chip is at a high level, thereby powering on the CPU chip. The input terminal of the power-off circuit is connected to the PWR signal output terminal of the MCU chip, and the output terminal of the power-off circuit is connected to the GPIO signal input terminal of the CPU chip. The power-off circuit is adapted to change the level of the GPIO signal input terminal of the CPU chip from low to high when the PWR signal output terminal of the MCU chip is at a low level, thereby powering off the CPU chip.

2. The power on / off circuit according to claim 1, characterized in that, The power-on circuit includes: The first switching transistor has its gate connected to the PWR signal output terminal of the MCU chip, its source connected to the CBL signal input terminal of the PMU chip, and its drain grounded. The CBL signal input terminal of the PMU chip is grounded after the first switching transistor is turned on. The first voltage divider circuit has its input terminal connected to the PWR signal output terminal of the MCU chip, and its output terminal connected to the gate of the first switching transistor.

3. The power-on / off circuit according to claim 2, characterized in that, The first voltage divider circuit includes: The first voltage divider resistor has one end connected to the PWR signal output terminal of the MCU chip and the other end connected to the gate of the first switching transistor. The second voltage divider resistor has one end connected to the gate of the first voltage divider resistor and the gate of the first switching transistor, and the other end grounded. The first voltage regulator capacitor has one end connected between the first voltage divider resistor and the second voltage divider resistor, and the other end connected between the second voltage divider resistor and the ground wire.

4. The power on / off circuit according to claim 3, characterized in that, The power-on circuit also includes: The fifth voltage divider resistor has one end connected to the source of the first switching transistor and the other end connected to the CBL signal input terminal of the PMU chip.

5. The power-on / off circuit according to claim 2, characterized in that, The shutdown circuit includes: The second switching transistor has its gate connected to the PWR signal output terminal of the MCU chip, its source connected to the power supply and the GPIO signal input terminal of the CPU chip, and its drain grounded. The GPIO signal input terminal of the CPU chip is grounded after the second switching transistor is turned on. The second voltage divider circuit has its input terminal connected to the PWR signal output terminal of the MCU chip, and its output terminal connected to the gate of the second switching transistor.

6. The power-on / off circuit according to claim 5, characterized in that, The second voltage divider circuit includes: The third voltage divider resistor has one end connected to the PWR signal output terminal of the MCU chip, and the other end connected to the gate of the second switching transistor. The fourth voltage divider resistor has one end connected to the gate of the third voltage divider resistor and the second switching transistor, and the other end grounded. The second voltage regulator capacitor has one end connected between the third and fourth voltage divider resistors, and the other end connected between the fourth voltage divider resistor and ground.

7. The power on / off circuit according to claim 6, characterized in that, The shutdown circuit also includes: The sixth voltage divider resistor has one end connected to the power supply and the other end connected to the GPIO signal input terminal of the CPU chip and the source of the second switching transistor, respectively. The seventh voltage divider resistor has one end connected to the GPIO signal input terminal of the CPU chip, and the other end connected to the source of the sixth voltage divider resistor and the second switching transistor, respectively.

8. The power on / off circuit according to claim 5, characterized in that, When the PWR signal output of the MCU chip is high, both the first and second switching transistors are in the ON state.

9. The power-on / off circuit according to claim 5, characterized in that, When the PWR signal output of the MCU chip is low, both the first and second switching transistors are in the off state.

10. An electronic device, characterized in that, The electronic device includes a power-on / off circuit as described in any one of claims 1-9.

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