A high and low voltage power-on timing control circuit

Abstract

This invention provides a high / low voltage power-on timing control circuit, including a low-voltage detection circuit and a high-voltage control circuit. The low-voltage detection circuit is connected to the high-voltage control circuit, and a high-voltage input signal is connected to the high-voltage control circuit. When the low-voltage detection circuit detects a set low voltage signal, it generates a control level to trigger the high-voltage control circuit to control the high-voltage output. The low-voltage detection circuit only generates a control level input to the high-voltage control circuit when it simultaneously detects both a low-voltage high-level signal and a low-voltage low-level signal. In this invention, the low-voltage detection circuit detects the positive voltage VCC and the negative voltage VEE; only when both voltage signals are present is the high-voltage output controlled by the high-voltage control circuit.

Description

Technical Field

[0001] This utility model relates to the field of high voltage switching circuits, and in particular to a high and low voltage power-on timing control circuit, which realizes the low voltage power-on drive switch closing to realize high voltage power-on. Background Technology

[0002] High-voltage switches employ electronic switches, which are driven by a low-voltage level. When the level signal is a valid control level, the electronic switch closes to output high voltage. In practice, the control level of the electronic switch is generated by a level generation module. During operation, the level generation module only needs to detect whether there is a voltage signal. When a voltage signal is present, it generates a control level to close the electronic switch. However, this method, which requires only a low-voltage signal to control the electronic switch, is prone to malfunctions, potentially causing the switch to close prematurely by outputting a single control level. Utility Model Content

[0003] This invention addresses the shortcoming of current high-voltage electronic switches, where the control level generated by a single low-voltage signal to close the switch is prone to malfunction. It provides a high / low voltage power-on sequence control circuit that only generates a control level to close the electronic switch when both a low-voltage high-level signal and a low-voltage low-level signal are present simultaneously. In other words, during operation, a control level is only generated to drive the electronic switch to close when both low-voltage high-level and low-voltage low-level signals are detected, thus avoiding the need for a single control level to close the electronic switch due to malfunction.

[0004] The technical solution for achieving the technical objective of this utility model is: a high and low voltage power-on timing control circuit, including a low voltage detection circuit and a high voltage control circuit. The low voltage detection circuit is connected to the high voltage control circuit, and the high voltage input signal is connected to the high voltage control circuit. When the low voltage detection circuit detects a set low voltage signal, it generates a control level to trigger the high voltage control circuit to control the high voltage output. The low voltage detection circuit only generates a control level input to the high voltage control circuit when it simultaneously detects a low voltage high level signal and a low voltage low level signal.

[0005] Furthermore, in the aforementioned high and low voltage power-on timing control circuit: the low-voltage high-level signal is the low-voltage positive level signal VCC, and the low-voltage low-level signal is the low-voltage negative level signal VEE.

[0006] Furthermore, in the aforementioned high and low voltage power-on timing control circuit: the control circuit includes an electronic switch, the input terminal of which is connected to high voltage, the output terminal of which is connected to the load, and the control terminal of which is connected to the low voltage detection circuit.

[0007] Furthermore, in the aforementioned high and low voltage power-on timing control circuit: the electronic switch is an N-channel MOS transistor Q2, the high voltage and the load are respectively connected to the source and drain terminals of the N-channel MOS transistor Q2, and the gate is connected to the aforementioned low voltage detection circuit.

[0008] Furthermore, in the aforementioned high and low voltage power-on timing control circuit: a Zener diode is provided between the source and drain of the N-channel MOSFET Q2, and two Zener diodes with their anodes connected are provided between the gate and drain of the N-channel MOSFET Q2.

[0009] Furthermore, in the above-mentioned high and low voltage power-on timing control circuit: the control circuit includes a driving circuit for the N-channel MOSFET Q2, and the driving circuit for the N-channel MOSFET Q2 includes transistors Q3 and Q5, bias resistor R34, current-limiting resistor R37, bias resistor R38, current-limiting resistor R42, and bias resistor R44.

[0010] The output of the low-voltage detection circuit is grounded through a bias resistor R44 and connected to the base of transistor Q3 through a current-limiting resistor R42. The collector of transistor Q3 is connected to a high voltage through a bias resistor R34 and to the base of transistor Q5 through a current-limiting resistor R37. The emitter of transistor Q3 is grounded. The collector of transistor Q5 is connected to the N-channel MOSFET Q2 and connected to a high voltage through a bias resistor R38. The emitter is grounded.

[0011] Furthermore, in the aforementioned high and low voltage power-on timing control circuit: the low voltage detection circuit includes sampling resistor R41, sampling resistor R43, and inverter U22. The positive power supply VCC is connected to the negative power supply VEE through sampling resistors R41 and R43 with the same resistance value. The positive power supply VCC is also connected to the VCC pin of inverter U22. The common terminal of sampling resistors R41 and R43 is connected to the A pin of inverter U22. The GND pin of inverter U22 is grounded. The output terminal of inverter U22 is the Y pin.

[0012] In this invention, a low-voltage detection circuit is used to detect the positive voltage VCC and the negative voltage VEE. Only when both voltage signals are present will the high-voltage control circuit control the high-voltage output.

[0013] The present invention will be described in more detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0014] Appendix Figure 1 This is a circuit diagram for the high and low voltage power-on timing control of this utility model;

[0015] Appendix Figure 2 This is a detailed circuit diagram of Embodiment 1 of the present invention. Detailed Implementation

[0016] This embodiment is a high and low voltage power-on timing control circuit diagram, such as... Figure 1 and Figure 2 As shown: This embodiment mainly solves the control circuit for the power-on sequence of high voltage and low voltage (including a positive low voltage and a negative low voltage). When either of the low voltages (including a positive voltage and a negative voltage) is not working, there is no output from the high voltage. Only when both the positive and negative low voltages are working simultaneously will the high voltage have an output. This high-low voltage power-on sequence control circuit avoids damage to components due to overcurrent caused by the high voltage arriving before the low voltage is working, resulting in inconsistent power-on times for the three voltages during power-on.

[0017] The circuit in this embodiment mainly consists of two parts: a low-voltage detection circuit and a high-voltage control circuit, as follows: Figure 1 As shown. The low-voltage detection circuit determines whether both VCC (positive) and VEE (negative) voltages are supplied to the low-voltage detection circuit. When both voltages are operating normally, the low-voltage detection circuit outputs a high-level control level (high-level voltage equal to VCC), which then drives the high-voltage control circuit to output high voltage. When one of the voltages is not operating normally, the low-voltage detection circuit outputs a low-level control level. When the control level is low, the high-voltage control circuit is cut off, and there is no high-voltage output.

[0018] like Figure 2 The diagram shown is the circuit schematic of this embodiment. This embodiment can be implemented through the following technical measures: The control circuit mainly consists of sampling resistors R41 and R43, inverter U22, transistors Q3 and Q5, N-channel MOSFET Q2, and bias resistors R34, R37, R38, R42, and R44. Here, bias resistors R34 and R37 are both 10MΩ, while bias resistor R44 is 10KΩ, and current-limiting resistors R42 and R37 are 1KΩ resistors. (See below.) Figure 2 As shown. Sampling resistors R41 and R43 are both 5.1K resistors.

[0019] The circuit operation process of this embodiment is analyzed below:

[0020] When there is no voltage input to the VEE and VCC voltage groups, the circuit is inoperable. At this time, with only high voltage input, the inverter U22 in the low voltage detection circuit is not working, and the voltage level at point B is 0V. The high voltage control circuit transistor Q3 is cut off. The high voltage, through the bias resistors R34 and R37, provides the base voltage to transistor Q5, causing Q5 to conduct. The high voltage then conducts to ground through the bias resistor R38 and transistor Q5. The gate voltage of MOSFET Q2 is low, so MOSFET Q2 is cut off, and there is no high voltage output (at point D).

[0021] For example, one voltage group of VCC is not working, while another group of VEE is working. At this time, when a high voltage is input, the inverter in the low voltage detection circuit U22 is not working, and the voltage level at point B is 0V. The high voltage control circuit transistor Q3 is cut off. The high voltage is divided by R34 and R37 to provide the base voltage for transistor Q5, causing Q5 to conduct. The high voltage is then conducted to ground through R38 and transistor Q5. The gate voltage of the N-channel MOSFET Q2 is low, so Q2 is cut off, and there is no high voltage output (at point D).

[0022] For example, one voltage group of VEE is not working, only one voltage group of VCC is working. At this time, when high voltage is input, the level at point A of the sampling circuit is 3.3V, the low voltage detection circuit U22 inverter U22 is working, and the output level at point B is 0V. The high voltage control circuit transistor Q3 is cut off. The high voltage is divided by bias resistors R34 and R37 to provide the base voltage for transistor Q5, causing transistor Q5 to conduct. The high voltage is then conducted to ground through bias resistor R38 and transistor Q5. The gate voltage of N-channel MOSFET Q2 is low, N-channel MOSFET Q2 is cut off, and there is no high voltage output (at point D).

[0023] For example, when both VCC and VEE low voltage groups have voltage inputs, when the high voltage is input, the sampling circuit at point A is 0V, the low voltage detection circuit inverter U22 works and outputs a level of 3.3V at point B, the high voltage control circuit transistor Q3 is turned on, and the voltage at point B is 0V because Q3 is conducting to ground. At this time, the voltage at point B is 0V, the transistor Q5 is turned off, and the high voltage provides the gate bias voltage for the N-channel MOSFET Q2 through the bias resistor R38. The N-channel MOSFET Q2 is turned on, and the high voltage is output (at point D).

[0024] In this embodiment, U22 is a high-speed and high-output drive CMOS inverter chip. Its connection method is that pin 2 is the detection level input port and pin 4 is the inverting output drive port.

[0025] It can also be a general-purpose inverter integrated circuit, such as the HEF4069UBT: an NXP product, which is a general-purpose six-channel inverter. It operates with a VDD recommended supply voltage range of 3V to 15V, based on VSS (usually ground). Each inverter has a single stage; the idle input must be connected to VDD, VSS, or another input. Its maximum quiescent current is 1μA, and both high and low output currents are 3.4mA. Logic low is 1V to 2.5V, and logic high is 4V to 12.5V. The propagation delay is 30ns at a 15V supply and a maximum load capacitance of 50pF. The operating temperature range is -40℃ to 125℃, and it is packaged in a 14-SOIC (0.145", 3.90mm wide) package.

[0026] CD4049: A CMOS hex inverter / converter. It performs level conversion and operates over a wide voltage range, typically 3V-15V. It is commonly used in circuits requiring signal inversion and conversion between different logic levels, such as converting lower logic level signals to higher logic level outputs to adapt to various subsequent circuit modules.

[0027] Inverter U22 can also be an inverter integrated circuit with a Schmitt trigger and a driver-type inverter integrated circuit.

[0028] Among them, the Schmitt trigger has hysteresis characteristics and can be used for pulse shaping, eliminating noise components in waveforms, etc.

[0029] The main models are:

[0030] 74HC14: A six-channel inverter logic integrated circuit with Schmitt triggers manufactured by NXP Semiconductors. It has a wide operating voltage range of 2V to 6V, is manufactured using high-speed CMOS technology, and features high switching speed and low power consumption. The internal Schmitt triggers shape the input signal, improving the circuit's noise immunity. It is widely used in logic operations and digital signal processing in computers, communication equipment, industrial control, and consumer electronics.

[0031] SN74LVC14AQ: Manufactured by Texas Instruments (TI), this model integrates six independent Schmitt trigger inverters. Utilizing low-voltage differential signaling technology, it is suitable for systems from 1.65V to 5.5V, featuring high speed and low power consumption. It also incorporates ESD (electrostatic discharge) protection and overvoltage suppression protection, and is commonly used in logic control, signal processing, and digital communications.

[0032] The TC74VHC14FT contains six inverters with identical functions and parameters. It is a CMOS Schmitt inverter and can be used as a line receiver to receive slow input signals while maintaining the low power consumption characteristics of CMOS.

[0033] Driver-type inverter integrated circuit:

[0034] The ULN2003 integrates a Darlington transistor and a diode to suppress back EMF, allowing it to drive inductive loads such as relays and DC motors. It has 16 pins: pins 1-7 are input, pins 10-16 are output, pin 8 is grounded, and Com is the common power supply terminal. When the input is high, the output is low and it can sink current. A single output can provide 500 mA, and the operating voltage is typically up to 50V. It is a seven-stage Darlington output array with open-collector outputs.

[0035] In practice, any of the above chips can be selected, and peripheral circuits can be added according to the requirements of the selected chip to complete the functions shown above. Only when VCC and VEE are both valid will the Y terminal output a valid signal, which controls the N-channel MOSFET Q2 through transistors Q3 and Q5.

Claims

1. A high / low voltage power-on timing control circuit, comprising a low-voltage detection circuit and a high-voltage control circuit, wherein the low-voltage detection circuit is connected to the high-voltage control circuit, and a high-voltage input signal is connected to the high-voltage control circuit; when the low-voltage detection circuit detects a set low voltage signal, it generates a control level to trigger the high-voltage control circuit to control the high-voltage output; characterized in that: The low-voltage detection circuit only generates a control level input to the high-voltage control circuit when it simultaneously detects both a low-voltage high-level signal and a low-voltage low-level signal.

2. The high and low voltage power-on timing control circuit according to claim 1, characterized in that: The low-voltage high-level signal is the low-voltage positive level signal VCC, and the low-voltage low-level signal is the low-voltage negative level signal VEE.

3. The high and low voltage power-on timing control circuit according to claim 2, characterized in that: The control circuit includes an electronic switch, the input terminal of which is connected to high voltage, the output terminal of which is connected to the load, and the control terminal is connected to the low voltage detection circuit.

4. The high and low voltage power-on timing control circuit according to claim 3, characterized in that: The electronic switch is an N-channel MOSFET Q2. The high voltage and the load are connected to the source and drain terminals of the N-channel MOSFET Q2, respectively, and the gate is connected to the low-voltage detection circuit.

5. The high and low voltage power-on timing control circuit according to claim 4, characterized in that: A Zener diode is placed between the source and drain of the N-channel MOSFET Q2, and two Zener diodes with connected anodes are placed between the gate and drain of the N-channel MOSFET Q2.

6. The high and low voltage power-on timing control circuit according to claim 5, characterized in that: The control circuit includes a driving circuit for an N-channel MOSFET Q2, which includes transistors Q3 and Q5, a bias resistor R34, a current-limiting resistor R37, a bias resistor R38, a current-limiting resistor R42, and a bias resistor R44. The output of the low-voltage detection circuit is grounded through a bias resistor R44 and connected to the base of transistor Q3 through a current-limiting resistor R42. The collector of transistor Q3 is connected to a high voltage through a bias resistor R34 and to the base of transistor Q5 through a current-limiting resistor R37. The emitter of transistor Q3 is grounded. The collector of transistor Q5 is connected to the N-channel MOSFET Q2 and connected to a high voltage through a bias resistor R38. The emitter is grounded.

7. The high and low voltage power-on timing control circuit according to any one of claims 1 to 6, characterized in that: The low-voltage detection circuit includes sampling resistors R41 and R43 and inverter U22. The positive power supply VCC is connected to the negative power supply VEE through sampling resistors R41 and R43 with the same resistance. The positive power supply VCC is also connected to the VCC pin of inverter U22. The common terminal of sampling resistors R41 and R43 is connected to the A pin of inverter U22. The GND pin of inverter U22 is grounded. The output terminal of inverter U22 is the Y pin.

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