Semiconductor devices and semiconductor chips

Abstract

This disclosure provides a semiconductor device and a semiconductor die. The semiconductor device includes a first die having transmission circuitry and a first phase-locked loop (PLL) circuitry for generating a first global clock signal. The semiconductor device includes a second die having receiver circuitry, a phase alignment element, and a second PLL circuitry. The phase alignment element is used to generate a reference clock signal using the first global clock signal and feedback from the second PLL circuitry. The second PLL circuitry is used to generate a second global clock signal based on the reference clock signal. The phases of the first global clock signal and the second global clock signal are aligned with each other to facilitate data transfer from the transmission circuitry to the receiver circuitry.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and semiconductor chips. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to a series of improvements in the integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, these improvements in integration density stem primarily from the continuous reduction in the size of the smallest feature (e.g., shrinking semiconductor process nodes towards nodes smaller than 20nm), allowing more components to be integrated into a given area. With the increasing demand for miniaturization, higher speeds, wider bandwidths, and lower power consumption and latency, the need for smaller and more advanced semiconductor die packaging technologies is also growing. Utility Model Content

[0003] This disclosure provides a semiconductor device including a first die and a second die. The first die has a transmitter circuit and a first phase-locked loop (PLL) circuit for generating a first global clock signal. The second die has a receiver circuit, a phase alignment element, and a second PLL circuit. The phase alignment element generates a reference clock signal using the first global clock signal and feedback from the second PLL circuit. The second PLL circuit generates a second global clock signal based on the reference clock signal. The phases of the first and second global clock signals are aligned to facilitate data transfer from the transmitter circuit to the receiver circuit.

[0004] This disclosure provides a semiconductor die including a phase-locked loop (PLL) circuit, a multiplexer, and a receiver circuit. The PLL circuit generates a first global clock signal. The multiplexer selects between the first global clock signal and a second global clock signal, the second global clock signal being electrically coupled to a second die relay of the semiconductor die. The receiver circuit receives the output from the multiplexer and receives data transmitted from the second die.

[0005] This disclosure provides a semiconductor device including a first die and a second die. The first die includes a first transmission circuit, a first delay circuit, and a second delay circuit. The second delay circuit is adjusted according to a set mismatch or maintain mismatch to generate a forwarding clock signal for the first die. The second die includes a second transmission circuit. The first die and the second die have different clock domains. The first delay circuit is adjusted to match a first delay corresponding to the first transmission circuit of the first die with a second delay corresponding to the second transmission circuit of the second die. Attached Figure Description

[0006] The embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation.

[0007] Figure 1 A block diagram of an example system for implementing high-bandwidth and low-latency chip-to-chip circuit communication according to some embodiments is shown.

[0008] Figure 2 A block diagram of a system comprising multiple dies implementing the die-to-die circuit communication technology described herein is illustrated according to some embodiments.

[0009] Figure 3 Block diagrams of example systems implementing high-bandwidth and low-latency chip-to-chip communication according to some embodiments are illustrated; and

[0010] Figure 4 This is an example flowchart of a method for configuring and implementing circuitry to perform the die-to-die circuit communication technology described herein, according to some embodiments.

[0011] [Symbol Explanation]

[0012] 100: System

[0013] 102A: First semiconductor die

[0014] 102B: Second semiconductor die

[0015] 104A: First Transmitter Circuit

[0016] 104B: Second Transmitter Circuit

[0017] 106A: First Receiver Circuit

[0018] 106B: Second Receiver Circuit

[0019] 108A: First Receiver Switch

[0020] 108B: Receiver flip-flop

[0021] 110A: First-chip to chip receiver interface circuit system

[0022] 110B: Second chip-to-chip receiver interface circuit system

[0023] 112A: First-die-to-die transfer interface circuit system

[0024] 112B: Second die-to-die transfer interface circuit system

[0025] 114A: First Transmission Switch

[0026] 114B: Second Transmission Switch

[0027] 116A: First transmission line

[0028] 116B: Second transmission line

[0029] 118A: First Receiver Data Register

[0030] 118B: Second Receiver Data Register

[0031] 120A: First Traffic Generator

[0032] 120B: Second Service Generator

[0033] 122A: First receiver pipeline circuit

[0034] 122B: Second receiver pipeline circuit

[0035] 124A: First PLL

[0036] 124B: Second PLL

[0037] 126: Phase alignment element

[0038] 128A: First-die to-die clock interface circuit system

[0039] 128B: Second die-to-die clock interface circuit system

[0040] 130A: First-die to-die clock receiver interface circuit system

[0041] 130B: Second-die to-die clock receiver interface circuit system

[0042] 132A: First-die to-die clock transmission interface circuit system

[0043] 132B: Second-die-to-die clock transmission interface circuit system

[0044] 134A: First Global DCDL

[0045] 134B: Second Global DCDL

[0046] 136A: First Region DCDL

[0047] 136B: Second Region DCDL

[0048] 148A: First global clock signal

[0049] 148B: Second global clock signal

[0050] 200: System

[0051] 202: Main grains

[0052] 204A~204C: Auxiliary grains

[0053] 205: Main PLL

[0054] 206A~206C: Auxiliary PLL

[0055] 208A~208C: Phase alignment element

[0056] 300: System

[0057] 302A: First grain

[0058] 302B: Second grain

[0059] 304A: First Transmitter Circuit

[0060] 304B: Second Transmitter Circuit

[0061] 306A: First Receiver Circuit

[0062] 306B: Second Receiver Circuit

[0063] 320A: First Service Generator

[0064] 320B: Second Service Generator

[0065] 322A: First Receiver Pipeline Circuit

[0066] 322B: Second Receiver Pipeline Circuit

[0067] 324A: First PLL

[0068] 324B: Second PLL

[0069] 326: Phase alignment element

[0070] 328A: First-die to-die clock interface circuit system

[0071] 328B: Second die-to-die clock interface circuit system

[0072] 330A: First-die to-die clock receiver interface circuit system

[0073] 330B: Second-die to-die clock receiver interface circuit system

[0074] 332A: First-die to-die clock transmission interface circuit system

[0075] 332B: Second-die-to-die clock transmission interface circuit system

[0076] 334A: First Global DCDL

[0077] 334B: Second Global DCDL

[0078] 336A: First Region DCDL

[0079] 336B: Second Region DCDL

[0080] 338A, 338B: OCC circuit

[0081] 340A, 340B: First Multiplexer

[0082] 342A, 342B: Second Multiplexer

[0083] 346A, 346B: Third Multiplexer

[0084] 348A: First global clock signal

[0085] 348B: Second global clock signal

[0086] 350A: First region clock signal

[0087] 350B: Second Region Clock Signal

[0088] 400: Method

[0089] 402, 404, 406: Operations Detailed Implementation

[0090] The following disclosure provides numerous different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the embodiments of this disclosure may repeat element symbols and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0091] Furthermore, for ease of description, this document uses spatially relative terms (such as "below," "below," "lower part," "above," "upper part," and similar) to describe the relationship between one element or feature illustrated in the figures and another element (or features) or feature (or features). In addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations) and therefore the spatially relative descriptive terms used herein can be interpreted similarly.

[0092] With the increasing demand for smaller and denser semiconductor devices, three-dimensional semiconductor devices (sometimes called 3D integrated circuits, 3D ICs, or 3D-ICs), typically constructed from multiple stacked semiconductor dies, have become an effective solution for reducing the physical area of ​​semiconductor devices. However, using multiple semiconductor dies presents several challenges. One of these challenges concerns the distribution of clock signals among the multiple dies, as each die in a multi-die system can operate in its own clock domain, resulting in asynchronous clock relationships between the dies and thus incurring significant delay costs when exchanging data.

[0093] Various techniques are commonly used to achieve synchronization across multiple chips, including phase-locked loops (PLLs), delay-locked loops (DLLs), and clock domain crossing (CDC) circuits. However, existing clock signal synchronization methods suffer from drawbacks, including their inability to effectively mitigate delays and low bit rates caused by physical separation between chips and mismatches between clock signals from different clock domains. Therefore, such circuits must be designed with additional buffer circuitry to compensate for performance limitations, resulting in increased power consumption, increased latency, and reduced data yield.

[0094] The technique described in this paper addresses these limitations by combining system synchronization with source synchronization clock operation using a synchronous PLL circuit, which operates using the global clock signal of the master die as a reference clock signal. Additional delay circuitry is tuned to address die-specific clock setting or hold mismatches between different clock domains, thereby optimizing bit rate and delay without the need for additional buffer circuitry. The technique eliminates the need for data synchronization circuitry, such as the skew-resistant first-in-first-out (FIFO) circuitry required by conventional methods for synchronizing data received from other dies, while mitigating the delays that occur when forwarding global clock signals across multiple dies.

[0095] Figure 1A block diagram of an example system 100 implementing high-bandwidth and low-latency die-to-die circuit communication according to some embodiments is illustrated. System 100 or its components may include one or more logic gates and sub-circuits, each sub-circuit being constructed from one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to produce a single output signal. Various embodiments of the circuitry and logic gates implementing system 100 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistor can be any suitable type of transistor, including but not limited to metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, P-channel metal-oxide semiconductor (PMOS) transistors, N-channel metal-oxide semiconductor (NMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, or the like.

[0096] As shown in the figure, system 100 includes a first semiconductor die 102A and a second semiconductor die 102B (sometimes referred to as "first die 102A" and "second die 102B", or generally referred to as "one or more semiconductor dies 102" or "one or more dies 102"). In the example configuration of system 100 shown, the first die 102A is the master die, which uses a first PLL 124A to generate a first global clock signal 148A. Although for visual clarity, the first PLL 124A is... Figure 1 The first PLL 124A is shown outside the boundary of the first die 102A, but it should be understood that the first PLL 124A may be included in the circuitry on the first die 102A, or otherwise defined as the circuitry on the first die 102A.

[0097] The first PLL 124A can operate using a feedback mechanism to generate an output clock signal (illustrated here as a first global clock (CLK) signal 148A) and synchronize it with a reference clock signal. The reference clock signal can be any type of reference clock signal, such as a square wave clock signal provided via reference clock generation circuitry. The reference clock can be generated via circuitry included in the first die 102A or received from an external clock source in communication with the first die 102A. In some embodiments, the first PLL 124A can be initialized in response to a reset signal that can control or otherwise enable various circuitry within the first die 102A.

[0098] The first PLL 124A may include a voltage-controlled oscillator (VCO), a phase detector, and a charge pump or divider circuitry. To generate a first global clock signal 148A, the VCO of the first PLL 124A generates a free clock signal, which is then compared by the phase detector to a reference clock signal. The phase difference between the two signals is detected and used to adjust the frequency of the VCO via the charge pump or divider circuitry. This process continues until the first global clock signal 148A is synchronized with the reference clock signal, at which point the PLL is locked, a condition indicated by a signal generated by the PLL. In some implementations, the first PLL 124A may operate within a frequency range (e.g., configured via an input signal or a reference clock signal), and in some embodiments, the first PLL 124A may generate a first global clock signal 148A with a specific or predetermined frequency.

[0099] As shown in the figure, the first PLL 124A of the first die 102A can provide the first global clock signal 148A to the first die-to-die clock interface circuit system 128A and other circuit systems in the first die 102A, such as the first digitally controlled delay line (DCDL) 134A (sometimes referred to herein as "first DCDL circuit 134A" or "global DCDL 134A"). As shown in the figure, the first die-to-die clock interface circuit system 128A of the first die 102A can be electrically coupled to the corresponding second die-to-die clock interface circuit system 128B of the second die 102B. The first die-to-die clock interface circuit system 128A can be used to transmit the first global clock signal 148A to components in the second die 102B. In the master-slave configuration of this embodiment, the first global clock signal 148A generated at the first die 102A operates as the master clock signal, the first die 102A operates as the "master die", and the second die 102B operates as the "slave die".

[0100] The first die-to-die clock interface circuit system 128A and the second die-to-die clock interface circuit system 128B may include any type of circuit system or electronic component to transfer the first global clock signal 148A from the first die 102A to the second die 102B. For example, the first die 102A and the second die 102B may be two semiconductor wafers or dies bonded together by suitable bonding techniques (such as hybrid bonding, microbumping, direct bonding, chemically initiated bonding, plasma initiated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermosetting bonding, reactive bonding, and / or the like). The first die-to-die clock interface circuit system 128A and the second die-to-die clock interface circuit system 128B may use a variety of through-hole structures (e.g., through substrate vias (TSVs) (e.g., through silicon vias), wire bonding, microbumps, through-die vias (TDVs) or the like) to provide electrical connections between stacked semiconductor dies.

[0101] As shown, a first global clock signal 148A generated by a first PLL 124A is provided as input to a phase alignment element 126. The phase alignment element 126 may include circuitry and other components that use feedback from a second PLL 124B on a second die 102B to generate an aligned reference clock signal. The second PLL 124B may be similar to the first PLL 124A on the first die 102A and may include any of its structure and function. The second PLL 124B generates a second global clock signal 148B and provides it to various circuits / components present on the second die 102B. As shown, the second global clock signal 148B generated by the second PLL 124B can be provided as a second input to the phase alignment element 126.

[0102] Phase alignment element 126 can receive a first global clock signal 148A and a second global clock signal 148B generated by the first PLL 124A as inputs to generate a reference clock signal for alignment of the second PLL 124B. The aligned reference signal can be used to adjust the phase of the second global clock signal 148B so that the phases of the first global clock signal 148A and the second global clock signal 148B are aligned with each other. Using phase alignment element 126 enables the second die 102B to generate a second global clock signal 148B that is automatically aligned with the first global clock signal 148A of the first die 102A. This method enables subsequent dies to generate clock signals that are aligned with all phases of the global clock signal of the master die (e.g., the first die 102A), such as in combination with... Figure 2 Further detailed description.

[0103] Each of the first die 102A and the second die 102B may include any number of components or circuits, including, but not limited to, system-on-chip (SoC) components, processing components (e.g., adders, multipliers, arithmetic logic units, etc.), memory circuits, logic gates, components, or circuits, data transfer circuits, or any other type of computing component. In some embodiments, the first die 102A and the second die 102B may include high-performance computing circuitry, such as parallel processing elements for graphics processing units (GPUs), compute-in-memory (CIM) circuitry, or other computing circuitry systems. In addition to such components and circuitry, the first die 102A is illustrated as including a circuitry system for transmitting data to and receiving data from the second die 102B, including a first transmitter circuitry 104A and a first receiver circuitry 106A.

[0104] The first transmitter circuit 104A is illustrated as including a first transmission pipeline circuit 116A (sometimes referred to as "first transmission pipeline 116A"), one or more first transmission flip-flops 114A, and a first die-to-die transmission interface circuit system 112A. The first die-to-die transmission interface circuit system 112A enables the transmission of data generated or accessed at the first die 102A to the second die 102B. The first die-to-die transmission interface circuit system 112A of the first die 102A may be electrically coupled to a corresponding second die-to-die receiver interface circuit system 110B of the second die 102B. The first die-to-die transmission interface circuit system 112A may include, but is not limited to, TSVs, wire junctions, microbumps, TDVs, or the like.

[0105] As shown in the figure, data transmission using the first die-to-die transfer interface circuit system 112A is provided by one or more first transfer flip-flops 114A. The first transfer flip-flops 114A may comprise any type of flip-flop, latch, or clock-controlled memory element capable of storing data according to set / hold constraints of the first die-to-die transfer interface circuit system 112A of the first die 102A and the second die-to-die receiver interface circuit system 110B of the second die 102B. In some embodiments, the first transfer flip-flops 114A may form a temporary register with a predetermined bit width. The first transmitter circuit 104A may include any number of first transfer flip-flops 114A to provide a transfer bus with any number of bits.

[0106] Each of the first transmit flip-flops 114A can receive a region clock signal generated by the first DCDL 134A of the first die 102A, as shown in the figure. The first DCDL 134A of the first die 102A can be used in conjunction with a region DCDL 136A of the first die 102A to reduce inter-die skew in a two-phase clock tuning procedure. Further details of the two-phase clock tuning method will be provided in conjunction with... Figure 3 The following description is provided. For example, the first DCDL 134A (sometimes referred to as the "first global DCDL 134A") of the first die 102A can be used to match the clock delay between the path from the first global clock signal 148A to the first die-to-die clock transmission interface circuit system 132A and the path from the second global clock signal 148B to the second die-to-die clock transmission interface circuit system 132B.

[0107] The first DCDL 134A may include any type of digital circuitry that enables control of signal timing by adjusting the propagation delay through a series of circuit elements (such as flip-flops or latches). The first DCDL 134A may include any suitable type of circuit delay element, including analog tunable delay elements and digitally controlled delay elements. The first DCDL 134A may be programmable, for example, by a control circuit. The control circuitry may be part of the first die 102A or external to the first die 102A. The first DCDL 134A may include any type of delay circuitry, including ring oscillator-based delay lines, PLL-based delay lines, tap delay lines, or switched-capacitor delay lines, etc. The delays of the aforementioned paths can be matched by scanning from the lowest potential delay to the maximum potential delay until the delays of the aforementioned paths for each die are mutually matched.

[0108] In addition to receiving the region clock signal from the first DCDL 134A, the first transmission flip-flop 114A also receives data input from the first transmission line 116A. The first transmission line 116A may contain any type of memory element that can store and configure data provided by the first traffic generator 120A for transmission via the first die-to-die transmission interface circuitry 112A. For example, the first transmission line 116A may contain any number of flip-flops, latches, or other memory elements to queue data for transmission from the first die 102A to the second die 102B. The data to be transmitted can be provided via the first traffic generator 120A.

[0109] The first traffic generator 120A may include any type of circuitry, logic components, or means for generating traffic to perform the various clock and delay synchronization techniques described herein. In some embodiments, the first traffic generator 120A may include logic components that automatically generate a predetermined data pattern. The first traffic generator 120A may generate data for transmission to the second die 102B and may include verification and validation logic (e.g., as part of or coupled to the second receiver pipeline circuitry 122B, which is further described in detail herein) to verify that the data is correctly transferred between the first die 102A and the second die 102B (e.g., without errors or corruption).

[0110] As shown in the figure, the first signal generator 120A and the first transmitter circuit 104A can each receive a region clock signal generated by the first DCDL 134A. Additionally, the region clock signal can be provided to the first receiver pipeline circuit 122A and the first receiver circuit 106A. The first receiver pipeline circuit 122A can receive data from the first receiver circuit 106A. The first receiver pipeline circuit 122A can include any number of memory elements, including, but not limited to, flip-flops, latches, static random access memory (SRAM), or dynamic random access memory (DRAM). In some embodiments, the first receiver pipeline circuit 122A can be coupled to one or more circuits that store, process, or transmit data received from the first receiver circuit 106A.

[0111] The first receiver circuit 106A is illustrated as including any number of first die-to-die receiver interface circuit systems 110A, one or more first receiver flip-flops 108A, and a first receiver data register 118A. The first die-to-die receiver interface circuit system 110A can receive data generated and transmitted from the second die 102B. The first die-to-die receiver interface circuit system 110A of the first die 102A can be electrically coupled to a corresponding second die-to-die transmission interface circuit system 112B of the second die 102B. The first die-to-die transmission interface circuit system 112A may include, but is not limited to, TSVs, wire junctions, microbumps, TDVs, or the like. As shown, the first die-to-die receiver interface circuit system 110A is electrically coupled to the first receiver flip-flop 108A.

[0112] The first receiver flip-flop 108A is shown receiving a clock signal from the first die-to-die clock receiver interface circuitry 130A, as described in further detail herein. The first receiver flip-flop 108A may include any type of flip-flop, latch, or clock memory element that can store data according to set / hold constraints of the first die-to-die receiver interface circuitry 110A of the first die 102A and the second die-to-die transfer interface circuitry 112B of the second die 102B, respectively. In some embodiments, the first receiver flip-flop 108A may form a register with a predetermined bit width. The first receiver circuitry 106A may include any number of first receiver flip-flops 108A to provide a transfer bus with any number of bits. The number of first receiver flip-flops 108A may be equal to the number of corresponding second transfer flip-flops 114B of the second transmitter circuitry 104B of the second die 102B.

[0113] The first receiver flip-flop 108A can receive and store data from the first die-to-die clock receiver interface circuit system 110A based on the clock signal received from the first die-to-die clock receiver interface circuit system 130A. The data stored in the first receiver flip-flop 108A can be provided to the first receiver data register 118A of the first receiver circuit 106A. The first receiver data register 118A can contain any type of memory element, such as a flip-flop, latch, static random access memory, or dynamic random access memory, storing the data received via the receiver flip-flop 108A. As shown, the first receiver data register 118A can receive the same clock signal from the first die-to-die clock receiver interface circuit system 130A as the first receiver flip-flop 108A. The data stored in the first receiver data register 118A can be retrieved by the receiver pipeline circuit 122A.

[0114] The receiver pipeline circuit 122A may include pipelines for registers or other memory elements that receive the region clock signal generated by the first DCDL 134A. In a system synchronization configuration, the memory elements in the receiver pipeline circuit 122A can retrieve data from the first receiver data register 118A provided in the clock domain of the clock signal of the first die-to-die clock receiver interface circuit system 130A. As described further herein, the clock signal received via the first die-to-die clock receiver interface circuit system 130A is synchronized with the region clock signal generated by the first DCDL 134A, thereby avoiding the need for additional buffer circuitry to asynchronously transfer data between clock domains. Data retrieved using the receiver pipeline circuit 122A can be directly accessed or otherwise processed by other components in the first die 102A. In some embodiments, the receiver pipeline circuit 122A may include verification and validation circuitry, such as cyclic redundancy check (CRC) circuitry.

[0115] To ensure that the clock signals used by the receiver circuitry (e.g., the first receiver circuitry 106A of the first die 102A and the second receiver circuitry 106B of the second die 102B) are synchronized with the regional clocks of the individual dies, additional delay circuitry can be utilized in the source synchronization configuration. As shown, the first die-to-die clock transmission interface circuitry system 132A receives the clock signals generated by the regional DCDL circuitry 136A of the first die 102A (sometimes referred to as "regional DCDL 136A" or "first regional DCDL 136A"). The first die-to-die clock transmission interface circuitry system 132A may include, but is not limited to, one or more TSVs, one or more wire junctions, one or more microbumps, one or more TDVs, or the like. As shown, the first die-to-die clock transmission interface circuitry system 132A provides the forwarded clock signals to the corresponding second die-to-die clock receiver interface circuitry system 130B of the second die 102B.

[0116] The clock signal, forwarded via the first chip-to-chip clock transmission interface circuit system 132A and received by the corresponding second chip-to-chip clock receiver interface circuit system 130B, can be generated by the region DCDL circuit 136A of the first chip 102A. The region DCDL circuit 136A can be similar to the first DCDL circuit 134A. The region DCDL 136A can be programmable, for example, by a control circuit. The control circuit can be part of the first chip 102A or external to the first chip 102A. The region DCDL 136A can include any type of delay circuit, including ring oscillator-based delay lines, PLL-based delay lines, tap delay lines, or switched capacitor delay lines, etc.

[0117] Region DCDL 136A can be tuned or otherwise programmed to provide suitable latency for a source-synchronous configuration used for data transfer between the first die 102A and the second die 102B. Using a source-synchronous configuration during data transfer eliminates die-to-die propagation delays in clock and data, resulting in higher bit rate transfers compared to other solutions. Further details on tuning / adjusting the first DCDL 134A and Region DCDL 136A will be discussed in conjunction with... Figure 3 Describe it.

[0118] The second die 102B includes components and structures similar to those of the first die 102A. The second die 102B is illustrated as including a second receiver circuit 106B (electrically coupled to the first transmitter circuit 104A), a second transmitter circuit 104B (electrically coupled to the first receiver circuit 106A), a second receiver pipeline circuit 122B, a second signal generator 120B, a second global DCDL circuit 134B, and a second regional DCDL circuit 136B. The second die 102B includes a second die-to-die clock receiver interface circuit system 130B (electrically coupled to the first die-to-die clock transmission interface circuit system 132A) and a second die-to-die clock transmission interface circuit system 132B (electrically coupled to the first die-to-die clock receiver interface circuit system 130A).

[0119] The second receiver circuit 106B (and its components) may include any structure and function of the first receiver circuit 106A. For example, the second receiver circuit 106B may include a second receiver data register 118B, one or more receiver flip-flops 108B, and a second chip-to-chip receiver interface circuit system 110B, which may be similar to the first receiver data register 118A, receiver flip-flops 108A, and first chip-to-chip receiver interface circuit system 110A of the first receiver circuit 106A. According to the techniques described herein, the second receiver circuit 106B may receive data from the first transmitter circuit 104A.

[0120] Data transmitted by the second transmitter circuit 104B can be generated by the second service generator 120B, which can be similar to the first service generator 120A and include any of its structure and functions. Data received by the second receiver circuit 106B can be captured by the second receiver pipeline circuit 122B, which can be similar to the first receiver pipeline circuit 122A and include any of its structure and functions. The second die 102B may include a second DCDL circuit 134B, which can be programmed to generate a regional clock signal that matches the delay between mutually matched forwarding transmission clocks (e.g., provided via the first die-to-die clock transmission interface circuit system 132A and the second die-to-die clock transmission interface circuit system 132B), such as in combination. Figure 3 Further detailed description.

[0121] The second die 102B is illustrated as including a second DCDL circuit 136B, which may be similar to the region DCDL circuit 136A and include any of its structure or function. The region DCDL 136A may be tuned or otherwise programmed to provide suitable delays, enabling a source-synchronous configuration for data transfer between the second die 102B and the first die 102A. Using a source-synchronous configuration during data transfer eliminates die-to-die propagation delays for clock and data, resulting in a higher bit rate transfer compared to other solutions. Further details on tuning / adjusting the first region DCDL 136A and the second region DCDL 136B will be discussed in conjunction with... Figure 3 Describe it.

[0122] In some implementations, each of the first DCDL circuit 134A and the first region DCDL circuit 136A of the first die 102A, and the second DCDL circuit 134B and the second region DCDL circuit 136B of the second die 102B, may include persistent memory elements that, when configured according to the techniques described herein, maintain the same programmed state even in the event of a power-off or reset event of the first die 102A and / or the second die 102B. For example, the first DCDL circuit 134A and the first region DCDL circuit 136A of the first die 102A, and the second DCDL circuit 134B and the second region DCDL circuit 136B of the second die 102B, may include eFuse memory, flash memory, or other persistent memory elements that retain their state even when the circuit is powered off. This feature allows the delay and bit rate of data transfer between the first die 102A and the second die 102B to be configured at once (e.g., during device manufacturing, during device configuration steps, etc.) without the need for further clock synchronization configuration operations.

[0123] While the foregoing describes in detail an example comprising two separate dies (e.g., first die 102A and second die 102B), it should be understood that the techniques described herein can be implemented with any number of dies, each of which can be any component described in conjunction with first die 102A and second die 102B. Furthermore, each of first die 102A and second die 102B may include any number of circuits for using data communicated between the dies, in addition to any processing, memory, or data transfer operations that can be performed using a semiconductor device. Each additional processing circuit of first die 102A and second die 102B may, for example, receive a first global clock signal 148A generated by first PLL 124A and a second global clock signal 148B generated by second PLL 124B, respectively, or receive regional clock signals generated by first DCDL 134A of second die 102B and second DCDL 134B of second die 102B, respectively.

[0124] Figure 2 A block diagram of a system comprising multiple dies implementing the die-to-die circuit communication technology described herein, according to some embodiments, is illustrated. In this example, system 200 is illustrated as comprising a primary die 202. The primary die 202 is illustrated as communicating with three auxiliary dies 204A, 204B, and 204C (sometimes referred to herein as "one or more auxiliary dies 204"). The primary die 202 may be similar to Figure 1 The first die 102A includes any structural and functional embodiments thereof. The main die 202 is illustrated as including a main PLL 205, which may be similar to... Figure 1 The first PLL 124A.

[0125] In system 200, the primary PLL 205 of the primary die 202 can provide a clock signal (e.g., a first global clock signal 148A, etc.) to each of the auxiliary dies 204. For this purpose, the primary die 202 may include a clock transmission interface circuitry (e.g., a first die-to-die clock interface circuitry 128A) for each of the auxiliary dies 204, and each of the auxiliary dies 204 may include a corresponding clock receiver circuitry (e.g., a second die-to-die clock interface circuitry 128B) that receives the clock signal and provides it to phase alignment elements (e.g., phase alignment elements 208A, 208B, and 208C).

[0126] Auxiliary dies 204A, 204B, and 204C are illustrated as including phase alignment elements 208A, 208B, and 208C (sometimes referred to as "one or more phase alignment elements 208") and auxiliary PLLs 206A, 206B, and 206C (sometimes also referred to as "one or more auxiliary PLLs 206"). Phase alignment element 208 may be similar to phase alignment element 126 and may include any of its structure and function. For example, phase alignment element 208 may include circuitry and other components that use feedback from the corresponding auxiliary PLL 206 of auxiliary die 204 to generate an aligned reference clock signal.

[0127] The aligned reference clock signal is then provided as input to the auxiliary PLL 206, which generates an individual global clock signal at each of the auxiliary dies 204. A phase alignment element 208 enables the generation of an individual global clock signal having a phase that is automatically aligned and locked to the phase of the global clock signal provided by the main PLL 205. Using phase alignment avoids the need for additional buffer circuitry to compensate for misaligned clocks resulting from a single main die being distributed to multiple auxiliary dies. Although three auxiliary dies 204 are illustrated in system 200, it should be understood that any number of auxiliary dies 204 can communicate with the main die 202. Furthermore, although all auxiliary dies 204 are illustrated as occupying a single layer, it should be understood that the main die 202 and auxiliary dies 204 can be arranged in any suitable configuration to implement any type of 3D-IC.

[0128] When the global clock signal generated by each auxiliary die is automatically aligned with the main clock signal of the main die 202, the system 200 can implement a hybrid system synchronization and source synchronization clock domain transfer method, maximizing data yield and minimizing latency. Further details of the specific tuning techniques for the various delay circuits (e.g., the first DCDL circuits 134A, 136A and the second DCDL circuits 134B, 136B) used to mitigate the effects of propagation delay will be provided in conjunction with... Figure 3 Describe it.

[0129] Figure 3A block diagram of an example system 300 implementing high-bandwidth and low-latency die-to-die circuit communication according to some embodiments is illustrated. System 300 or its components may include one or more logic gates and sub-circuits, each sub-circuit being constructed from one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to produce a single output signal. Various embodiments of the circuitry and logic gates implementing system 300 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, or the like.

[0130] Figure 3 System 300 can be similar to Figure 1 The system 100, including any of its structures and components, and implementing... Figure 1 Any functionality of system 100. System 300 is illustrated as including a first die 302A (which may be similar to the first die 102A and include any of its structures) communicating with the second die 302B (which may be similar to the first die 102A and include any of its structures).

[0131] In the example configuration shown in system 100, the first die 302A is the master die (or primary die), which uses the first PLL 324A to generate the first global clock signal 348A. Although for visual clarity, the first PLL 324A... Figure 3 The first PLL 324A is depicted outside the boundary of the first die 302A, but it should be understood that the first PLL 324A may be included in the circuitry on the first die 302A, or otherwise defined as the circuitry on the first die 302A. The first PLL 324A may be similar to... Figure 1 The first PLL 124A and includes any of its structure and functions.

[0132] The first PLL 324A can operate using a feedback mechanism to generate an output clock signal, illustrated here as a global clock (CLK) 348A, and synchronize it with a reference clock signal. The reference clock signal can be any type of reference clock signal, such as a square wave clock signal provided via reference clock generation circuitry. The reference clock can be generated via circuitry included in the first die 302A or received from an external clock source in communication with the first die 302A. In some implementations, the first PLL 324A can be initialized in response to a reset signal or a signal from a control circuitry system that can control or otherwise enable various circuits in the first die 302A.

[0133] As shown in the figure, the first PPL 324A of the first die 302A can provide the first global clock signal 348A to the first die-to-die clock interface circuit system 328A and other circuit systems in the first die 302A, such as the first global DCDL 334A. The first die-to-die clock interface circuit system 328A and the first global DCDL 334A can be similar to the first die-to-die clock interface circuit system 128A and the first DCDL 134A, respectively, and can include any of their structures or functions. As shown in the figure, the first die-to-die clock interface circuit system 328A of the first die 302A can be electrically coupled to the corresponding second die-to-die clock interface circuit system 328B of the second die 302B. As described herein, the first die-to-die clock interface circuit system 328A can be used to transmit the first global clock signal 348A to components in the second die 302B.

[0134] As shown in the figure, the first global clock signal 348A generated using the first PLL 324A is provided as input to the phase alignment element 326. The phase alignment element 326 can be similar to Figure 1 The phase alignment element 126 performs any of its functions, and the second PLL 324B can be similar to... Figure 1 The second PLL 124B includes any of its structure and functions. The second PLL 324B can generate a second global clock signal 348B, which is provided to various circuits / components present on the second die 302B. As shown in the figure, as described herein, the second global clock signal 348B generated by the second PLL 324B can be provided as a second input to the phase alignment element 326, such that the second PLL 324B generates a second global clock signal 348B having the same phase as the first global clock signal 348A.

[0135] Each of the first grain 302A and the second grain 302B is depicted as containing and Figure 1 The first die 102A and the second die 102B are similar components. The first die 302A is illustrated as including a first transmitter circuit 304A and a first receiver circuit 306A, which may include any components of the first transmitter circuit 104A and the first receiver circuit 106A and perform any of their functions. Data transmitted by the first transmitter circuit 304A may be provided by a first service generator 320A, which may be similar to... Figure 1 The first signal generator 120A. Data received by the first receiver circuit 306A can be captured by the first receiver pipeline circuit 322A, which can be similar to... Figure 1 The first receiver pipeline circuit is 122A.

[0136] As described herein, the corresponding components may reside on the second die 302B. The second die 302B is illustrated as including a second transmitter circuit 304B and a second receiver circuit 306B, which may include any components of the second transmitter circuit 304B and the second receiver circuit 306B, and perform any of their functions. Data transmitted by the second transmitter circuit 304B may be provided by a second signal generator 320B, which may be similar to... Figure 1 The second signal generator 120B. Data received by the second receiver circuit 306B can be captured by the second receiver pipeline circuit 322B, which can be similar to... Figure 1 The second receiver pipeline circuit 122B.

[0137] As described herein, the first transmitter circuit 304A can communicate electrically with and transmit data to the corresponding second receiver circuit 306B, while the second transmitter circuit 304B can communicate electrically with and transmit data to the corresponding first receiver circuit 306A. Figure 1 Similarly, the first die 102A and the second die 102B can communicate with each other using an interface circuit system. The interface circuit system may include, but is not limited to, TSV, wire bonding or TDV.

[0138] As described herein, the forwarding clock signal used by the first receiver circuit 306A can be provided via the second chip-to-chip clock transmission interface circuit system 332B of the second chip 302B, and received via the first chip-to-chip clock receiver interface circuit system 330A of the first chip 302A, wherein each can be similar to Figure 1 The second chip-to-chip clock transmission interface circuit system 132B and the first chip-to-chip clock receiver interface circuit system 130A. Similarly, the forwarding clock signal used by the second receiver circuit 306B can be provided via the chip-to-chip clock transmission interface circuit system 330A of the first chip 302A and received via the second chip-to-chip clock receiver interface circuit system 330B of the second chip 302B, wherein each can be similar to Figure 1 The first chip-to-chip clock transmission interface circuit system 132A and the second chip-to-chip clock receiver interface circuit system 130B.

[0139] The configuration shown in system 300 can be used to tune or otherwise adjust the first global DCDL circuit 334A of the first die 302A and the second global DCDL circuit 334B of the second die 302B (sometimes referred to as "global DCDL circuits 334A and 334B", "one or more global DCDL circuits 334", or "one or more global DCDL 334"), and to tune or otherwise adjust the region DCDL circuit 336A of the first die 302A and the region DCDL circuit 336B of the second die 302B. As shown, in some embodiments, the first die 302A and the second die 302B may respectively include on-chip clock correction (OCC) circuits 338A and 338B (sometimes commonly referred to as "one or more OCC circuits 338"). Because the clock path generated by the global DCDL circuit 334 may be relatively large, duty cycle distortion may occur. To correct these problems, the OCC circuit 338 can be used to generate a first-region clock signal 350A and a second-region clock signal 350B with corrected operating cycles for the first die 302A and the second die 302B, respectively. The OCC circuit 338 may include one or more clock divider circuits that receive the output of the global DCDL 334 and generate the first-region clock signal 350A and the second-region clock signal 350B as outputs. In some embodiments, the OCC circuit 338 may include delay circuit elements that adjust the timing of the rising and falling edges of the input clock signals, thereby correcting the operating cycle imbalance caused by signal propagation delay.

[0140] As shown in the figure, the first region clock signal 350A can be provided to the first service generator 320A, the first receiver pipeline circuit 322A, and additional delay components in the first die 302A, illustrated here as the second region DCDL 336B, the first multiplexer 340A, and the second multiplexer 342A. Similarly, the second region clock signal 350B can be provided to the second service generator 320B, the second receiver pipeline circuit 322B, and additional delay components in the second die 302B, illustrated here as the second region DCDL 336B, the first multiplexer 340B, and the second multiplexer 342B. Each delay element can be controlled, for example, by input from the control circuitry of the first die 302A and / or the second die 302B, to generate any desired delay for the first region clock signal 350A and the second region clock signal 350B, thereby maximizing the transfer bit rate while minimizing system latency.

[0141] In the example configuration procedure, various delay elements in the first die 302A and the second die 302B can be adjusted in two stages. Each delay element described herein can be adjusted via the control circuitry system of the first die 302A and the second die 302B or via an external control circuitry system communicating with the first die 302A and / or the second die 302B. In the first stage of the tuning procedure, the global DCDLs 334A and 334B can be iteratively tuned such that the clock delays from the first region clock signal 350A and the second region clock signal 350B of the OCC circuits 338A and 338B to the first die-to-die clock transmission interface circuitry system 332A and the second die-to-die clock transmission interface circuitry system 332B, respectively, are equal to each other.

[0142] As this article combines Figure 1 As described in the first DCDL 134A and the second DCDL 134B, the global DCDLs 334A and 334B may include programmable delay elements capable of applying a set of predetermined delays to the input clock signal. When the first PLL 324A and the second PLL 324B are locked and generate phase-aligned global clock signals 348A and 348B, programming or other adjustments to the global DCDLs 334A and 334B can be performed. In a first stage, the global DCDLs 334A and 334B can be iteratively adjusted (e.g., using a scan across all programmable settings) until the clock delay from the first PLL 324A to the first die-to-die clock transmission interface circuitry 332A in the first die 302A matches the clock delay from the second PLL 324B to the second die-to-die clock transmission interface circuitry 332B in the second die 302B.

[0143] In some embodiments, this delay can be monitored by a control circuitry communicating with the first die 302A and the second die 302B. In the first stage, the second multiplexers 342A and 342B of the first die 302A and the second die 302B can each be in a first state, such that the outputs of the OCC circuits 338A and 338B are directly transmitted to the first die-to-die clock transmission interface circuitry 332A and the second die-to-die clock transmission interface circuitry 332B, respectively. The states of the second multiplexers 342A and 342B can be controlled, for example, using corresponding signals generated by the control circuitry communicating with the first die 302A and the second die 302B. The states of the third multiplexers 346A and 346B can be controlled, for example, using corresponding signals generated by control circuitry communicating with the first die 302A and the second die 302B, such that the third multiplexers 346A and 346B provide a first region clock signal 350A and a second region clock signal 350B to the first receiver circuit 306A and the second receiver circuit 306B, respectively. Therefore, the first tuning phase can be performed in system synchronization mode. The global DCDLs 334A and 334B can be adjusted to select the minimum possible delay while matching the delay of the clock path between the first die 302A and the second die 302B, with the aim of delaying the die with a faster global clock backbone.

[0144] Once the full-domain DCDLs 334A and 334B are tuned, the second tuning stage can adjust each of the first region DCDL 336A and the second region DCDL 336B (sometimes referred to as "one or more region DCDLs 336A and 336B", "one or more region DCDL circuits 336A and 336B", or "one or more region DCDLs 336"). Region DCDL 336 can be adjusted in source-synchronous mode to further increase the bit rate while minimizing overall system latency. Any of the first multiplexers 340A and 340B, the second multiplexers 342A and 342B, the third multiplexers 346A and 346B, and the regions DCDLs 336A and 336B can be enabled, disabled, or adjusted to perform the second tuning step. The second tuning step can be used to compensate for the worst-case inflection point changes between the first region clock signal 350A and the second region clock signal 350B and the forwarding clock received via the first chip-to-chip clock receiver interface circuit system 330A and the second chip-to-chip clock receiver interface circuit system 330B, respectively.

[0145] To perform the second tuning step, the third multiplexers 346A and 346B can each switch to source-synchronous mode. In source-synchronous mode, the clock signals received from the first die-to-die clock receiver interface circuit system 330A and the second die-to-die clock receiver interface circuit system 330B are provided as inputs to the first receiver circuit 306A and the second receiver circuit 306B, respectively. When source-synchronous mode is enabled, one or more of the first multiplexers 340A and 340B, the second multiplexers 342A and 342B, and the regions DCDL 336A and 336B can be enabled, disabled, or adjusted to minimize the regional clock skew across the first die 302A and the second die 302B in source-synchronous mode.

[0146] First multiplexers 340A and 340B can be enabled to apply regions DCDL 336A and 336B to the first transmitter circuit 304A and the second transmitter circuit 304B, respectively (e.g., delaying data transmission to resolve skew), and second multiplexers 342A and 342B can be enabled to apply regions DCDL 336A and 336B to the second receiver circuit 306B and the first receiver circuit 306A, respectively (e.g., delaying data acquisition from the opposite die 302 to resolve skew). For example, if clock skew causes a setting violation at the second receiver circuit 306B of the second die 302B, the second multiplexer 342A can be activated, and the delay of region DCDL 336A of the first die 302A can be adjusted according to a control input (e.g., determined by scanning to optimize the transfer bit rate) to resolve clock skew. If a setting violation is detected at the first die 302A, similar adjustments can be performed at the second die 302B for the second multiplexer 342B and the second region DCDL 336B.

[0147] In another example, if clock skew causes a hold violation in the first transmitter circuit 304A of the first die 302A, the first multiplexer 340A can be activated, and the delay of the region DCDL 336A of the first die 302A can be adjusted according to control inputs (e.g., determined by scanning to optimize the transfer bit rate) to resolve the clock skew mismatch. If a hold violation is detected at the second transmitter circuit 304B of the second die 302B, similar adjustments can be performed at the second die 302B for the first multiplexer 340B and the region DCDL 336B.

[0148] In some embodiments, tuning of the global DCDL 334 and the regional DCDL 336 can be performed by iteratively applying one of a predetermined set of delay inputs to a given DCDL to select the delay to be evaluated. Each DCDL described herein can be controlled via one or more control registers that enable programmable delays by establishing predetermined circuit paths through a predetermined number of delay circuit elements. The DCDLs described herein can contain any suitable delay resolution, such as four-bit resolution, six-bit resolution, or eight-bit resolution.

[0149] When the global DCDL 334 and the regional DCDL 336 are tuned, the configuration value of each DCDL can be stored in memory and applied to the configuration inputs of the global DCDL 334 and the regional DCDL 336, thereby correcting the latency after configuration. Similar control inputs can be stored and applied to the first multiplexers 340A and 340B, the second multiplexers 342A and 342B, and the third multiplexers 346A and 346B. By using the aforementioned clock paths and delay circuits, system 300 can implement hybrid system synchronization and source synchronization clock allocation schemes across any number of semiconductor dies. It should be understood that although two dies are described in conjunction with this example, the use of the techniques described herein, including similar... Figure 2 The configuration shown allows any number of semiconductor chips to be synchronized with each other.

[0150] Figure 4 This is an example flowchart of a method 400 for configuring and implementing circuitry to perform the die-to-die circuit communication technology described herein, according to some embodiments. It should be noted that method 400 is merely an example and is not intended to limit this disclosure. Therefore, it can be understood that... Figure 4 The order of operations in method 400 can be changed. Figure 4 Additional operations are provided before, during, and after Method 400, and only a few of these additional operations may be briefly described in this document.

[0151] Method 400 begins with operation 402, in which a data transfer procedure is initiated in a system synchronization mode between a first die (e.g., first die 102A, 202, 302A) and a second die (e.g., second die 102B, 204, 302B) having different clock domains. In some implementations, the first die may be a master die / major die, and the second die may be a slave die / auxiliary die. The first die may use a first PLL (e.g., first PLL 124A, 324A) to generate a first global clock signal (e.g., first global clock signal 148A) provided to the second die. The second die may use phase alignment elements (e.g., phase alignment elements 126, 326) and a second PLL (second PLL 124B, second PLL 324B) to generate a second global clock signal.

[0152] The system synchronization mode can be initiated by adjusting the state of one or more multiplexers (e.g., first multiplexers 340A and 340B, second multiplexers 342A and 342B, and third multiplexers 346A and 346B) of the first and second dies to distribute individual global clock signals to each component of the individual die. In some embodiments, the global clock signals may be provided as input to individual OCC circuits (e.g., OCC circuits 338A and 338B) of the first and second dies. In the system synchronization mode, the output of the OCC circuits may be provided to the transmitter circuits (e.g., first transmitter circuit 304A and second transmitter circuit 304B) and receiver circuits (e.g., first receiver circuit 306A and second receiver circuit 306B) of the first and second dies. Data transfer can be initiated by enabling data from one or more of the signal generators (e.g., first signal generators 120A and 320A) of the first and second dies.

[0153] Method 400 continues to operation 404, in which a first delay circuit (e.g., a first global DCDL 134A, 334A) of the first die is adjusted to match a first delay of the first transmission circuit of the first die with a second delay of the second transmission circuit of the second die. In some embodiments, the delay can be optimized by monitoring the bit rate of the data transfer procedure and selecting one of a set of predetermined delay values ​​for the delay circuit (used to optimize the initial bit rate from the first die to the second die). In some embodiments, the delay can be monitored by measuring the clock skew difference between the first die and the second die. This includes the clock skew of the first path from the first PLL of the first die to the first clock transmission interface (e.g., the first die to die clock transmission interface circuitry 132A, 332A) and the clock skew of the second path from the second PLL of the second die to the second clock transmission interface (e.g., the second die to die clock transmission interface circuitry 132B, 332B).

[0154] In some embodiments, the global delay circuit at the first or second die can be adjusted along the aforementioned path depending on whether the clock speed at the first die is later (e.g., slower) or earlier (e.g., faster) than the clock speed at the second die. In some embodiments, if the first global clock speed at the first die is faster than the second global clock speed at the second die, the first global delay circuit at the first die can be enabled and adjusted to resolve skew. In some embodiments, if the second global clock speed at the second die is faster than the first global clock speed at the first die, the second global delay circuit at the second die can be enabled and adjusted to resolve skew.

[0155] Method 400 continues to operation 406, in which the second delay circuit of the first chip (e.g., the first region DCDL 136A, 336A) is adjusted according to a set mismatch or a maintained mismatch to generate a forwarding clock signal for the first chip. Before adjusting or enabling the second delay circuit, the first and second chips can be operated in source-synchronous mode. For this purpose, multiplexers (e.g., third multiplexers 346A, 346B) at the first and second chips can be changed to a state such that the first receiver circuit of the first chip (e.g., the first receiver circuit 306A) receives the forwarding clock signal from the second chip, and the second receiver circuit of the second chip (e.g., the second receiver circuit 306B) receives the forwarding clock signal from the first chip.

[0156] When source-synchronous mode is configured, the regional delay circuitry at the first and / or second die can be selectively applied to resolve any detected set-up or hold violations. To enable the regional delay circuitry, additional multiplexers (e.g., first multiplexers 340A, 340B, second multiplexers 342A, 342B) can be selectively enabled to resolve set-up / hold violations at each die. For example, if clock skew causes a set-up violation at the second receiver circuitry of the second die, a multiplexer at the first die (e.g., second multiplexer 342A) can be enabled to apply the delay of the regional delay circuitry (e.g., first region DCDL 336A) of the first die. The regional delay circuitry can be adjusted based on control inputs (e.g., determined via scan to optimize the transfer bit rate) to resolve clock skew. If a setting violation is detected at the first receiver circuit of the first die, similar adjustments can be made to the corresponding multiplexer (e.g., the second multiplexer 342B) and delay circuit (e.g., the region DCDL 336B) at the second die.

[0157] In another example, if clock skew causes a hold violation at the first transmitter circuit of the first die, another multiplexer (e.g., first multiplexer 340A) can be activated, and a delay circuit of the first die 302A (e.g., first region DCDL 336A) can be applied to the input clock signal of the first transmitter circuit. As described herein, the region delay circuit can be adjusted based on a control input (e.g., determined via scanning to optimize the transfer bit rate) to resolve the clock skew mismatch. If a hold violation is detected at the second transmitter circuit of the second die, similar adjustments can be performed on another corresponding multiplexer (e.g., first multiplexer 340B) and delay circuit (e.g., region DCDL 336B) at the second die.

[0158] When the global and regional delay circuits are tuned / adjusted, the configuration value for each delay can be stored in memory (e.g., eFuse or other persistent memory) and applied to the configuration inputs of the delay circuits after startup or reset, thereby correcting the delays after configuration. Similar control inputs can be stored and applied to each multiplexer at the first and second dies (e.g., first multiplexers 340A and 340B, second multiplexers 342A and 342B, and third multiplexers 346A and 346B). Using the above techniques, the first and second dies can be tuned to implement hybrid system synchronization and source synchronization clock allocation schemes across any number of semiconductor dies.

[0159] In one embodiment of this disclosure, a semiconductor device is disclosed. The semiconductor device includes a first die and a second die. The first die has a transmitter circuit and a first phase-locked loop (PLL) circuit for generating a first global clock signal. The second die has a receiver circuit, a phase alignment element, and a second PLL circuit. The phase alignment element generates a reference clock signal using the first global clock signal and feedback from the second PLL circuit. The second PLL circuit generates a second global clock signal based on the reference clock signal. The phases of the first and second global clock signals are aligned to facilitate data transfer from the transmitter circuit to the receiver circuit.

[0160] In some embodiments of this type of semiconductor device, the first die is electrically coupled to the second die through one or more of a plurality of through-silicon vias, a plurality of wire bondings, a plurality of microbumps, or a plurality of through-die vias.

[0161] In some embodiments of this type of semiconductor device, the receiver circuit of the second die is used to operate in source-synchronous mode by receiving a first global clock signal forwarded from the first die via a die-to-die clock interface.

[0162] In some embodiments of this type of semiconductor device, the receiver circuit of the second die is used to operate in system synchronization mode by receiving a second global clock signal generated by the second phase-locked loop circuit.

[0163] In some embodiments of this type of semiconductor device, the semiconductor device further includes an on-chip clock correction circuit. The on-chip clock correction circuit is used to correct the duty cycle of the first global clock signal.

[0164] In some embodiments of this type of semiconductor device, the semiconductor device further includes a programmable global delay circuit for: receiving a first global clock signal generated by a first phase-locked loop circuit; and generating a first regional clock signal having a delay selected based on a clock skew between the first global clock signal and a second global clock signal.

[0165] In some embodiments of this type of semiconductor device, the first die further includes a first receiver circuit. The first receiver circuit is used to receive a second global clock signal relayed from the second die in a source-synchronous configuration.

[0166] In some embodiments of this type of semiconductor device, the first die further includes a region delay circuit. The region delay circuit is used to delay either the input clock for the transmitter circuitry or the input clock for the first die-to-die clock transmission interface of the first die.

[0167] In some embodiments of this type of semiconductor device, the second die further includes a second region delay circuit. The second region delay circuit is used to delay either the input clock of the second transmitter circuit of the second die or the input clock of the second die-to-die clock transmission interface of the second die.

[0168] In some embodiments of this type of semiconductor device, the first die further includes a die-to-die global clock transmission interface. The die-to-die global clock transmission interface is used to transmit a first global clock signal to a phase alignment element of the second die.

[0169] In some embodiments of this type of semiconductor device, the semiconductor device further includes a third die. The third die is electrically coupled to the first die and has a second receiver circuit, a second phase alignment element, and a third phase-locked loop circuit. The second phase alignment element is used to generate a second reference clock signal using a first global clock signal and feedback from the third phase-locked loop circuit. The third phase-locked loop circuit is used to generate a third global clock signal for the third die based on the second reference clock signal.

[0170] In some embodiments of this type of semiconductor device, the first die further includes a second transmitter circuit, and the phase of the first global clock signal is aligned with the phase of the third global clock signal to facilitate data transfer from the second transmitter circuit to the second receiver circuit.

[0171] In another embodiment of this disclosure, a semiconductor die is disclosed. The semiconductor die includes a phase-locked loop (PLL) circuit, a multiplexer, and a receiver circuit. The PLL circuit generates a first global clock signal. The multiplexer selects between the first global clock signal and a second global clock signal, the second global clock signal being electrically coupled to a second die relay of the semiconductor die. The receiver circuit receives the output from the multiplexer and receives data transmitted from the second die.

[0172] In some embodiments of this other type of semiconductor die, the semiconductor die further includes a global delay circuit. The global delay circuit is used to apply a programmable delay to a first global clock signal. A multiplexer is used to select between delaying the first global clock signal and a second global clock signal.

[0173] In some embodiments of this other type of semiconductor die, the semiconductor die further includes a region delay circuit. The region delay circuit is used to receive a delayed first global clock signal as input and generate a delayed region clock signal.

[0174] In some embodiments of this other type of semiconductor die, the semiconductor die further includes a transmitter circuit and a second multiplexer. The transmitter circuit is used to transmit data to the second die. The second multiplexer is used to select between a delayed first global clock signal and a delayed regional clock signal. The output of the second multiplexer is provided to the transmitter circuit.

[0175] In some embodiments of this other type of semiconductor die, the semiconductor die further includes a die-to-die clock transmission interface and a third multiplexer. The die-to-die clock transmission interface is used to forward clock signals to a second die. The third multiplexer is used to select between a delayed first global clock signal and a delayed regional clock signal. The output of the third multiplexer is provided to the die-to-die clock transmission interface.

[0176] In another embodiment of this disclosure, an operating method is disclosed. The operating method includes the following steps: initiating a data transfer procedure between a first die and a second die having different clock domains in a system synchronization mode; adjusting a first delay circuit of the first die such that a first delay corresponding to a first transmission circuit of the first die matches a second delay corresponding to a second transmission circuit of the second die; and adjusting the second delay circuit of the first die according to a set mismatch or maintaining a mismatch to generate a forwarding clock signal for the first die.

[0177] In some embodiments of this alternative operating method, the step of initiating the data transfer procedure in system synchronization mode includes the following steps: causing a first multiplexer to output a first global clock signal of the first die to a first receiver circuit of the first die, wherein the first multiplexer is used to select between the first global clock signal and a second global clock signal forwarded from the second die.

[0178] In some embodiments of this alternative operating method, the step of adjusting the second delay circuit includes the following steps: switching to source synchronization mode by causing the first multiplexer to output a second global clock signal forwarded from the second die.

[0179] In another embodiment of this disclosure, a semiconductor device is disclosed. The semiconductor device includes a first die and a second die. The first die includes a first transmission circuit, a first delay circuit, and a second delay circuit. The second delay circuit is adjusted according to a set mismatch or a maintained mismatch to generate a forwarding clock signal for the first die. The second die includes a second transmission circuit. The first die and the second die have different clock domains. The first delay circuit is adjusted to match a first delay corresponding to the first transmission circuit of the first die with a second delay corresponding to the second transmission circuit of the second die.

[0180] As used herein, the terms “about” and “approximately” generally mean plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0181] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same benefits. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A first die, having a transmitter circuit and a first phase-locked loop circuit, the first phase-locked loop circuit being used to generate a first global clock signal; and A second die includes a receiver circuit, a phase alignment element, and a second phase-locked loop (PLL) circuit. The phase alignment element generates a reference clock signal using the first global clock signal and feedback from the second PLL circuit. The second PLL circuit generates a second global clock signal based on the reference clock signal. One phase of the first global clock signal is aligned with one phase of the second global clock signal to facilitate a data transfer from the transmitter circuit to the receiver circuit.

2. The semiconductor device as claimed in claim 1, characterized in that, The receiver circuit of the second chip is used to operate in a source-synchronous mode by receiving the first global clock signal forwarded from the first chip via a chip-to-chip clock interface.

3. The semiconductor device as claimed in claim 1, characterized in that, The receiver circuit of the second chip is used to operate in a system synchronization mode by receiving the second global clock signal generated by the second phase-locked loop circuit.

4. The semiconductor device as claimed in claim 1, characterized in that, It further includes a programmable global delay circuit for: Receive the first global clock signal generated by the first phase-locked loop circuit; and A first regional clock signal is generated, the first regional clock signal having a delay selected based on a clock skew between the first global clock signal and the second global clock signal.

5. The semiconductor device as claimed in claim 1, characterized in that, The first die further includes a region delay circuit for delaying either an input clock for the transmitter circuit or an input clock for a first die-to-die clock transmission interface of the first die.

6. The semiconductor device as claimed in claim 5, characterized in that, The second die further includes a second region delay circuit, which is used to delay either an input clock of a second transmitter circuit of the second die or an input clock of a second die-to-die clock transmission interface of the second die.

7. The semiconductor device as claimed in claim 1, characterized in that, The first die further includes a die-to-die global clock transmission interface, which is used to transmit the first global clock signal to the phase alignment element of the second die.

8. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A third die is electrically coupled to the first die. The third die has a second receiver circuit, a second phase alignment element, and a third phase-locked loop circuit. The second phase alignment element is used to generate a second reference clock signal using the first global clock signal and a feedback from the third phase-locked loop circuit. The third phase-locked loop circuit is used to generate a third global clock signal for the third die based on the second reference clock signal.

9. A semiconductor die, characterized in that, Include: A phase-locked loop circuit is used to generate a first global clock signal; A multiplexer is used to select between a first global clock signal and a second global clock signal, the second global clock signal being electrically coupled to a second die forwarder of the semiconductor die. as well as A receiver circuit is used to receive an output from the multiplexer and to receive data transmitted by the second die.

10. A semiconductor device, characterized in that, Include: A first die includes a first transmission circuit, a first delay circuit, and a second delay circuit, wherein the second delay circuit is adjusted according to a set mismatch or a hold mismatch to generate a forwarding clock signal for the first die; and A second die, comprising a second transmission circuit, The first grain and the second grain have different time-wave domains, and The first delay circuit is used to be adjusted to match a first delay of the first transmission circuit corresponding to the first die with a second delay of the second transmission circuit corresponding to the second die.

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