A multi-communication test circuit

Abstract

This utility model belongs to the technical field of test circuits, and particularly relates to a multi-communication test circuit. The multi-communication test circuit includes a main control chip with at least one communication receiver and at least one communication output; at least one communication module with a first receiver and a first output, the first receiver connected to the output harness to receive a first communication signal, and the first output connected to the receiver to convert the first communication signal into a second communication signal and send it to the main control chip; and a communication conversion module located between the communication output and the aging component to convert the signal from the communication output into a third communication signal. This allows the aging device to convert different communication signals into a unified communication signal and send it to the aging component via the main control chip and the communication conversion module, thus avoiding cost waste.

Description

Technical Field

[0001] This utility model belongs to the technical field of test circuits, and in particular relates to a multi-communication test circuit. Background Technology

[0002] Aging tests for energy storage and smart power battery packs are a necessary step in the production testing of battery packs. The purpose is to simulate the aging process and performance parameters of the product during long-term use.

[0003] In existing technologies, each battery pack requires a different communication method. Therefore, when conducting communication tests on different products, it is necessary to set up different communication modules or different aging chambers for each product to achieve aging tests.

[0004] Designing different communication modules for different products or setting up aging cabinets with different communication methods will make testing and production costs very high, and the testing flexibility will be very poor, which will further lead to low production efficiency. Utility Model Content

[0005] To address the technical problem that "different products using different communication modules or aging cabinets with different communication methods result in very high testing and production costs, poor testing flexibility, and ultimately low production efficiency," this invention proposes a multi-communication test circuit.

[0006] This utility model solves the above problems through the following technical means: In a first aspect, this utility model proposes a multi-communication test circuit, disposed between an aging device and an aging component. The aging device is provided with an output wiring harness, and the aging component is provided with a receiving wiring harness. The multi-communication test circuit includes: The main control module is equipped with a main control chip U0, which has at least one communication receiver and at least one communication output. At least one communication module is provided with a first receiving end and a first output end. The first receiving end is connected to an output harness to receive a first communication signal, and the first output end is connected to the communication receiving end to convert the first communication signal into a second communication signal and send it to the main control chip U0; and The communication conversion module is located between the communication output terminal and the aging component to convert the signal from the communication output terminal into a third communication signal, and then transmits the third communication signal to the aging component via the receiving harness.

[0007] By placing a multi-communication test circuit between the aging device and the aging component, the aging device is equipped with an output wiring harness, and the aging component is equipped with a receiving wiring harness. The multi-communication test circuit includes a main control module with a main control chip U0, which has at least one communication receiver and at least one communication output; at least one communication module with a first receiver and a first output, the first receiver being connected to the output wiring harness to receive a first communication signal, and the first output being connected to the communication receiver to convert the first communication signal into a second communication signal and send it to the main control chip U0; and a communication conversion module, located between the communication output and the aging component, to convert the signal from the communication output into a third communication signal and send the third communication signal to the aging component via the receiving wiring harness. This allows the aging device to convert different communication signals into a unified communication signal and send it to the aging component through the main control chip U0 and the communication conversion module, thus avoiding resource waste caused by designing the aging device itself.

[0008] In some implementations, the communication conversion module includes a first chip circuit, a transient suppression circuit, a first MOSFET circuit, and a second MOSFET circuit; The input terminal of the first chip circuit is connected to the communication output terminal. The output terminal of the first chip circuit includes a third output terminal and a fourth output terminal. The third output terminal is connected to the input terminal of the first MOS transistor circuit, and the fourth output terminal is connected to the input terminal of the second MOS transistor circuit. The transient suppression circuit is set between the third output terminal and the fourth output terminal. The output terminals of the first MOS transistor circuit and the second MOS transistor circuit are connected to the receiving harness to send the third communication signal to the aging device.

[0009] In some implementations, the first chip circuit includes a first chip U1, a first resistor R1, and a second resistor R2; The first chip U1 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the main control chip U0 includes a first communication output terminal and a second communication output terminal. The first input terminal of the first chip is connected to the first communication output terminal through the first resistor R1, the second input terminal of the first chip is connected to the second communication output terminal through the second resistor R2, the first output terminal of the first chip is connected to the input terminal of the first MOS transistor circuit, and the second output terminal of the first chip is connected to the input terminal of the second MOS transistor circuit.

[0010] In some implementations, the transient suppression circuit includes a first Zener diode D1, a second Zener diode D2, a third Zener diode D3, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The first Zener diode D1 is connected between the first output terminal and the second output terminal of the first chip. The cathode of the second Zener diode D2 is connected to the first output terminal of the first chip, and the anode of the second Zener diode D2 is grounded. The negative terminal of the third Zener diode D3 is connected to the second output terminal of the first chip, and the positive terminal of the third Zener diode D3 is grounded. One end of the third resistor R3 is connected to the second output terminal of the first chip. The fourth resistor R4 is connected between the first output terminal and the second output terminal of the first chip. One end of the fifth resistor R5 is connected to the first output terminal of the first chip, and the other end of the fifth resistor R5 is connected to the input terminal of the first MOS transistor circuit. The sixth resistor R6 is connected to the second output terminal of the first chip, and the other end of the sixth resistor R6 is connected to the input terminal of the second MOS transistor circuit.

[0011] In some implementations, the output harness is provided with a first power input terminal, the main control chip U0 is provided with a main control chip U0 power terminal and a first main control power output terminal, and an isolation circuit is provided between the first power input terminal and the main control chip U0 power terminal. The first main control power supply output terminal is equipped with a step-down circuit, which reduces the voltage at the first main control power supply output terminal and outputs a low voltage through the second main control power supply output terminal.

[0012] In some implementations, the first MOSFET circuit includes a first MOSFET, a seventh resistor R7, and an eighth resistor R8; The gate of the first MOSFET is connected to one end of the seventh resistor R7, the output terminal of the second main control power supply is connected to the other end of the seventh resistor R7, the source of the first MOSFET is the input terminal of the first MOSFET circuit, the drain of the first MOSFET is connected to the receiving wire harness, and the eighth resistor R8 is connected between the source and drain of the first MOSFET. The second MOSFET circuit includes a second MOSFET, a ninth resistor R9, and a tenth resistor R10; the main control chip U0 is provided with a first power output terminal; The gate of the second MOSFET is connected to one end of the ninth resistor R9, the output terminal of the second main control power supply is connected to the other end of the ninth resistor R9, the source of the first MOSFET is the input terminal of the second MOSFET circuit, the drain of the second MOSFET is connected to the receiving harness, and the tenth resistor R10 is connected between the source and drain of the second MOSFET.

[0013] In some implementations, the output harness includes a first UART signal input terminal and a second UART signal input terminal; The communication module is configured as a UART module, which includes a UART signal chip U2 and a UART signal conversion circuit. The first UART signal input terminal and the second UART signal input terminal output UART signals to the UART signal chip U2. The UART signal chip U2 and the UART signal conversion circuit convert the UART signals to the second communication signal, and the UART signal chip U2 transmits the second communication signal to the main control chip U0.

[0014] In some implementations, the output harness includes a first I2C signal input terminal and a second I2C signal input terminal; The communication module is configured as an I2C module, which includes an I2C signal chip U3 and an I2C signal conversion circuit. The first I2C signal input terminal and the second I2C signal input terminal output I2C signals to the I2C signal chip U3. The I2C signal chip U3 and the I2C signal conversion circuit convert the I2C signals to the second communication signal, and the I2C signal chip U3 transmits the second communication signal to the main control chip U0.

[0015] In some implementations, the output harness includes a first CAN signal input terminal and a second CAN signal input terminal; The communication module is set as a CAN module, which includes a CAN signal chip and a CAN signal conversion circuit. The first CAN signal input terminal and the second CAN signal input terminal output CAN signals to the CAN signal chip. The CAN signal chip and the CAN signal conversion circuit convert the CAN signal to the second communication signal, and the CAN signal chip transmits the second communication signal to the main control chip U0.

[0016] In some implementations, the output harness includes a first single-wire compatible signal input terminal and a second single-wire compatible signal input terminal; The communication module is configured as a single-wire compatible module, which includes a single-wire compatible signal chip U6 and a single-wire compatible signal conversion circuit. The first and second single-wire compatible signal input terminals output single-wire compatible signals to the single-wire compatible signal chip U6. The single-wire compatible signal chip U6 and the single-wire compatible signal conversion circuit convert the single-wire compatible signal to the second communication signal, and the single-wire compatible signal chip U6 transmits the second communication signal to the main control chip U0.

[0017] The beneficial effects of this utility model's multi-communication test circuit are: By placing a multi-communication test circuit between the aging equipment and the aging component, the aging equipment is equipped with an output wiring harness, and the aging component is equipped with a receiving wiring harness. The multi-communication test circuit includes a main control module with a main control chip, the main control chip having at least one communication receiver and at least one communication output; at least one communication module with a first receiver and a first output, the first receiver being connected to the output wiring harness to receive a first communication signal, and the first output being connected to the communication receiver to convert the first communication signal into a second communication signal and send it to the main control chip; and a communication conversion module, placed between the communication output and the aging component, to convert the signal from the communication output into a third communication signal and send the third communication signal to the aging component via the receiving wiring harness. This allows the aging equipment to adapt to communication modules with different protocols through the main control chip and the communication conversion module, thereby avoiding the need for multiple aging equipment sets to adapt to different aging components. Attached Figure Description

[0018] Figure 1 The structure of the multi-communication test circuit of this utility model Figure 1 ; Figure 2 This is a structural diagram of the communication conversion module of the multi-communication test circuit of this utility model; Figure 3 This is a circuit diagram of Embodiment 1 of the multi-communication test circuit of this utility model; Figure 4 This is a circuit diagram of the output harness of the multi-communication test circuit of this utility model; Figure 5 The structure of the multi-communication test circuit of this utility model Figure 2 ; Figure 6 This is a structural diagram of the UART module of the multi-communication test circuit of this utility model; Figure 7 This is a structural diagram of the I2C module of the multi-communication test circuit of this utility model; Figure 8 This is a structural diagram of the CAN module of the multi-communication test circuit of this utility model; Figure 9 This is a structural diagram of the single-wire compatibility module of the multi-communication test circuit of this utility model.

[0019] Figure label: 1. Aging equipment; 21. Communication module; 22. Main control chip; 23. Communication conversion module; 231. First chip circuit; 232. Transient suppression circuit; 233. First MOSFET circuit; 234. Second MOSFET circuit; 211. UART module; 212. I2C module; 213. CAN module; 214. Single-wire compatible module; 3. Aging parts. Detailed Implementation

[0020] It should be noted that, in the absence of conflict, the embodiments and technical features in the embodiments of this utility model can be combined with each other. The detailed description in the specific embodiments should be understood as an explanation of the spirit of this utility model and should not be regarded as an improper limitation of this utility model.

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the specific technical solutions of this utility model will be further described in detail below with reference to the accompanying drawings of the embodiments of this utility model. The following embodiments are used to illustrate this utility model, but are not intended to limit the scope of this utility model.

[0022] In the embodiments of this utility model, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this utility model, unless otherwise stated, "a plurality of" means two or more.

[0023] Furthermore, in this embodiment of the invention, directional terms such as "upper," "lower," "left," and "right" are defined relative to the positions of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the position of the components in the accompanying drawings.

[0024] In the embodiments of this utility model, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0025] In embodiments of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0026] In this embodiment of the invention, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this embodiment of the invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant information in a specific manner.

[0027] Example 1 like Figures 1-4 As shown, this utility model proposes a multi-communication test circuit, which is disposed between the aging device 1 and the aging component 3. The aging device 1 is provided with an output wiring harness, and the aging component 3 is provided with a receiving wiring harness. The multi-communication test circuit includes: The main control module is equipped with a main control chip U022, which has at least one communication receiver and at least one communication output. At least one communication module 21 is provided with a first receiving end and a first output end. The first receiving end is connected to an output harness to receive a first communication signal, and the first output end is connected to the communication receiving end to convert the first communication signal to a second communication signal and send it to the main control chip U022; and The communication conversion module 23 is located between the communication output terminal and the aging component 3 to convert the signal of the communication output terminal into a third communication signal and send the third communication signal to the aging component 3 through the receiving wire harness.

[0028] Specifically, the multi-communication test circuit can be understood as a switching circuit between the aging device 1 and the aging component 3, enabling the aging device 1 to adapt to aging tests that require different communication protocols, such as I2C, single-wire compatibility, UART, and CAN. Multiple communication modules 21 are used to adapt to different communication protocols, so that when the aging device 1 performs tests using different protocols, the corresponding communication module 21 converts the communication protocol into a unified second communication signal recognizable by the main control chip U022. In some preferred embodiments, this is typically a UART signal, allowing the main control chip U022 to recognize the signal and convert the recognized second communication signal into a third communication signal recognizable by the aging component 3, enabling the aging component 3 to perform the aging test. In some preferred embodiments, the third communication signal can be an RS485 signal.

[0029] By placing a multi-communication test circuit between the aging device 1 and the aging component 3, the aging device 1 is equipped with an output wiring harness, and the aging component 3 is equipped with a receiving wiring harness. The multi-communication test circuit includes a main control module with a main control chip U022, which has at least one communication receiving end and at least one communication output end; at least one communication module 21 with a first receiving end and a first output end, the first receiving end being connected to the output wiring harness to receive a first communication signal, and the first output end being connected to the communication receiving end to convert the first communication signal into a second communication signal and send it to the main control chip U022; and a communication conversion module 23, placed between the communication output end and the aging component 3, to convert the signal from the communication output end into a third communication signal and send the third communication signal to the aging component 3 through the receiving wiring harness. This allows the aging device 1 to adapt to communication modules 21 with different protocols through the main control chip U022 and the communication conversion module 23, thereby avoiding the need to use multiple sets of aging devices 1 to adapt to different aging components 3.

[0030] In some embodiments, the communication conversion module 23 includes a first chip circuit 231, a transient suppression circuit 232, a first MOS transistor circuit 233, and a second MOS transistor circuit 234; The input terminal of the first chip circuit 231 is connected to the communication output terminal. The output terminal of the first chip circuit 231 includes a third output terminal and a fourth output terminal. The third output terminal is connected to the input terminal of the first MOS transistor circuit 233, and the fourth output terminal is connected to the input terminal of the second MOS transistor circuit 234. The transient suppression circuit 232 is disposed between the third output terminal and the fourth output terminal. The output terminals of the first MOS transistor circuit 233 and the second MOS transistor circuit 234 are connected to the receiving harness to send the second communication signal to the aging device 3.

[0031] Specifically, the communication conversion module 23 includes a first chip circuit 231, a transient suppression circuit 232, a first MOSFET circuit 233, and a second MOSFET circuit 234. In some preferred embodiments, the first chip circuit 231 is a chip that converts the UART protocol to the RS485 protocol and its peripheral circuitry. The transient suppression circuit 232 enables bidirectional transient suppression. In a preferred embodiment, the RS485 protocol has A and B connection ports. The first MOSFET circuit 233 and the second MOSFET circuit 234 can respectively control the transmission of the third communication signal from ports A and B to the aging device 3. In some embodiments, the first chip circuit 231 includes a first chip U1, a first resistor R1, and a second resistor R2; The first chip U1 includes a first input terminal U1_DI, a second input terminal U1_RO, a first output terminal U1_A, and a second output terminal U1_RO; the main control chip U022 includes a first communication output terminal U0_31 and a second communication output terminal U0_30. The first input terminal U1_DI of the first chip is connected to the first communication output terminal U0_31 through the first resistor R1. The second input terminal U1_RO of the first chip is connected to the second communication output terminal U0_30 through the second resistor R2. The first output terminal U1_A of the first chip is connected to the input terminal of the first MOS transistor circuit 233. The second output terminal U1_RO of the first chip is connected to the input terminal of the second MOS transistor circuit 234.

[0032] Specifically, the first chip U1 can be a TP8485E, which converts UART signals to RS485 signals. It also includes a first resistor R1 and a second resistor R2. The first input terminal U1_DI of the first chip is connected to the first communication output terminal U0_31 through the first resistor R1, and the second input terminal U1_RO of the first chip is connected to the second communication output terminal U0_30 through the second resistor R2. The first resistor R1 is typically 100Ω, and the second resistor R2 is also typically 100Ω. The main control chip U022 includes a first communication output terminal U0_31 and a second communication output terminal U0_30, which are dual-channel signals converted from UART signals. Preferably, the first communication output terminal U0_31 is RS485A and the second communication output terminal U0_30 is RS485B. The first output terminal U1_A of the first chip is connected to the input terminal of the first MOS transistor circuit 233, and the second output terminal U1_RO of the first chip is connected to the input terminal of the second MOS transistor circuit 234. The output of the control signal is controlled by the first MOS transistor circuit 233 and the second MOS transistor circuit 234 respectively.

[0033] In some preferred embodiments, the first chip U1 further includes a first enable terminal U1_DE, a second enable terminal U1_RE, a first input power terminal U1_VCC, and a first ground terminal U1_GND. The first enable terminal U1_DE and the second enable terminal U1_RE are connected. The first enable terminal U1_DE is connected to the main control chip U022 through an eleventh resistor R11. The eleventh resistor R11 is used for current limiting protection and can usually be selected as 100R. A twelfth resistor R12 can also be provided. One end of the twelfth resistor R12 is connected to one end of the eleventh resistor R11, and the other end of the twelfth resistor R12 is grounded. The twelfth resistor R12 can be 10K. The first input power terminal U1_VCC and the first input terminal U1_DI of the first chip can be connected via a thirteenth resistor R13, which can be 10KΩ. Multiple grounding capacitors can be provided between the first input power terminal U1_VCC and the first input terminal U1_DI of the first chip to prevent signal interference. In optional embodiments, this can include a first capacitor C1, a second capacitor C2, and a third capacitor C3, with values ​​of 0.1uF, 0.1uF, and 22uF, respectively. In other optional embodiments, multiple pull-up resistors can also be provided between the first input power terminal U1_VCC and the first input terminal U1_DI of the first chip. For example, a fourteenth resistor R14 is connected to 3.3V, and a fifteenth resistor R15 is connected to the chip's power supply terminal. The fourteenth resistor R14 is 10R, and the fifteenth resistor R15 can also be 10R or NC to power the chip. The first input power terminal U1_VCC and the second communication output terminal U0_30 can be connected via a sixteenth resistor R16, which can be 1.2KΩ.

[0034] In some embodiments, the transient suppression circuit 232 includes a first Zener diode D1, a second Zener diode D2, a third Zener diode D3, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The first Zener diode D1 is connected between the first output terminal U1_A and the second output terminal U1_RO of the first chip. The cathode of the second Zener diode D2 is connected to the first output terminal U1_A of the first chip, and the anode of the second Zener diode D2 is grounded. The negative terminal of the third Zener diode D3 is connected to the second output terminal U1_RO of the first chip, and the positive terminal of the third Zener diode D3 is grounded. One end of the third resistor R3 is connected to the second output terminal U1_RO of the first chip. The fourth resistor R4 is connected between the first output terminal U1_A and the second output terminal U1_RO of the first chip. One end of the fifth resistor R5 is connected to the first output terminal U1_A of the first chip, and the other end of the fifth resistor R5 is connected to the input terminal of the first MOS transistor circuit 233. The sixth resistor R6 is connected to the second output terminal U1_RO of the first chip, and the other end of the sixth resistor R6 is connected to the input terminal of the second MOS transistor circuit 234.

[0035] Specifically, the first Zener diode D1 can be SMAJ12CA, 12V; the second Zener diode D2, the third Zener diode D3, the fourth resistor R4 for protection can be 120Ω; the fifth resistor R5 and the sixth resistor R6 are adapter resistors and can also be 120Ω. In some optional embodiments, a seventeenth resistor R17 may also be included. One end of the seventeenth resistor R17 is connected to the second output terminal U1_RO of the first chip, and the other end of the seventeenth resistor R17 is grounded.

[0036] In some embodiments, the output harness is provided with a first power input terminal, the main control chip U022 is provided with a main control chip U022 power terminal and a first main control power output terminal, and an isolation circuit is provided between the first power input terminal and the main control chip U022 power terminal. The first main control power supply output terminal is equipped with a step-down circuit, which reduces the voltage at the first main control power supply output terminal and outputs a low voltage through the second main control power supply output terminal.

[0037] Specifically, the output harness is equipped with a first power input terminal for supplying power to the chip and some special first communication modules 21. The main control chip U022 is equipped with a main control chip U022 power supply terminal and a first main control power output terminal. An isolation circuit is provided between the first power input terminal and the main control chip U022 power supply terminal. In some optional embodiments, the isolation circuit can be a combination of TPS7933 and E0505FS-1W. The first power input terminal of the output harness is input to the isolation circuit, and the power is output to the main control chip U022 power supply terminal through the isolation circuit, thereby achieving isolation between the first power input terminal and the main control chip U022 power supply terminal. This circuit can isolate the aging device 1 and the two ends of the multi-communication test circuit, avoiding electrical interference.

[0038] Simultaneously, the chip supplies power to external circuits via the first main control power output terminal. This first main control power output terminal can be selected as 5V and includes a step-down circuit. This circuit reduces the voltage at the first main control power output terminal, optionally using an E0505FS-1W chip to step down the 5V to 3.3V. A lower voltage is then output via the second main control power output terminal.

[0039] In some embodiments, the first MOSFET circuit 233 includes a first MOSFET Q1, a seventh resistor R7, and an eighth resistor R8; The gate of the first MOSFET Q1 is connected to one end of the seventh resistor R7, the output terminal of the second main control power supply is connected to the other end of the seventh resistor R7, the source of the first MOSFET Q1 is the input terminal of the first MOSFET circuit 233, the drain of the first MOSFET Q1 is connected to the receiving wire harness, and the eighth resistor R8 is connected between the source and drain of the first MOSFET Q1. The second MOSFET circuit 234 includes a second MOSFET Q2, a ninth resistor R9, and a tenth resistor R10; the main control chip U022 is provided with a first power output terminal; The gate of the second MOSFET Q2 is connected to one end of the ninth resistor R9, the output terminal of the second main control power supply is connected to the other end of the ninth resistor R9, the source of the first MOSFET Q1 is the input terminal of the second MOSFET circuit 234, the drain of the second MOSFET Q2 is connected to the receiving wire harness, and the tenth resistor R10 is connected between the source and drain of the second MOSFET Q2.

[0040] Specifically, the first MOSFET Q1 and the second MOSFET Q2 can be AQ3402, the seventh resistor R7 and the ninth resistor R9 can be 2K, and the tenth resistor R10 and the eighth resistor R8 can also be 2K or NC.

[0041] Example 2: like Figure 6 As shown, this embodiment proposes an implementation method for a communication module 21, which includes: In some embodiments, the output harness includes a first UART signal input terminal U2_VIA and a second UART signal input terminal U2_VOB; The communication module 21 is configured as a UART module 211, which includes a UART signal chip U2 and a UART signal conversion circuit. The first UART signal input terminal U2_VIA and the second UART signal input terminal U2_VOB output UART signals to the UART signal chip U2. The UART signal chip U2 and the UART signal conversion circuit convert the UART signals to the second communication signal, and the UART signal chip U2 transmits the second communication signal to the main control chip U022.

[0042] Specifically, in some embodiments, the output harness includes a first UART signal input terminal U2_VIA and a second UART signal input terminal U2_VOB for inputting UART signals. The communication module 21 includes a UART signal chip U2 and a UART signal conversion circuit. The UART signal chip U2 is preferably a π121M31 and peripheral circuitry for converting signals. The π121M31 chip includes at least a first UART chip input terminal and a second UART chip input terminal, and may also include a first UART chip output terminal and a second UART chip output terminal for connecting to the main control chip U022 and transmitting the converted second communication signal.

[0043] Example 3: like Figure 7 As shown, this embodiment proposes an implementation method for a communication module 21, which includes: In some embodiments, the output harness includes a first I2C signal input terminal U3_SDA2 and a second I2C signal input terminal U3_SCL2; The communication module 21 is configured as an I2C module 212, which includes an I2C signal chip U3 and an I2C signal conversion circuit. The first I2C signal input terminal U3_SDA2 and the second I2C signal input terminal U3_SCL2 output I2C signals to the I2C signal chip U3. The I2C signal chip U3 and the I2C signal conversion circuit convert the I2C signals to the second communication signal, and the I2C signal chip U3 transmits the second communication signal to the main control chip U022.

[0044] Specifically, in some embodiments, the output harness includes a first I2C signal input terminal U3_SDA2 and a second I2C signal input terminal U3_SCL2 for inputting I2C signals. The communication module 21 includes an I2C signal chip U3 and an I2C signal conversion circuit. The I2C signal chip U3 can be a π220N31 and peripheral circuitry for converting signals. The π220N31 includes at least a first I2C chip input terminal and a second I2C chip input terminal, and may also include a first I2C chip output terminal and a second I2C chip output terminal for connecting to the main control chip U022 and transmitting the converted second communication signal.

[0045] Example 4: like Figure 8 As shown, this embodiment proposes an implementation method for a communication module 21, which includes: In some embodiments, the output harness includes a first CAN signal input terminal U4_CANH and a second CAN signal input terminal U4_CANL; The communication module 21 is configured as a CAN module 213, which includes a CAN signal chip and a CAN signal conversion circuit. The first CAN signal input terminal U4_CANH and the second CAN signal input terminal U4_CANL output CAN signals to the CAN signal chip. The CAN signal chip and the CAN signal conversion circuit convert the CAN signal to the second communication signal, and the CAN signal chip transmits the second communication signal to the main control chip U022.

[0046] Specifically, in some embodiments, the output harness includes a first CAN signal input terminal U4_CANH and a second CAN signal input terminal U4_CANL for inputting CAN signals. The communication module 21 includes a CAN signal chip and a CAN signal conversion circuit. The CAN signal chip may include a second chip U4 and a third chip U5. The second chip U4 may be a TJA1051T, and the third chip U5 may be a combination of π221M31. There are also peripheral circuits for converting signals using TJA1051T and π221M31. TJA1051T includes at least a first CAN chip input terminal and a second CAN chip input terminal. π221M31 includes a first CAN chip output terminal and a second CAN chip output terminal for connecting to the main control chip U022. TJA1051T is used to receive CAN signals and convert them into a model that π221M31 can recognize. π221M31 then converts the signals into a second communication signal for the main control chip U022.

[0047] Example 5: like Figure 9 As shown, this embodiment proposes an implementation method for a communication module 21, which includes: In some embodiments, the output harness includes a first single-wire compatible signal input terminal U6_4 and a second single-wire compatible signal input terminal U6_3; The communication module 21 is configured as a single-wire compatible module 214, which includes a single-wire compatible signal chip U6 and a single-wire compatible signal conversion circuit. The first single-wire compatible signal input terminal U6_4 and the second single-wire compatible signal input terminal U6_3 output single-wire compatible signals to the single-wire compatible signal chip U6. The single-wire compatible signal chip U6 and the single-wire compatible signal conversion circuit convert the single-wire compatible signal to the second communication signal, and the single-wire compatible signal chip U6 transmits the second communication signal to the main control chip U022.

[0048] Specifically, in some embodiments, the output harness includes a first single-wire compatible signal input terminal U6_4 and a second single-wire compatible signal input terminal U6_3 for inputting single-wire compatible signals. The communication module 21 includes a single-wire compatible signal chip U6 and a single-wire compatible signal conversion circuit. The single-wire compatible signal chip U6 can be EL357NB-TA-G, and peripheral circuitry for converting signals using EL357NB-TA-G is also included. EL357NB-TA-G includes at least a first single-wire compatible chip input terminal and a second single-wire compatible chip input terminal. EL357NB-TA-G also includes a first single-wire compatible chip output terminal and a second single-wire compatible chip output terminal for connecting to the main control chip U022. EL357NB-TA-G is used to receive single-wire compatible signals and converts the signals into a second communication signal for the main control chip U022.

[0049] like Figure 5 As shown, it should be noted that Embodiments 2 to 5 can be combined or arranged. The main control chip U022 detects the input of each protocol and converts it into a recognizable second communication signal, which is then sent to the aging component 3. The communication module 21 includes, but is not limited to, CAN module 213, I2C module 212, UART module 211, and single-wire compatible module 214. It may also include RS485 module, some / ip, and other test modules used in aging tests.

[0050] The serial numbers of the utility model embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The above are only preferred embodiments of this utility model and do not limit the patent scope of this utility model. Any equivalent device or equivalent process transformation made based on the content of this utility model specification and drawings, or direct or indirect application in other related technical fields, are similarly included in the patent protection scope of this utility model.

Claims

1. A multi-communication test circuit, characterized in that, The multi-communication test circuit is positioned between the aging equipment and the aging component. The aging equipment is equipped with an output wiring harness, and the aging component is equipped with a receiving wiring harness. The main control module is equipped with a main control chip U0, which has at least one communication receiving end and at least one communication output end. At least one communication module is provided with a first receiving end and a first output end. The first receiving end is connected to the output harness to receive a first communication signal, and the first output end is connected to the communication receiving end to convert the first communication signal into a second communication signal and send it to the main control chip U0; and A communication conversion module is disposed between the communication output terminal and the aging component to convert the signal of the communication output terminal into a third communication signal, and to send the third communication signal to the aging component through the receiving harness.

2. The multi-communication test circuit according to claim 1, characterized in that, The communication conversion module includes a first chip circuit, a transient suppression circuit, a first MOS transistor circuit, and a second MOS transistor circuit; The input terminal of the first chip circuit is connected to the communication output terminal. The output terminal of the first chip circuit includes a third output terminal and a fourth output terminal. The third output terminal is connected to the input terminal of the first MOS transistor circuit, and the fourth output terminal is connected to the input terminal of the second MOS transistor circuit. The transient suppression circuit is disposed between the third output terminal and the fourth output terminal. The output terminals of the first MOS transistor circuit and the second MOS transistor circuit are connected to the receiving harness to send the third communication signal to the aging device.

3. The multi-communication test circuit according to claim 2, characterized in that, The first chip circuit includes a first chip U1, a first resistor R1, and a second resistor R2; The first chip U1 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the main control chip U0 includes a first communication output terminal and a second communication output terminal. The first input terminal of the first chip is connected to the first communication output terminal through the first resistor R1, the second input terminal of the first chip is connected to the second communication output terminal through the second resistor R2, the first output terminal of the first chip is connected to the input terminal of the first MOS transistor circuit, and the second output terminal of the first chip is connected to the input terminal of the second MOS transistor circuit.

4. The multi-communication test circuit according to claim 3, characterized in that, The transient suppression circuit includes a first Zener diode D1, a second Zener diode D2, a third Zener diode D3, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The first Zener diode D1 is connected between the first output terminal and the second output terminal of the first chip. The cathode of the second Zener diode D2 is connected to the first output terminal of the first chip, and the anode of the second Zener diode D2 is grounded. The negative terminal of the third Zener diode D3 is connected to the second output terminal of the first chip, and the positive terminal of the third Zener diode D3 is grounded. One end of the third resistor R3 is connected to the second output terminal of the first chip. The fourth resistor R4 is connected between the first output terminal and the second output terminal of the first chip. One end of the fifth resistor R5 is connected to the first output terminal of the first chip, and the other end of the fifth resistor R5 is connected to the input terminal of the first MOS transistor circuit. The sixth resistor R6 is connected to the second output terminal of the first chip, and the other end of the sixth resistor R6 is connected to the input terminal of the second MOS transistor circuit.

5. The multi-communication test circuit according to claim 3, characterized in that, The output harness is provided with a first power input terminal, the main control chip U0 is provided with a main control chip U0 power terminal and a first main control power output terminal, and an isolation circuit is provided between the first power input terminal and the main control chip U0 power terminal. The first main control power supply output terminal is provided with a step-down circuit, which reduces the voltage of the first main control power supply output terminal and outputs a low voltage through the second main control power supply output terminal.

6. The multi-communication test circuit according to claim 5, characterized in that, The first MOSFET circuit includes a first MOSFET Q1, a seventh resistor R7, and an eighth resistor R8; The gate of the first MOS transistor Q1 is connected to one end of the seventh resistor R7, the output terminal of the second main control power supply is connected to the other end of the seventh resistor R7, the source of the first MOS transistor Q1 is the input terminal of the first MOS transistor circuit, the drain of the first MOS transistor Q1 is connected to the receiving harness, and the eighth resistor R8 is connected between the source and drain of the first MOS transistor Q1. The second MOS transistor circuit includes a second MOS transistor Q2, a ninth resistor R9, and a tenth resistor R10; the main control chip U0 is provided with a first power output terminal; The gate of the second MOS transistor Q2 is connected to one end of the ninth resistor R9, the output terminal of the second main control power supply is connected to the other end of the ninth resistor R9, the source of the first MOS transistor Q1 is the input terminal of the second MOS transistor circuit, the drain of the second MOS transistor Q2 is connected to the receiving harness, and the tenth resistor R10 is connected between the source and drain of the second MOS transistor Q2.

7. The multi-communication test circuit according to claim 1, characterized in that, The output harness includes a first UART signal input terminal and a second UART signal input terminal; The communication module is configured as a UART module, which includes a UART signal chip U2 and a UART signal conversion circuit. The first UART signal input terminal and the second UART signal input terminal output UART signals to the UART signal chip U2. The UART signal chip U2 and the UART signal conversion circuit convert the UART signal to the second communication signal, and the UART signal chip U2 transmits the second communication signal to the main control chip U0.

8. The multi-communication test circuit according to claim 1, characterized in that, The output harness includes a first I2C signal input terminal and a second I2C signal input terminal; The communication module is configured as an I2C module, which includes an I2C signal chip U3 and an I2C signal conversion circuit. The first I2C signal input terminal and the second I2C signal input terminal output I2C signals to the I2C signal chip U3. The I2C signal chip U3 and the I2C signal conversion circuit convert the I2C signals to the second communication signal, and the I2C signal chip U3 transmits the second communication signal to the main control chip U0.

9. The multi-communication test circuit according to claim 1, characterized in that, The output harness includes a first CAN signal input terminal and a second CAN signal input terminal; The communication module is configured as a CAN module, which includes a CAN signal chip and a CAN signal conversion circuit. The first CAN signal input terminal and the second CAN signal input terminal output CAN signals to the CAN signal chip. The CAN signal chip and the CAN signal conversion circuit convert the CAN signal to the second communication signal, and the CAN signal chip transmits the second communication signal to the main control chip U0.

10. The multi-communication test circuit according to claim 1, characterized in that, The output harness includes a first single-wire compatible signal input terminal and a second single-wire compatible signal input terminal; The communication module is configured as a single-line compatible module, which includes a single-line compatible signal chip U6 and a single-line compatible signal conversion circuit. The first single-wire compatible signal input terminal and the second single-wire compatible signal input terminal output single-wire compatible signals to the single-wire compatible signal chip U6. The single-wire compatible signal chip U6 and the single-wire compatible signal conversion circuit convert the single-wire compatible signal to the second communication signal, and the single-wire compatible signal chip U6 transmits the second communication signal to the main control chip U0.

Images