A stacked capacitor and semiconductor device

Abstract

This application provides a stacked capacitor and a semiconductor device. The stacked capacitor includes a base dielectric layer, alternating stacked multilayer conductive layers and multilayer spacer dielectric layers, a top dielectric layer, first and second connecting holes, and first and second conductive structures; the odd-numbered conductive layers are made of different materials than the even-numbered conductive layers; the top dielectric layer is disposed on the side of the multilayer conductive layers and multilayer spacer dielectric layers facing away from the base dielectric layer; a first insulating layer is formed on the hole wall of each odd-numbered conductive layer; the first conductive structure is at least partially located in the first connecting hole and is electrically connected to each even-numbered conductive layer, and is electrically isolated from each odd-numbered conductive layer by the first insulating layer; a second insulating layer is formed on the hole wall of each even-numbered conductive layer; the second conductive structure is at least partially located in the second connecting hole and is electrically connected to each odd-numbered conductive layer, and is electrically isolated from each even-numbered conductive layer by the second insulating layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a stacked capacitor and semiconductor device. Background Technology

[0002] Capacitors are common and important passive electronic components in integrated circuits. Common capacitors include metal-oxide-semiconductor (MOS) capacitors, PN junction capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and metal-insulator-metal (MIM) capacitors. MIM capacitors are typically formed on a metal interconnect structure in the back-end of line (BEOL) process. This increases the distance between the MIM capacitor and the silicon substrate, thereby reducing the parasitic capacitance between the MIM capacitor and the substrate. Furthermore, the performance of MIM capacitors is less affected by frequency and temperature. In addition, MIM capacitors are formed during the metal interconnect process, making the MIM formation process compatible with existing integrated circuit technologies. Therefore, MIM capacitors have gradually become the mainstream type of passive capacitor. As Moore's Law continues to evolve, the requirements for capacitor density in integrated circuits are becoming increasingly stringent. This is particularly evident in high-performance chips such as CPUs, GPUs, and FPGAs; mobile chips including 5G modems, system-on-a-chip (SoC), power management chips (PMICs), and 2.5D / 3D chiplets, where there is a significant demand for high-density capacitors. Currently, a major mainstream structure for achieving high-density capacitors is stacked capacitors. Improving the performance of stacked capacitors has become a major focus. Summary of the Invention

[0003] This application provides a stacked capacitor, which includes: Base dielectric layer; The system comprises multiple conductive layers and multiple spacer dielectric layers stacked alternately on a base dielectric layer. In each conductive layer, from the conductive layer closest to the base dielectric layer towards the conductive layer farthest from the base dielectric layer, the multiple conductive layers include alternating odd-numbered and even-numbered conductive layers. All odd-numbered conductive layers are made of the same material, and all even-numbered conductive layers are made of the same material. The odd-numbered conductive layers and even-numbered conductive layers in the multiple conductive layers are made of different materials. A top dielectric layer is disposed on the side of the multilayer conductive layer and the multilayer spacer dielectric layer that is away from the base dielectric layer; A first connecting hole penetrates the top dielectric layer, all conductive layers, and spacer dielectric layers; wherein a first insulating layer is formed on the hole wall of each odd-numbered conductive layer. A first conductive structure, at least partially located in the first connecting hole, electrically connected to each even-numbered conductive layer, and electrically isolated from each odd-numbered conductive layer by a first insulating layer; The second connection hole penetrates the top dielectric layer, all conductive layers and the spacer dielectric layer, and is spaced apart from the first connection hole; wherein, a second insulating layer is formed on the hole wall of each even-numbered conductive layer; The second conductive structure is at least partially located in the second connection hole and is electrically connected to each odd-numbered conductive layer, and electrically isolated from each even-numbered electrically connected layer by the second insulating layer.

[0004] In some embodiments, the thickness of the conductive layer is 10 nm to 100 nm; The thickness of the spacer dielectric layer is 5nm-50nm.

[0005] In some embodiments, the material of the odd-numbered conductive layers is selected from aluminum, titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, citriium, molybdenum, and hafnium; The even-numbered conductive layers are selected from aluminum, titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, citric acid, molybdenum, and hafnium.

[0006] In some embodiments, each conductive layer is a flat film layer; Each spacer dielectric layer is a flat film.

[0007] In some embodiments, the first insulating layer is a passivation layer, or the first insulating layer is a halogenated layer.

[0008] In some embodiments, the second insulating layer is a passivation layer, or the second insulating layer is a halogenation layer.

[0009] In some embodiments, the stacked capacitor includes a first conductive structure and a second conductive structure; or, The stacked capacitor includes multiple sets of first conductive structures and second conductive structures, wherein each set of first conductive structures and second conductive structures is arranged along a first direction, and each first conductive structure in the multiple sets of first conductive structures and second conductive structures points in the same direction toward the second conductive structure in its respective set.

[0010] In some embodiments, the first conductive structure includes a first adhesive layer and a first conductive body. The first adhesive layer is attached to the wall of the first connection hole to connect each of the even-numbered conductive layers. The first conductive body fills the first connection hole and is covered by the first adhesive layer. The second conductive structure includes a second adhesive layer and a second conductive body. The second adhesive layer is attached to the wall of the second connection hole to connect the odd-numbered conductive layers. The second conductive body fills the second connection hole and is covered by the second adhesive layer.

[0011] This application also provides a semiconductor device comprising stacked capacitors as described above.

[0012] In some embodiments, the semiconductor device further includes a chip, and the stacked capacitors are disposed outside the chip or inside the chip.

[0013] The main technical effects achieved by the embodiments of this application are: The stacked capacitor and semiconductor device provided in this application embodiment form odd-numbered and even-numbered conductive layers that are alternately stacked with each spacer dielectric layer using metal materials of different conductive materials. A first insulating layer is provided on the wall of the first connection hole of each odd-numbered conductive layer, and a first conductive structure is provided at least partially located in the first connection hole, so that it is electrically connected to each even-numbered conductive layer and electrically isolated from each odd-numbered conductive layer by the first insulating layer. Similarly, a second insulating layer is provided on the wall of the second connection hole of each even-numbered conductive layer, and a second conductive structure is provided at least partially located in the second connection hole, so that the second conductive structure is electrically connected to each odd-numbered conductive layer and electrically isolated from each even-numbered conductive layer by the second insulating layer. Compared to the method that requires staggering the odd-numbered and even-numbered conductive layers to provide separate areas for each conductive structure, the above-described stacked capacitor fabrication method eliminates the need for patterning each conductive layer, which helps reduce production costs, improve production efficiency, and increase the area ratio of the conductive layers, thereby increasing capacitance density. Attached Figure Description

[0014] Figure 1 This is a flowchart illustrating a method for fabricating a stacked capacitor according to an exemplary embodiment of this application; Figures 2 to 25 These are structural diagrams corresponding to different processes used in fabricating stacked capacitors using an exemplary embodiment of this application. Figure 26 This is a top view of a stacked capacitor provided in an exemplary embodiment of this application; Figure 27 It is along Figure 26 The cross-sectional view of the stacked capacitors obtained by section line AA shown. Detailed Implementation

[0015] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0016] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture; if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0017] The following is in conjunction with the appendix Figures 1 to 27 The following describes some embodiments of this application in detail. Unless otherwise specified, the embodiments and features described below can be combined with each other.

[0018] Please refer to Figure 1 This application provides a method for fabricating stacked capacitors, which includes the following steps S10 to S70: In step S10, a base dielectric layer is provided; In step S20, multiple conductive layers and multiple spacer dielectric layers are formed on the base dielectric layer, with the multiple conductive layers and multiple spacer dielectric layers stacked alternately; in each conductive layer, from the conductive layer closest to the base dielectric layer to the conductive layer farthest from the base dielectric layer, the multiple conductive layers include alternating odd-numbered conductive layers and even-numbered conductive layers; all odd-numbered conductive layers are made of the same material, and all even-numbered conductive layers are made of the same material; the odd-numbered conductive layers and even-numbered conductive layers in the multiple conductive layers are made of different materials; In step S30, a top dielectric layer is provided, which is disposed on the side of the multilayer conductive layer and the multilayer spacer dielectric layer away from the base dielectric layer; In step S40, a first connection hole is formed, and a first insulating layer is formed on the hole wall of each odd-numbered conductive layer; wherein, the first connection hole penetrates the top dielectric layer, all conductive layers, and the spacer dielectric layer; In step S50, a first conductive structure is formed, which is at least partially located in the first connecting hole and is electrically connected to each even-numbered conductive layer and electrically isolated from each odd-numbered conductive layer by a first insulating layer. In step S60, a second connection hole is formed, and a second insulating layer is formed on the hole wall of each even-numbered conductive layer; wherein the second connection hole penetrates the top dielectric layer, all conductive layers and spacer dielectric layers, and is spaced apart from the first connection hole; In step S70, a second conductive structure is formed, which is at least partially located in the second connecting hole and is electrically connected to each odd-numbered conductive layer and electrically isolated from each even-numbered electrically connected layer by the second insulating layer.

[0019] The following is combined with Figures 2 to 25 Taking a 4-layer conductive layer as an example, the fabrication method of the above-mentioned stacked capacitor will be described in detail. It is understood that the conductive layer can also be multiple layers, such as 3, 5, 6, 7, 8 layers, etc.

[0020] Combination Figure 2 and Figure 3 As shown, in step S10, a base dielectric layer 001 is provided.

[0021] The base dielectric layer 001 can be made of low-k dielectric material (low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride or silicon oxynitride, etc., to provide a platform for the subsequent manufacturing of stacked capacitors (and MIM stacked capacitors).

[0022] It is understood that the stacked capacitor can be a capacitor structure formed inside the chip or on the chip surface. In the implementation where the stacked capacitor is formed inside the chip or on the chip surface, the base dielectric layer 001 can also be used to isolate the previous metal interconnect structure in the back-end of line (BEOL) process, that is, to electrically isolate the stacked capacitor from the chip.

[0023] The base dielectric layer 001 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and other methods.

[0024] Combination Figures 2 to 9As shown, in step S20, a first conductive layer 101, a second conductive layer 103, a third conductive layer 105, a fourth conductive layer 107, and a first spacer dielectric layer 102, a second spacer dielectric layer 104, and a third spacer dielectric layer 106 are formed on the base dielectric layer 001. The first conductive layer 101, the second conductive layer 103, the third conductive layer 105, the fourth conductive layer 107, and the first spacer dielectric layer 102, the second spacer dielectric layer 104, and the third spacer dielectric layer 106 are stacked alternately. In each conductive layer, from the first conductive layer 101 closest to the base dielectric layer 001 towards the fourth conductive layer 107 furthest from the base dielectric layer 001, that is, in the capacitor thickness direction z, the first conductive layer 101, the second conductive layer 103, the third conductive layer 105, and the fourth conductive layer 107 include alternating odd-numbered conductive layers (i.e., the first conductive layer 101 and the third conductive layer 105) and even-numbered conductive layers (i.e., the second conductive layer 103 and the fourth conductive layer 107). All odd-numbered conductive layers (i.e., the first conductive layer 101 and the third conductive layer 105) are made of the same material, and all even-numbered conductive layers (i.e., the second conductive layer 103 and the fourth conductive layer 107) are made of the same material. The odd-numbered conductive layers (i.e., the first conductive layer 101 and the third conductive layer 105) in the multilayer conductive layers are made of different materials than the even-numbered conductive layers (i.e., the second conductive layer 103 and the fourth conductive layer 107).

[0025] like Figure 2 and Figure 3 As shown, a first conductive layer 101 is formed on the base dielectric layer 001.

[0026] The first conductive layer 101 can be formed by deposition, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0027] In some embodiments, aluminum is selected as the electrode material for the first conductive layer 101 (i.e., the odd-numbered conductive layer). It is understood that in other embodiments, other etchable metals such as titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, citriium, molybdenum, and hafnium may also be selected as the material for the first conductive layer 101 (i.e., the odd-numbered conductive layer).

[0028] The thickness of the first conductive layer 101 can be 10nm-100nm. For example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm.

[0029] like Figure 4 and Figure 5 As shown, a first spacer dielectric layer 102 is formed on the first conductive layer 101.

[0030] The first spacer dielectric layer 102 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods.

[0031] The material of the first layer spacer dielectric 102 can be any one or a mixture of materials including, but not limited to, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0032] In some embodiments, the thickness of the first layer spacer dielectric 102 can be 5nm-50nm. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0033] like Figure 6 and Figure 7 As shown, a second conductive layer 103 is formed on the first spacer dielectric layer 102, and a second spacer dielectric layer 104 is formed on the second conductive layer 103.

[0034] The second conductive layer 103 can be formed by deposition, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0035] In some embodiments, the thickness of the second conductive layer 103 can be 10nm-100nm. For example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm.

[0036] In some embodiments, Ti is selected as the material of the second conductive layer 103, that is, as the material of the even-numbered electrode layers. Alternatively, in other embodiments, the second conductive layer 103 may be selected as other metallic materials different from the first conductive layer 101, such as including but not limited to titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, zirconia, molybdenum, hafnium, etc., which are etchable.

[0037] The material of the odd-numbered conductive layers can be selected from aluminum, titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, citriium, molybdenum, and hafnium. The material of the even-numbered conductive layers can be selected from aluminum, titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, citriium, molybdenum, and hafnium.

[0038] Understandably, the materials of the odd-numbered conductive layers are different from those of the even-numbered conductive layers. Furthermore, the physicochemical properties of the odd-numbered conductive layers' materials, oxides, and halides must be clearly distinguishable from those of the even-numbered conductive layers. This allows for better design of the subsequent first and second insulating layers.

[0039] The material of the second spacer dielectric layer 104 may be any one or a mixture of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0040] The thickness of the second spacer dielectric layer 104 can be 5nm-50nm. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0041] like Figure 8 and Figure 9 As shown, a third conductive layer 105 is formed on the second spacer dielectric layer 104, a third spacer dielectric layer 106 is formed on the third conductive layer 105, and a fourth conductive layer 107 is formed on the third spacer dielectric layer 106.

[0042] The third conductive layer 105 is an odd-numbered electrode material and uses the same material as the first conductive layer 101.

[0043] The thickness of the third conductive layer 105 is 10nm-100nm. For example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, and 100nm.

[0044] The material of the third spacer dielectric layer 106 may include, but is not limited to, any one or a mixture of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0045] The thickness of the third spacer dielectric layer 106 can be 5nm-50nm. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0046] The fourth conductive layer 107, as an even-numbered electrode material, uses the same material as the second conductive layer 103. The thickness of the fourth conductive layer 107 can be 10nm-100nm, such as 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, and 100nm.

[0047] It is understandable that the thickness of each conductive layer can be the same or different, the thickness of each spacer dielectric layer can be the same or different, and the material of each spacer dielectric layer can be the same or different, which can be set according to specific needs.

[0048] In some embodiments, the thickness of the spacer dielectric layer may be less than the thickness of the conductive layer.

[0049] like Figure 8 and Figure 9 As shown, in step S30, a top dielectric layer 108 is provided. The top dielectric layer 108 is disposed on the side of the multilayer conductive layer and the multilayer spacer dielectric layer opposite to the base dielectric layer 001.

[0050] In this embodiment, the top dielectric layer 108 is disposed on the side of the fourth conductive layer 107 away from the base dielectric layer 001.

[0051] The material of the top dielectric layer 108 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride.

[0052] The top dielectric layer 108 is relatively thick, at least greater than the thickness of a single spacer dielectric layer. The thickness of the top dielectric layer 108 can be greater than the thickness of a single conductive layer.

[0053] For stacked capacitors that are away from the base dielectric layer 001 (which can be understood as the top of the stacked capacitors) and require other metal interconnect structures to be set later, the top dielectric layer 108 can be used to isolate the metal interconnect structures in the back-end of line (BEOL) process on the top of the stacked capacitors.

[0054] like Figures 10 to 13 In step S40, a first connection hole 111 is formed, and a first insulating layer 112 is formed on the hole wall of each odd-numbered conductive layer; wherein, the first connection hole 111 penetrates the top dielectric layer 108, all conductive layers and the spacer dielectric layer.

[0055] Step S40 can be achieved through steps S401 and S402.

[0056] In step S401, a first connecting hole 111 is formed.

[0057] In step S402, a first insulating layer 112 is formed on the hole walls of each odd-numbered conductive layer. like Figure 10 and Figure 11 As shown, in step S401, a first connection hole 111 is formed. The first connection hole 111 penetrates the top dielectric layer 108, the first conductive layer 101, the second conductive layer 103, the third conductive layer 105, the fourth conductive layer 107, and the first spacer dielectric layer 102, the second spacer dielectric layer 104, and the third spacer dielectric layer 106.

[0058] like Figure 11 As shown, the first connection hole 111 can also etch a portion of the base dielectric layer 001 to ensure that all conductive layers are etched through.

[0059] When the first connection hole 111 is formed, the etching depth of the base dielectric layer 001 can be controlled within a few nanometers, such as 5nm, 8nm, 10nm, 12nm, or 15nm.

[0060] Of course, in some other embodiments, the bottom conductive layer may not need to be etched through, or it may be etched just to the surface of the base dielectric layer 001.

[0061] The first connecting hole 111 can be etched by dry etching, physical etching (such as plasma etching using inert gases such as argon), or chemical physical etching using chlorine (Cl)-containing gases.

[0062] It is understandable that the first connecting hole 111 is formed in the same process, such as in the same etching process, without the need for multiple etching processes.

[0063] like Figure 12 and Figure 13 As shown, in step S402, a first insulating layer 112 is formed on the hole walls of the first conductive layer 101 and the third conductive layer 105.

[0064] In some embodiments, step S402, which forms the first insulating layer 112 on the hole wall of each odd-numbered conductive layer, can be achieved through the following steps S4021 and S4022: In step S4021, the hole walls of all conductive layers are processed, with the hole walls of each odd-numbered conductive layer forming a first insulating layer and the hole walls of each even-numbered conductive layer forming a second insulating layer. The first insulating layer is an insulating material layer.

[0065] In step S4022, the second insulating layer on the hole wall of all even-numbered conductive layers is removed, and the first insulating layer on the hole wall of each odd-numbered conductive layer is retained. The first insulating layer serves as the first insulating layer 112.

[0066] Understandably, considering that a small portion of metal oxides are acidic oxides, some are amphoteric oxides, and most are basic oxides, acid-base reactions can be used to remove the second insulating layer. Alternatively, acid / base solutions compatible with the second insulating layer can be used for selective removal of the second insulating layer (metal oxides) from both the first and second insulating layers. For example, we can select two metals, one with amphoteric oxide and the other with basic oxide, respectively. After etching the vias, oxygen is introduced or the metals are immersed in a strong oxidizing agent solution to oxidize them both. Then, sodium hydroxide solution is added to dissolve the amphoteric oxide, leaving the basic oxide. Alternatively, we can select one metal whose oxide is an amphoteric oxide, soluble in dilute strong acid or dilute strong base solutions, and another metal whose oxide is a corrosion-resistant material, insoluble in dilute strong acid or dilute strong base solutions.

[0067] For example, in some embodiments, step S4021 may passivate the hole walls of all conductive layers. The first insulating layer formed on the hole walls of each odd-numbered conductive layer and the second insulating layer formed on the hole walls of each even-numbered conductive layer are both passivation layers formed on each conductive layer, i.e., oxide layers, such as metal oxides.

[0068] Accordingly, after forming a first insulating layer on the hole wall of each odd-numbered conductive layer in step S4021 and forming a second insulating layer on the hole wall of each even-numbered conductive layer, the second insulating layer on the hole wall of all even-numbered conductive layers can be removed in step S4022 by acid-base reaction or redox reaction.

[0069] The acid-base reaction can be performed by using a suitable acidic solution (such as a dilute strong acid, like dilute sulfuric acid or dilute nitric acid) to react with the second insulating layer. Alternatively, a suitable alkaline solution can be used to react with the second insulating layer.

[0070] Redox reactions can be carried out using suitable redox agents, such as hydrogen gas at high temperatures.

[0071] For example, oxygen or other strong oxidizing gases can be introduced to passivate all conductive layers, and then the passivation layer formed on the hole walls of the even-numbered conductive layers can be removed.

[0072] Taking an example where the odd-numbered conductive layers are made of aluminum (Al) and the even-numbered conductive layers are made of titanium (Ti), in step S4021, O2 can be introduced first, and the preset temperature can be controlled as needed to generate a sufficiently thick oxide film on the hole walls of both the odd-numbered and even-numbered conductive layers. Specifically, Al2O3 is formed on the hole walls of the odd-numbered conductive layers, and TiO2 is formed on the sidewalls of the even-numbered conductive layers. Then, in step S4022, fluorine gas can be used for etching. Al2O3 cannot be etched, but TiO2 can be etched, thereby removing the oxide film of the even-numbered conductive layers (Ti) while retaining the oxide film of the odd-numbered conductive layers (Al). That is, in this example, the first insulating layer is micro-alumina.

[0073] For example, in some other embodiments, step S4021 may involve treating the hole walls of all conductive layers by halogenating them. This is achieved by introducing a halogen gas (such as chlorine, bromine, or fluorine) or a halogen-containing compound. A first insulating layer is formed on the hole walls of each odd-numbered conductive layer, and a second insulating layer, also composed of halides, is formed on the hole walls of each even-numbered conductive layer.

[0074] Accordingly, after forming a first insulating layer on the hole wall of each odd-numbered conductive layer in step S4021 and forming a second insulating layer on the hole wall of each even-numbered conductive layer, the second insulating layer on the hole wall of all odd-numbered conductive layers can be removed by heating in step S4022.

[0075] In this embodiment, the boiling point of the second insulating layer on the hole wall of the odd-numbered conductive layers is lower than the boiling point of the first insulating layer on the hole wall of the even-numbered conductive layers. Furthermore, there is a certain temperature difference between their boiling points. For example, the temperature difference can be controlled to be above 50 degrees Celsius, or even hundreds of degrees Celsius. Accordingly, in step S4022, the temperature can be heated to a level higher than the boiling point of the second insulating layer, but lower than the boiling point of the first insulating layer on the hole wall of the even-numbered conductive layers.

[0076] In this embodiment, taking an odd-numbered conductive layer of Ti and an even-numbered conductive layer of Al as an example, bromine gas can be introduced in step S4021. The temperature is controlled according to a preset limit to generate a sufficiently thick halide film on the pore walls of both the odd-numbered and even-numbered conductive layers. Specifically, TiBr3 is formed on the pore walls of the odd-numbered conductive layers, and AlBr3 is formed on the sidewalls of the even-numbered conductive layers. Then, in step S4022, heating can be performed. AlBr3 has a boiling point of approximately 265°C, and TiBr3 has a boiling point of approximately 379°C. Step S4022 can be heated to a temperature between 265°C and 379°C, such as 270°C, 280°C, 290°C, 300°C, or 310°C, to remove the AlBr3. That is, in this embodiment, the first insulating layer is TiBr3.

[0077] In some other embodiments, step S40 may also skip steps S4021 and S4022 to set the first insulating layer 112. Instead, the first insulating layer 112 may be set directly through step S4023.

[0078] In step S4023, only the hole walls of all odd-numbered conductive layers are processed to form the first insulating layer 112.

[0079] For example, in some embodiments, the hole walls of all odd-numbered conductive layers are passivated.

[0080] Considering that only some metals undergo passivation reactions to form oxide films (such as Fe, Al, Cr, Ni, Co, Mo, Ta, Nb, and W, which are passivated by concentrated sulfuric acid), a strong oxidizing solution (such as concentrated sulfuric acid) can be used to passivate the pore walls of all odd-numbered conductive layers. Accordingly, the materials for odd-numbered conductive layers can be selected that can be passivated by a suitable strong oxidizing solution, such as aluminum, while the materials for even-numbered conductive layers can be selected that will not be passivated by a strong oxidizing solution.

[0081] For example, in other embodiments, atomic layer deposition (ALD) of insulating material can be performed on all odd-numbered conductive layers. For instance, if the material of the odd-numbered conductive layers is aluminum and the material of the even-numbered conductive layers is titanium nitride (TiN), atomic layer deposition of aluminum oxide or silicon dioxide can be used to deposit an insulating layer on the hole walls of the odd-numbered conductive layers. That is, in this embodiment, the first insulating layer 112 is the deposited aluminum oxide or silicon dioxide.

[0082] It is understood that each odd-numbered conductive layer in this application uses the same material, which facilitates the formation of the first insulating layer 112 of different conductive layers in the same process.

[0083] like Figures 14 to 17 As shown, in step S50, a first conductive structure is formed. The first conductive structure is at least partially located in the first connecting hole 111 and is electrically connected to each even-numbered conductive layer, and is electrically isolated from each odd-numbered conductive layer by the first insulating layer 112.

[0084] like Figure 14 and Figure 15 As shown, an adhesive layer 113 can be first disposed in the first connecting hole 111 to connect the even-numbered layers. This adhesive layer can be formed by atomic layer deposition (ALD) to achieve good coverage.

[0085] The material of the adhesion layer 113 can be a conductive material with good adhesion, such as Ti, TiN, Ta, TaN, etc. The first adhesion layer 121 can also serve as a seed layer and a barrier layer.

[0086] like Figure 16and Figure 17 As shown, a conductive body 114 is then disposed in the first connection hole 111. The conductive body 114 and the adhesive layer 113 together form the first conductive structure.

[0087] The conductive body 114 can be made of metals such as copper (Cu) and tungsten (W).

[0088] The conductive body 114 can be formed by electroplating a conductive body material onto the adhesion layer 113 and then performing chemical mechanical polishing (CMP) to form a first conductive structure flush with the top dielectric layer 108.

[0089] In other embodiments, the first conductive structure can also be formed by directly filling the conductive body 114.

[0090] like Figures 18 to 21 As shown, in step S60, a second connection hole 121 is formed, and a second insulating layer 122 is formed on the hole wall of each even-numbered conductive layer. The second connection hole 121 penetrates the top dielectric layer 108, all conductive layers, and spacer dielectric layers, and is spaced apart from the first connection hole 111.

[0091] It is understood that the second connecting hole 121 is formed in the same process.

[0092] In step S60, the second connecting hole 121 may be formed in the same or similar manner as the first connecting hole 111 described above. Please refer to the relevant descriptions above, which will not be repeated here.

[0093] In some embodiments, step S60, forming a second insulating layer 122 on the hole wall of each even-numbered conductive layer may include the following steps: The hole walls of all conductive layers are treated, and the hole walls of each odd-numbered conductive layer form a third insulating layer, while the hole walls of each even-numbered conductive layer form a fourth insulating layer. Remove the third insulating layer on the hole walls of all odd-numbered conductive layers and retain the fourth insulating layer on the hole walls of each even-numbered conductive layer, which serves as the second insulating layer 122.

[0094] For example, in some embodiments, processing the hole walls of all conductive layers includes passivating the hole walls of all conductive layers. After forming a third insulating layer on the hole walls of each odd-numbered conductive layer and a fourth insulating layer on the hole walls of each even-numbered conductive layer, the third insulating layer on the hole walls of all odd-numbered conductive layers is removed by acid-base reaction or redox reaction.

[0095] The description of passivation treatment and removal of the third insulating layer on the hole walls of all odd-numbered conductive layers using acid-base reaction or redox reaction in this embodiment can be found in the description of step S402 above, and will not be repeated here.

[0096] For example, in other embodiments, treating the hole walls of all conductive layers includes halogenating the hole walls of all conductive layers. After forming a third insulating layer on the hole walls of each odd-numbered conductive layer and a fourth insulating layer on the hole walls of each even-numbered conductive layer, the third insulating layer on the hole walls of all even-numbered conductive layers is removed by heating.

[0097] The descriptions of halogenation treatment and the removal of the third insulating layer on the hole walls of all even-numbered conductive layers by heating in the embodiments can be found in the descriptions of step S402 above, and will not be repeated here.

[0098] In other embodiments, the second insulating layer 122 can also be formed directly in the following manner. For example, in some embodiments, in each conductive layer, only the hole walls of the even-numbered conductive layers are processed to form the second insulating layer 122.

[0099] In some embodiments, the holes in the even-numbered conductive layers are passivated or atomic layer deposition of insulating material is performed.

[0100] The method of processing only the hole walls of the even-numbered conductive layers to form the second insulating layer 122 is similar to the description of step S4023 above, and can be referred to the description of step S4023 above, which will not be repeated here.

[0101] It should be noted that the first insulating layer 112 and the second insulating layer 122 can be formed using appropriate processes depending on the specific materials of the odd-numbered conductive layers and the even-numbered conductive layers.

[0102] like Figure 22 and Figure 23 As shown, in step S70, a second conductive structure is formed. The second conductive structure is at least partially located in the second connecting hole 121 and is electrically connected to each odd-numbered conductive layer, and electrically isolated from each even-numbered electrically connected layer by the second insulating layer 122.

[0103] Similar to the first conductive structure described above, an adhesive layer 123 can be first disposed in the second connecting hole 121 to connect the odd-numbered layers. This adhesive layer 123 can be formed by atomic layer deposition (ALD) to achieve good coverage.

[0104] The material of the adhesion layer 123 can be a conductive material with good adhesion, such as Ti, TiN, Ta, TaN, etc. The first adhesion layer 121 can also serve as a seed layer and a barrier layer.

[0105] A conductive body 124 is then disposed in the second connection hole 121. The conductive body 124 and the adhesive layer 123 together form the second conductive structure.

[0106] The conductive body 124 can be made of metals such as copper (Cu) and tungsten (W).

[0107] The conductive body 124 can be formed by electroplating a conductive body material onto the adhesion layer 113 and then performing chemical mechanical polishing (CMP) to form a second conductive structure flush with the top dielectric layer 108.

[0108] This completes the stacked capacitor structure.

[0109] After step S70, the resulting stacked capacitor structure may include a set of first conductive structures and second conductive structures (i.e., a first conductive structure and a second conductive structure), or it may include multiple sets of first conductive structures and second conductive structures.

[0110] A first conductive structure and a second conductive structure are arranged at intervals in the x-direction.

[0111] Combination Figure 22 As shown, the stacked capacitor includes multiple sets of first conductive structures and second conductive structures. Each set of first conductive structures and second conductive structures is arranged along a first direction (i.e., the x-direction). Each first conductive structure in the multiple sets of first conductive structures and second conductive structures points in the same direction toward the second conductive structure in its respective set (i.e., the positive x-direction as shown in the figure). This facilitates the arrangement of the first connecting hole 111, the second connecting hole 121, the first conductive structures, and the second conductive structures.

[0112] For example, stacked capacitors are typically fabricated in wafer-level semiconductor structures and generally include multiple sets of first conductive structures and second conductive structures.

[0113] Combination Figure 24 and Figure 25 As shown, after step S70, the method may further include dividing the stacked capacitor structure to form multiple capacitor units spaced apart in the y-direction. For example... Figure 24 and Figure 25 The three capacitor units are shown.

[0114] There is a gap of 1001 between adjacent capacitor units. The gap extends to the base dielectric layer 001.

[0115] The direction y can be perpendicular to both directions x and z, or both directions can have other non-zero angles.

[0116] Understandable, Figure 24 and Figure 25 An example is shown with three capacitor cells. A stacked capacitor structure may include more capacitor cells.

[0117] One of the capacitor units may include, for example: Figure 24 and Figure 25 The diagram shows a stacked capacitor comprising a first conductive structure and a second conductive structure.

[0118] Of course, in some other embodiments, a capacitor unit may also include multiple sets of stacked capacitors corresponding to the first conductive structure and the second conductive structure.

[0119] It is understood that in the stacked capacitor formed by the above-described fabrication method, each conductive layer (such as the first conductive layer 101, the second conductive layer 103, the third conductive layer 105, and the fourth conductive layer 107) is a flat film. Correspondingly, each spacer dielectric layer (such as the first spacer dielectric layer 102, the second spacer dielectric layer 104, and the third spacer dielectric layer 106) is also a flat film. In this way, compared to when the spacer dielectric layer 104 and the conductive layers are non-flat films, the reduction in breakdown voltage caused by electric field concentration at non-flat locations (such as steps) can be avoided, which is beneficial for ensuring and improving the breakdown voltage of the stacked capacitor. At the same time, it also ensures the continuity of the films within the same conductive layer, guaranteeing the electrical performance of the stacked capacitor.

[0120] like Figure 26 and Figure 27 This application also provides a stacked capacitor 1. The stacked capacitor 1 includes a base dielectric layer 001, multiple conductive layers and multiple spacer dielectric layers, a top dielectric layer 108, a first connection hole 111, a second connection hole 121, a first conductive structure and a second conductive structure.

[0121] Multiple conductive layers and multiple spacer dielectric layers are located on the base dielectric layer 001. The multiple conductive layers and multiple spacer dielectric layers are stacked alternately; in each conductive layer, from the conductive layer closest to the base dielectric layer 001 to the conductive layer farthest from the base dielectric layer 001, the multiple conductive layers include alternately arranged odd-numbered conductive layers and even-numbered conductive layers; all odd-numbered conductive layers are made of the same material, and all even-numbered conductive layers are made of the same material; the odd-numbered conductive layers and even-numbered conductive layers in the multiple conductive layers are made of different materials.

[0122] like Figure 27As shown, the multilayer conductive layers include a first conductive layer 101, a second conductive layer 103, a third conductive layer 105, and a fourth conductive layer 107. The multilayer spacer dielectric layers include a first spacer dielectric layer 102, a second spacer dielectric layer 104, and a third spacer dielectric layer 106. The first conductive layer 101, the second conductive layer 103, the third conductive layer 105, the fourth conductive layer 107, and the first spacer dielectric layer 102, the second spacer dielectric layer 104, and the third spacer dielectric layer 106 are stacked alternately. In each conductive layer, from the first conductive layer 101 closest to the base dielectric layer 001 towards the fourth conductive layer 107 furthest from the base dielectric layer 001, that is, in the capacitor thickness direction z, the first conductive layer 101, the second conductive layer 103, the third conductive layer 105, and the fourth conductive layer 107 include alternating odd-numbered conductive layers (i.e., the first conductive layer 101 and the third conductive layer 105) and even-numbered conductive layers (i.e., the second conductive layer 103 and the fourth conductive layer 107). All odd-numbered conductive layers (i.e., the first conductive layer 101 and the third conductive layer 105) are made of the same material, and all even-numbered conductive layers (i.e., the second conductive layer 103 and the fourth conductive layer 107) are made of the same material. The odd-numbered conductive layers (i.e., the first conductive layer 101 and the third conductive layer 105) in the multilayer conductive layers are made of different materials than the even-numbered conductive layers (i.e., the second conductive layer 103 and the fourth conductive layer 107).

[0123] The first conductive layer 101, the second conductive layer 103, the third conductive layer 105, and the fourth conductive layer 107 can be formed by deposition methods, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0124] The thickness of each conductive layer can be 10nm-100nm. For example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, and 100nm.

[0125] In some embodiments, the material of the odd-numbered conductive layers is selected from aluminum, titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, citriium, molybdenum, and hafnium; The even-numbered conductive layers are selected from aluminum, titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, citric acid, molybdenum, and hafnium.

[0126] For example, in some embodiments, the odd-numbered conductive layers may be made of aluminum, and the even-numbered conductive layers may be made of titanium.

[0127] Understandably, the materials of the odd-numbered conductive layers are different from those of the even-numbered conductive layers. Furthermore, the physicochemical properties of the odd-numbered conductive layers' materials, oxides, and halides must be clearly distinguishable from those of the even-numbered conductive layers. This allows for better design of the subsequent first and second insulating layers.

[0128] The first spacer dielectric layer 102, the second spacer dielectric layer 104, and the third spacer dielectric layer 106 can all be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods.

[0129] The material of the interlayer dielectric layer can be any one or a mixture of materials including, but not limited to, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0130] The thickness of the dielectric layer separating each layer can be 5nm-50nm. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0131] It is understandable that the thickness of each conductive layer can be the same or different, the thickness of each spacer dielectric layer can be the same or different, and the material of each spacer dielectric layer can be the same or different, which can be set according to specific needs.

[0132] In some embodiments, the thickness of the spacer dielectric layer may be less than the thickness of the conductive layer.

[0133] The top dielectric layer 108 is disposed on the side of the multilayer conductive layer and the multilayer spacer dielectric layer away from the base dielectric layer 001.

[0134] like Figure 27 As shown, the top dielectric layer 108 is disposed on the side of the fourth conductive layer 107 away from the base dielectric layer 001.

[0135] The material of the top dielectric layer 108 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride.

[0136] The top dielectric layer 108 is relatively thick, at least greater than the thickness of a single spacer dielectric layer. The thickness of the top dielectric layer 108 can be greater than the thickness of a single conductive layer.

[0137] For stacked capacitors that are away from the base dielectric layer 001 (which can be understood as the top of the stacked capacitors) and require other metal interconnect structures to be set later, the top dielectric layer 108 can be used to isolate the metal interconnect structures in the back-end of line (BEOL) process on the top of the stacked capacitors.

[0138] The first connection hole 111 penetrates the top dielectric layer 108, all conductive layers, and the spacer dielectric layers. A first insulating layer 112 is formed on the hole wall of each odd-numbered conductive layer.

[0139] like Figure 27 As shown, a first insulating layer 112 is formed on the hole walls of the first conductive layer 101 and the third conductive layer 105.

[0140] In some embodiments, the first insulating layer 112 is a passivation layer. For example, when the odd-numbered conductive layers are aluminum, the first insulating layer 112 may be aluminum oxide.

[0141] In other embodiments, the first insulating layer 112 is a halide layer. For example, when the odd-numbered conductive layers are titanium, the first insulating layer 112 can be TiBr3.

[0142] The first insulating layer 112 can be formed using the corresponding process described above.

[0143] The first conductive structure is at least partially located in the first connection hole 111 and is electrically connected to each odd-numbered conductive layer, and is electrically isolated from each odd-numbered conductive layer by the first insulating layer 112.

[0144] In some embodiments, the first conductive structure may include an adhesive layer 113 (i.e., a first adhesive layer) and a conductive body 114 (i.e., a first conductive body). For example, the first conductive structure is formed by the conductive body 114 and the adhesive layer 113 together. The adhesive layer 113 is attached to the wall of the first connection hole 111, connecting each of the even-numbered conductive layers, and the conductive body 114 fills the first connection hole 111 and is covered by the adhesive layer 113.

[0145] The material of the adhesion layer 113 can be a conductive material with good adhesion, such as Ti, TiN, Ta, TaN, etc. The first adhesion layer 121 can also serve as a seed layer and a barrier layer.

[0146] The conductive body 114 can be made of metals such as copper (Cu) and tungsten (W).

[0147] In other embodiments, the first conductive structure can also be formed by directly filling the conductive body 114.

[0148] The second connection hole 121 penetrates the top dielectric layer 108, all conductive layers and spacer dielectric layers, and is spaced apart from the first connection hole 111; wherein, a second insulating layer 122 is formed on the hole wall of each even-numbered conductive layer.

[0149] It should be noted that the first connecting hole 111 and the second connecting hole 121 can be as follows: Figure 27 The shape is an inverted trapezoid or a similar shape. The cross-sectional dimensions of the first connecting hole 111 and the second connecting hole 121 near the bottom of the base dielectric layer 001 are smaller than the cross-sectional dimensions of the holes away from the openings of the base dielectric layer 001. In some embodiments, the second insulating layer 122 is a passivation layer. For example, when the even-numbered conductive layers are aluminum, the second insulating layer 122 can be aluminum oxide. In other embodiments, the second insulating layer 122 is a halide layer. For example, when the even-numbered conductive layer is titanium, the second insulating layer 122 can be TiBr3.

[0150] The second insulating layer 122 can be formed using the corresponding process described above.

[0151] The second conductive structure is at least partially located in the second connection hole 121 and is electrically connected to each odd-numbered conductive layer, and electrically isolated from each even-numbered electrically connected layer by the second insulating layer 122.

[0152] In some embodiments, the second conductive structure may include an adhesive layer 123 (i.e., a second adhesive layer) and a conductive body 124 (i.e., a second conductive body).

[0153] The adhesive layer 123 is attached to the wall of the second connection hole 121 to connect the odd-numbered conductive layers. The conductive body 124 is filled in the second connection hole 121 and covered by the adhesive layer 123.

[0154] For example, the adhesive layer 123 and the conductive body 124 form the second conductive structure.

[0155] The material of the adhesion layer 123 can be a conductive material with good adhesion, such as Ti, TiN, Ta, TaN, etc. The first adhesion layer 121 can also serve as a seed layer and a barrier layer.

[0156] The conductive body 124 can be made of metals such as copper (Cu) and tungsten (W).

[0157] In some other embodiments, the second conductive structure may also consist only of the conductive body 124.

[0158] like Figure 26 and Figure 27As shown, in the stacked capacitor formed by the above preparation method, each conductive layer (such as the first conductive layer 101, the second conductive layer 103, the third conductive layer 105, and the fourth conductive layer 107) is a flat film layer. Correspondingly, each spacer dielectric layer (such as the first spacer dielectric layer 102, the second spacer dielectric layer 104, and the third spacer dielectric layer 106) is also a flat film layer. In this way, compared with spacer dielectric layer 104 and conductive layers being non-flat films, the reduction in breakdown voltage caused by electric field concentration at non-flat points (such as steps) can be avoided, which is beneficial to ensuring and improving the breakdown voltage of the stacked capacitor. At the same time, it can also ensure the continuity of the film layers in the same conductive layer, ensuring the electrical performance of the stacked capacitor.

[0159] It should be noted that, as Figure 26 and Figure 27 The example shown has 4 conductive layers. It is understood that in some other embodiments, the stacked capacitor may also include other multiple conductive layers, such as 3, 5, 6, 7, 8, etc.

[0160] This application also provides a semiconductor device. The semiconductor device includes the stacked capacitor 1 as described above.

[0161] In some embodiments, the semiconductor device further includes a chip, and the stacked capacitor 1 is disposed outside the chip (e.g., on the surface of the chip or on the surface of the chip through other intermediate structural layers) or inside the chip.

[0162] The chips mentioned include, but are not limited to, high-performance chips such as CPU chips, GPU chips, FPGA chips, 5G modem chips, system-on-a-chip (SoC), power management chips (PMIC), and 2.5D / 3D chiplets.

[0163] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A stacked capacitor, characterized in that, include: Base dielectric layer; The system comprises multiple conductive layers and multiple spacer dielectric layers stacked alternately on a base dielectric layer. In each conductive layer, from the conductive layer closest to the base dielectric layer towards the conductive layer farthest from the base dielectric layer, the multiple conductive layers include alternating odd-numbered and even-numbered conductive layers. All odd-numbered conductive layers are made of the same material, and all even-numbered conductive layers are made of the same material. The odd-numbered conductive layers and even-numbered conductive layers in the multiple conductive layers are made of different materials. A top dielectric layer is disposed on the side of the multilayer conductive layer and the multilayer spacer dielectric layer that is away from the base dielectric layer; A first connecting hole penetrates the top dielectric layer, all conductive layers, and spacer dielectric layers; wherein a first insulating layer is formed on the hole wall of each odd-numbered conductive layer. A first conductive structure, at least partially located in the first connecting hole, electrically connected to each even-numbered conductive layer, and electrically isolated from each odd-numbered conductive layer by a first insulating layer; The second connection hole penetrates the top dielectric layer, all conductive layers and the spacer dielectric layer, and is spaced apart from the first connection hole; wherein, a second insulating layer is formed on the hole wall of each even-numbered conductive layer; The second conductive structure is at least partially located in the second connection hole and is electrically connected to each odd-numbered conductive layer, and electrically isolated from each even-numbered electrically connected layer by the second insulating layer.

2. The stacked capacitor as described in claim 1, characterized in that, The thickness of the conductive layer is 10nm-100nm; The thickness of the spacer dielectric layer is 5nm-50nm.

3. The stacked capacitor as described in claim 1, characterized in that, The material of the odd-numbered conductive layers is selected from aluminum, titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, citriium, molybdenum and hafnium; The even-numbered conductive layers are selected from aluminum, titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, citric acid, molybdenum, and hafnium.

4. The stacked capacitor as described in claim 1, characterized in that, Each conductive layer is a flat film layer; Each spacer dielectric layer is a flat film.

5. The stacked capacitor as described in claim 1, characterized in that, The first insulating layer is a passivation layer, or the first insulating layer is a halogenated layer.

6. The stacked capacitor as described in claim 1, characterized in that, The second insulating layer is a passivation layer, or the second insulating layer is a halogenated layer.

7. The stacked capacitor as described in claim 1, characterized in that, The stacked capacitor includes a first conductive structure and a second conductive structure; or, The stacked capacitor includes multiple sets of first conductive structures and second conductive structures, wherein each set of first conductive structures and second conductive structures is arranged along a first direction, and each first conductive structure in the multiple sets of first conductive structures and second conductive structures points in the same direction toward the second conductive structure in its respective set.

8. The stacked capacitor as described in claim 1, characterized in that, The first conductive structure includes a first adhesive layer and a first conductive body. The first adhesive layer is attached to the wall of the first connecting hole to connect each of the even-numbered conductive layers. The first conductive body fills the first connecting hole and is covered by the first adhesive layer. The second conductive structure includes a second adhesive layer and a second conductive body. The second adhesive layer is attached to the wall of the second connection hole to connect the odd-numbered conductive layers. The second conductive body fills the second connection hole and is covered by the second adhesive layer.

9. A semiconductor device, characterized in that, The semiconductor device includes a stacked capacitor as described in any one of claims 1 to 8.

10. The semiconductor device as claimed in claim 9, characterized in that, The semiconductor device further includes a chip, and the stacked capacitor is disposed outside the chip or inside the chip.

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