A stacked capacitor and semiconductor device

Abstract

This application provides a stacked capacitor and a semiconductor device. The semiconductor device includes a base dielectric layer, a capacitor body, a top dielectric layer, a first connection hole, a second connection hole, a first conductive structure, and a second conductive structure. The capacitor body includes multiple stacked conductive layers and spacer dielectric layers. The stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a first direction. Odd-numbered conductive layers are located in the first connection region and the conductive layer stack region, and even-numbered conductive layers are located in the second connection region and the conductive layer stack region. The first connection hole is located in the first connection region and is stepped. The first conductive structure is electrically connected to the sidewalls of each odd-numbered conductive layer and the surface of each odd-numbered conductive layer exposed from the first connection hole. The second connection hole is located in the second connection region and is stepped. The second conductive structure is electrically connected to the sidewalls of each even-numbered conductive layer and the surface of each even-numbered conductive layer exposed from the second connection hole.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a stacked capacitor and semiconductor device. Background Technology

[0002] Capacitors are common and important passive electronic components in integrated circuits. Common capacitors include metal-oxide-semiconductor (MOS) capacitors, PN junction capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and metal-insulator-metal (MIM) capacitors. MIM capacitors are typically formed on a metal interconnect structure in the back-end of line (BEOL) process. This increases the distance between the MIM capacitor and the silicon substrate, thereby reducing the parasitic capacitance between the MIM capacitor and the substrate. Furthermore, the performance of MIM capacitors is less affected by frequency and temperature. In addition, MIM capacitors are formed during the metal interconnect process, making the MIM formation process compatible with existing integrated circuit technologies. Therefore, MIM capacitors have gradually become the mainstream type of passive capacitor. As Moore's Law continues to evolve, the requirements for capacitor density in integrated circuits are becoming increasingly stringent. This is particularly evident in high-performance chips such as CPUs, GPUs, and FPGAs; mobile chips including 5G modems, system-on-a-chip (SoC), power management chips (PMICs), and 2.5D / 3D chiplets, where there is a significant demand for high-density capacitors. Currently, a major mainstream structure for achieving high-density capacitors is stacked capacitors. Improving the performance of stacked capacitors has become a major focus. Summary of the Invention

[0003] This application provides a stacked capacitor, which includes: Base dielectric layer; A capacitor body located on a base dielectric layer, the capacitor body comprising multiple stacked conductive layers and spacer dielectric layers located between each adjacent pair of conductive layers; in each conductive layer, from the surface of the base dielectric layer toward the conductive layer farthest from the base dielectric layer, the multiple conductive layers comprise alternately arranged odd-numbered conductive layers and even-numbered conductive layers; wherein, the stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a first direction; each odd-numbered conductive layer is located in the first connection region and the conductive layer stack region, and each even-numbered conductive layer is located in the second connection region and the conductive layer stack region; A top dielectric layer is located on the side of the capacitor body that is away from the base dielectric layer. The first connection hole is located in the first connection area and is stepped. The first connection hole penetrates the top dielectric layer, penetrates each odd-numbered conductive layer above the odd-numbered conductive layer closest to the base dielectric layer, and penetrates the spacer dielectric layer between each odd-numbered conductive layer. In each pair of adjacent odd-numbered conductive layers, the orthographic projection of the odd-numbered conductive layer away from the base dielectric layer on the surface of the base dielectric layer falls into the orthographic projection of the odd-numbered conductive layer close to the base dielectric layer on the surface of the base dielectric layer. Furthermore, at least one of the odd-numbered conductive layers has a portion of its surface on the side away from the base dielectric layer exposed in the first connection hole. A first conductive structure is located in the first connecting hole, and the first conductive structure is electrically connected to the sidewalls of each odd-numbered conductive layer and the exposed surfaces of each odd-numbered conductive layer from the first connecting hole. The second connection hole is located in the second connection area and is stepped. The second connection hole penetrates the top dielectric layer, penetrates each even-numbered conductive layer above the even-numbered conductive layer closest to the base dielectric layer, and penetrates the spacer dielectric layer between each even-numbered conductive layer. In each pair of adjacent even-numbered conductive layers, the orthographic projection of the even-numbered conductive layer away from the base dielectric layer on the surface of the base dielectric layer falls within the orthographic projection of the even-numbered conductive layer close to the base dielectric layer on the surface of the base dielectric layer. Furthermore, at least one even-numbered conductive layer has a portion of its surface on the side away from the base dielectric layer exposed in the second connection hole. The second conductive structure is located in the second connection hole, and the second conductive structure is electrically connected to the sidewalls of each even-numbered conductive layer and the exposed surfaces of each even-numbered conductive layer from the second connection hole.

[0004] In some embodiments, the first conductive structure includes a first conductive body and a first adhesive layer; the first conductive body fills the first connection hole; the first adhesive layer is located between the first conductive body and the inner wall of the first connection hole; and / or, The second conductive structure includes a second conductive body and a second adhesive layer; the second conductive body is filled in the second connection hole; the second adhesive layer is located between the second conductive body and the inner wall of the second connection hole.

[0005] In some embodiments, each of the conductive layers is a metal layer.

[0006] In some embodiments, the thickness of each conductive layer is the same.

[0007] In some embodiments, among the odd-numbered conductive layers, the odd-numbered conductive layer closest to the base dielectric layer is flat, and the other odd-numbered conductive layers include a first flat portion, a second flat portion, and a first connecting portion connecting the first flat portion and the second flat portion; wherein the distance between the first flat portion and the base dielectric layer is less than the distance between the second flat portion and the base dielectric layer.

[0008] In some embodiments, each even-numbered conductive layer includes a third flat portion, a fourth flat portion, and a second connecting portion connecting the third flat portion and the fourth flat portion; wherein the distance between the third flat portion and the base dielectric layer is less than the distance between the fourth flat portion and the base dielectric layer.

[0009] In some embodiments, the thickness of the conductive layer is 10nm-100nm.

[0010] In some embodiments, in the conductive stack region, the thickness of the spacer dielectric layer located between two adjacent conductive layers is 5 nm-50 nm.

[0011] This application also provides a semiconductor device, which includes stacked capacitors as described above.

[0012] In some embodiments, the semiconductor device further includes a chip, and the stacked capacitors are disposed outside the chip or inside the chip.

[0013] The main technical effects achieved by the embodiments of this application are: The stacked capacitor and semiconductor device provided in this application embodiment, by setting the connection holes in the stacked capacitor as stepped holes, enable the conductive structure in each connection hole to contact the surface of at least part of the conductive layer away from the base dielectric layer, thereby increasing the contact area between the conductive structure and the conductive layer, which is beneficial to reducing contact resistance and improving the reliability of the stacked capacitor. Attached Figure Description

[0014] Figure 1 This is a flowchart illustrating a method for fabricating a stacked capacitor according to an exemplary embodiment of this application; Figures 2 to 17 These are structural diagrams corresponding to different processes used in fabricating stacked capacitors using an exemplary embodiment of this application. Figure 18 This is a top view of a stacked capacitor provided in an exemplary embodiment of this application; Figure 19 It is along Figure 18 The cross-sectional view of the stacked capacitors obtained by section line AA shown. Detailed Implementation

[0015] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0016] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture; if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0017] The following is in conjunction with the appendix Figures 1 to 19 The following describes some embodiments of this application in detail. Unless otherwise specified, the embodiments and features described below can be combined with each other.

[0018] Please refer to Figure 1 This application provides a method for fabricating stacked capacitors, which includes the following steps S10 to S60: In step S10, a base dielectric layer is provided; In step S20, a capacitor body is formed on the base dielectric layer. The capacitor body includes multiple stacked conductive layers and spacer dielectric layers located between each pair of adjacent conductive layers. In each conductive layer, from the surface of the base dielectric layer toward the conductive layer farthest from the base dielectric layer, the multiple conductive layers include alternating odd-numbered conductive layers and even-numbered conductive layers. The stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a first direction. Each odd-numbered conductive layer is located in the first connection region and the conductive layer stack region, and each even-numbered conductive layer is located in the second connection region and the conductive layer stack region. In step S30, a top dielectric layer is formed, which is located on the side of the capacitor body away from the base dielectric layer; In step S40, a first connection hole is formed, which penetrates the top dielectric layer, penetrates each odd-numbered conductive layer above the odd-numbered conductive layer closest to the base dielectric layer, and penetrates the spacer dielectric layer between each odd-numbered conductive layer; in each pair of adjacent odd-numbered conductive layers, the orthographic projection of the odd-numbered conductive layer facing away from the base dielectric layer on the surface of the base dielectric layer falls within the orthographic projection of the odd-numbered conductive layer close to the base dielectric layer on the surface of the base dielectric layer, and at least one of the odd-numbered conductive layers has a portion of its surface facing away from the base dielectric layer exposed in the first connection hole; In step S50, a second connection hole is formed, which penetrates the top dielectric layer, all even-numbered conductive layers above the even-numbered conductive layer closest to the base dielectric layer, and the spacer dielectric layer between the even-numbered conductive layers. In each pair of adjacent even-numbered conductive layers, the orthographic projection of the even-numbered conductive layer facing away from the base dielectric layer on the surface of the base dielectric layer falls within the orthographic projection of the even-numbered conductive layer closest to the base dielectric layer on the surface of the base dielectric layer, and at least one even-numbered conductive layer has a portion of its surface facing away from the base dielectric layer exposed in the second connection hole. In step S60, a first conductive structure is formed in the first connecting hole and a second conductive structure is formed in the second connecting hole; the first connecting hole is located in the first connecting region and is stepped, and the first conductive structure is electrically connected to the sidewalls of each odd-numbered conductive layer and the surface of each odd-numbered conductive layer exposed from the first connecting hole; the second connecting hole is located in the second connecting region and is stepped, and the second conductive structure is electrically connected to the sidewalls of each even-numbered conductive layer and the surface of each even-numbered conductive layer exposed from the second connecting hole.

[0019] The following is combined with Figures 2 to 17 Taking a 6-layer conductive layer as an example, the fabrication method of the above-mentioned stacked capacitor will be described in detail. It is understood that the conductive layer can also be multiple layers, such as 3, 4, 5, 7, 8, etc.

[0020] In step S10, a base dielectric layer 2 is provided.

[0021] The material of the base dielectric layer 2 can be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride, to provide a platform for the subsequent manufacturing of stacked capacitors (and MIM stacked capacitors).

[0022] It is understood that the stacked capacitor can be a capacitor structure formed inside the chip or on the chip surface. In the implementation where the stacked capacitor is formed inside the chip or on the chip surface, the base dielectric layer 2 can also be used to isolate the previous metal interconnect structure in the back-end of line (BEOL) process, that is, to electrically isolate the stacked capacitor from the chip.

[0023] The base dielectric layer 2 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods.

[0024] The base dielectric layer 2 may have mutually opposing surfaces 21 and 22.

[0025] Combination Figures 2 to 4 As shown, in step S20, a capacitor body 1 is formed on the base dielectric layer 2. The capacitor body 1 is disposed on the surface 21 of the base dielectric layer 2.

[0026] The capacitor body 1 includes multiple stacked conductive layers 101 and spacer dielectric layers 102 located between each adjacent pair of conductive layers 101. In each conductive layer 101, from the surface S1 of the base dielectric layer 2 towards the conductive layer 101 furthest from the base dielectric layer 2, i.e., in the thickness direction of the stacked capacitor (i.e., the second direction z), the multiple conductive layers 101 include alternating odd-numbered and even-numbered conductive layers 101. The stacked capacitor has a first connection region Q1, a conductive layer stack region Q2, and a second connection region Q2 arranged along the first direction x; each odd-numbered conductive layer 101 is located in the first connection region Q1 and the conductive layer stack region Q2, and each even-numbered conductive layer 101 is located in the second connection region Q2 and the conductive layer stack region Q2.

[0027] The first direction x and the second direction z are perpendicular to each other. Of course, they can also have other non-zero angles.

[0028] Combination Figure 4 As shown, the capacitor body 1 includes multiple stacked layers: a first conductive layer 1011, a second conductive layer 1012, a third conductive layer 1013, a fourth conductive layer 1014, a fifth conductive layer 1015, and a sixth conductive layer 1016. A spacer dielectric layer 102 is formed between each adjacent pair of conductive layers 1011, 1012, 1013, 1014, 1015, and 1016.

[0029] In the direction from the surface 21 of the base dielectric layer 2 toward the sixth conductive layer 1016, which is furthest from the base dielectric layer 2, the conductive layer 101 includes odd-numbered conductive layers such as the first conductive layer 1011, the third conductive layer 1013, and the fifth conductive layer 1015, and even-numbered conductive layers such as the second conductive layer 1012, the fourth conductive layer 1014, and the sixth conductive layer 1016.

[0030] Conductive material layers can be deposited layer by layer, and each layer can be patterned by etching to form the corresponding conductive layer 101. The following is a combination of... Figures 2 to 4 The formation of capacitor body 1 is described in detail.

[0031] Combination Figure 2 As shown, the first conductive layer 1011 is formed.

[0032] First, a first conductive material layer can be deposited on the base dielectric layer 2. A mask layer (such as photoresist) is set on the first conductive material layer to etch away the photoresist on the area to be etched. The conductive material layer is patterned by etching, and the first conductive layer 1011 is formed after removing the mask layer.

[0033] The first conductive material layer can be formed by deposition, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0034] The material of the first conductive layer 1011 can be a metallic material, such as aluminum. Of course, in some other embodiments, the material of the first conductive layer can also be selected from, but is not limited to, titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, zirconia, molybdenum, hafnium, and other etchable metals.

[0035] The thickness of the first conductive layer 1011 can be 10nm-100nm. For example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, and 100nm.

[0036] Combination Figure 3 As shown, a first spacer dielectric layer 1021 is then formed on the first conductive layer 1011.

[0037] The first spacer dielectric layer 1021 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods.

[0038] The first spacer dielectric layer 1021 covers the surface of the first conductive layer 1011 away from the base dielectric layer 2, covers the sidewall of the first conductive layer 1011 facing the second connection area Q3, and covers the area on the surface 21 of the base dielectric layer 2 exposed from the first conductive layer 1011.

[0039] The first spacer dielectric layer 1021 has a uniform thickness in all regions.

[0040] The material of the first spacer dielectric layer 1021 can be any one or more mixed materials selected from, but not limited to, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0041] In some embodiments, the thickness of the first spacer dielectric layer 1021 can be 5nm-50nm. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0042] Continue to combine Figure 3 Then, a second conductive layer 1012 is formed on the first spacer dielectric layer 1021.

[0043] The second conductive layer 1012 can be configured in the same way as the first conductive layer 1011, as described above.

[0044] Combination Figure 4 As shown, a second spacer dielectric layer 1022, a third conductive layer 1013, a third spacer dielectric layer 1023, a fourth conductive layer 1014, a fourth spacer dielectric layer 1024, a fifth conductive layer 1015, a fifth spacer dielectric layer 1025, and a sixth conductive layer 1016 are sequentially disposed on the second conductive layer 1012, thereby forming the capacitor body 1.

[0045] It is understandable that the thickness of each conductive layer 101 can be the same.

[0046] The material of each conductive layer 101 can be the same. For example, the material of each conductive layer 101 can be a metal, such as aluminum. Of course, in some other embodiments, the material of each conductive layer can also be selected from, but is not limited to, etchable metals such as titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, zirconia, molybdenum, and hafnium.

[0047] The thickness of each spacer dielectric layer 102 can be the same. The material of each spacer dielectric layer can be the same. For example, the material of each spacer dielectric layer can be any one or more of the following materials, including but not limited to HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.

[0048] It is understood that in some other embodiments, the materials of the conductive layers may also be different. The thickness of each conductive layer 101 may also be different. The materials of each spacer dielectric layer 102 may also be different. The thickness of each spacer dielectric layer 102 may also be different.

[0049] like Figure 5 As shown, in step S30, a top dielectric layer 103 is formed. The top dielectric layer 103 is located on the side of the capacitor body 1 opposite to the base dielectric layer 2.

[0050] In this embodiment, the top dielectric layer 103 is disposed on the side of the fourth conductive layer 107 away from the base dielectric layer 2.

[0051] The top dielectric layer 103 is made of a low-k dielectric material (a low-k dielectric material is a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material is a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride.

[0052] The top dielectric layer 103 is relatively thick, at least greater than the thickness of a spacer dielectric layer. The thickness of the top dielectric layer 103 can be greater than the thickness of a conductive layer.

[0053] For stacked capacitors that are away from the base dielectric layer 2 (which can be understood as the top of the stacked capacitors) and require the subsequent setting of other metal interconnect structures, the top dielectric layer 103 can be used to isolate the metal interconnect structures in the back-end of line (BEOL) process at the top of the stacked capacitors.

[0054] Combination Figures 6 to 15 In step S40, a first connection hole 1005 is formed. The first connection hole 1005 is located in the first connection area Q1 and is stepped. The first connection hole 1005 penetrates the top dielectric layer 103, penetrates each odd-numbered conductive layer 101 above the odd-numbered conductive layer 101 closest to the base dielectric layer 2, and penetrates the spacer dielectric layer 102 between each odd-numbered conductive layer 101. In each pair of adjacent odd-numbered conductive layers 101, the orthographic projection of the odd-numbered conductive layer 101 facing away from the base dielectric layer 2 onto the surface 21 of the base dielectric layer 2 falls within the orthographic projection of the odd-numbered conductive layer 101 closest to the base dielectric layer 2 onto the surface 21 of the base dielectric layer 2, and at least one of the odd-numbered conductive layers 101 has a portion of its surface 21 facing away from the base dielectric layer 2 exposed in the first connection hole 1005.

[0055] Combination Figures 6 to 15In step S50, a second connection hole 1010 is formed. The second connection hole 1010 is located in the second connection area Q2 and is stepped. The second connection hole 1010 penetrates the top dielectric layer 103, penetrates each even-numbered conductive layer 101 above the even-numbered conductive layer 101 closest to the base dielectric layer 2, and penetrates the spacer dielectric layer 102 between each even-numbered conductive layer 101; in each pair of adjacent even-numbered conductive layers 101, the orthographic projection of the even-numbered conductive layer 101 facing away from the base dielectric layer 2 on the surface of the base dielectric layer 2 falls within the orthographic projection of the even-numbered conductive layer 101 closest to the base dielectric layer 2 on the surface of the base dielectric layer 2, and at least one even-numbered conductive layer 101 has a portion of its surface facing away from the base dielectric layer 2 exposed in the second connection hole 1010.

[0056] In some embodiments, the first connection hole 1005 may be formed by etching.

[0057] When etching to form the first connection hole 1005, the etching stops at the odd-numbered conductive layer 101 closest to the base dielectric layer 2, which is away from the surface of the base dielectric layer 2. After the first conductive structure is formed, the first conductive structure and the odd-numbered conductive layer 101 closest to the base dielectric layer 2 are away from the surface of the base dielectric layer 2.

[0058] In some embodiments, the second connection hole 1010 may be formed by etching.

[0059] When etching to form the second connection hole 1010, the etching stops at the even-numbered conductive layer 101 closest to the base dielectric layer 2, which is away from the surface of the base dielectric layer 2. After the second conductive structure is formed, the second conductive structure and the even-numbered conductive layer 101 closest to the base dielectric layer 2 are away from the surface of the base dielectric layer 2.

[0060] In some embodiments, the first connecting hole 1005 and the second connecting hole 1010 are formed simultaneously, which helps to save process time and reduce hole opening costs.

[0061] In some embodiments, the first connection hole 1005 and the second connection hole 1010 can be formed by etching the same mask layer in stages, further reducing the cost of opening holes.

[0062] Combination Figures 6 to 15 As shown, an exemplary embodiment in which the first connecting hole 1005 and the second connecting hole 1010 are formed simultaneously and using the same mask layer 200 is provided.

[0063] like Figure 6 and Figure 7As shown, a mask layer 200 is formed on the surface of the top dielectric layer 103 facing away from the base dielectric layer 2. Two etched holes 201 are respectively located above the first connection region Q1 and the second connection region Q3 on the mask layer 200.

[0064] The etched hole 201 can be opened by etching, such as by using oxygen etching, so as not to damage the conductive layer 101 and the spacer dielectric layer 102.

[0065] The mask layer 200 can be photoresist.

[0066] Continuing, such as Figure 8 As shown, etching forms a central hole 1001 located in the first connection region Q1 and a central hole 1006 located in the second connection region Q3.

[0067] A central via 1001 penetrates the top dielectric layer 103 and the fifth spacer dielectric layer 1025 located above the fifth conductive layer 1015. Correspondingly, the fifth conductive layer 1015 is exposed through the central via 1001. A central via 1006 penetrates the top dielectric layer 103. A sixth conductive layer 1016 is exposed through the central via 1006.

[0068] Intermediate vias 1001 and 1006 can be formed by etching, such as dry etching. A gaseous material that serves as an etching stop layer on the conductive layer and is capable of etching the top dielectric layer 103 can be used for etching. For example, fluorine-based gases.

[0069] Taking the conductive layer 101 as an example of aluminum material, it can be dry etched using fluorine (F) gas to etch away the dielectric, and the conductive layer 101 is a stop layer.

[0070] Specifically, fluorine (F) gases can etch the top dielectric layer 103 and the exposed fifth spacer dielectric layer 1025. However, a dense AlF3 film forms on the surface of Al. AlF3 has a melting and boiling point of over 1,000 degrees Celsius, making it difficult to generate volatile products and thus hindering the etching of Al.

[0071] Continuing, such as Figure 9 and 10 As shown, the fifth conductive layer 1015 and the sixth conductive layer 1016 are etched to form intermediate holes 1002 that penetrate the top dielectric layer 103 and the fifth conductive layer 1015, and intermediate holes 1007 that penetrate the top dielectric layer 103 and the sixth conductive layer 1016, respectively.

[0072] The fifth conductive layer 1015 and the sixth conductive layer 1016 can be etched using a dry etching method. For example, dry etching can be used.

[0073] Taking the material of conductive layer 101 as aluminum as an example, since AlCl3 has a low melting and boiling point, it can generate volatile products that can be etched away by Cl-type gases. Therefore, the fifth conductive layer 1015 and the sixth conductive layer 1016 can be etched away by dry etching with chlorine (Cl)-type gases.

[0074] The fifth conductive layer 1015 and the sixth conductive layer 1016 were etched simultaneously.

[0075] Accordingly, the fourth spacer dielectric layer 1024 below the fifth conductive layer 1015 is exposed, and the fifth spacer dielectric layer 1025 below the sixth conductive layer 1016 is exposed.

[0076] Continue, continue to combine Figure 9 and Figure 10 As shown, etching can continue at the etching hole 201 of the mask layer 200 to form the etching hole 202.

[0077] This means etching a certain distance outward from the etched hole 201 to form a larger etched hole 202.

[0078] The etching hole 202 can be etched using the same etching method as the etching hole 201.

[0079] Continuing, such as Figure 11 The intermediate holes 1003 and 1008 are formed by etching according to the etching hole 202.

[0080] The exposed top dielectric layer 103 and part of the spacer dielectric layer 102 are etched. The intermediate hole 1002 can be etched to form the intermediate hole 1003, and the intermediate hole 1007 can be etched to form the intermediate hole 1008.

[0081] Compared to intermediate hole 1002, in intermediate hole 1003, the top dielectric layer 103 and the connected fifth spacer dielectric layer 1025 are etched outwards to form dimensions matching the etched hole 202. The exposed fourth spacer dielectric layer 1024, along with the underlying third spacer dielectric layer 1023, is also etched. During this etching step, due to the protection of the fifth conductive layer 1015, the fourth spacer dielectric layer 1024, along with the underlying third spacer dielectric layer 1023, is etched to the point where it matches the dimensions of the etched hole 202. Figure 9 and Figure 10 The fifth conductive layer 1015 shown is etched to match the dimensions.

[0082] Compared to intermediate via 1007, in intermediate via 1008, the top dielectric layer 103 is etched outwards to form a size matching the etched via 202. The exposed fifth spacer dielectric layer 1025, along with the underlying fourth spacer dielectric layer 1024, is etched. During this etching step, due to the protection of the sixth conductive layer 1016, the fifth spacer dielectric layer 1025 and the fourth spacer dielectric layer 1024 are etched to a size matching the etched via 1008. Figure 9and Figure 10 The dimensions of the sixth conductive layer 1016 shown are matched.

[0083] This etching step is similar to the etching steps of intermediate hole 1001 and intermediate hole 1006 mentioned above, and can be referred to the relevant descriptions above.

[0084] Continuing, such as Figure 12 and Figure 13 As shown, the third conductive layer 1013 and the fourth conductive layer 1014 are etched to form intermediate holes 1004 and 1009, respectively. Further etching of the photoresist forms a larger etched hole 203.

[0085] Continuing, such as Figure 14 As shown, the etching of the dielectric layer continues to form the first connection hole 1005 and the second connection hole 1010.

[0086] Continuing, such as Figure 15 As shown, the photoresist is removed.

[0087] It should be noted that in the above embodiments, the mask layer 200, each dielectric layer, and the conductive layer are etched using different etching materials to form the stepped first and second connecting holes. When etching the mask layer 200, the exposed dielectric and conductive layers are not etched. When etching the dielectric layer, the exposed mask layer 200 and the exposed conductive layer are not etched. When etching the conductive layer, the mask layer 200 and the exposed dielectric layer are not etched.

[0088] It is understood that in some other embodiments, the first connecting hole and the second connecting hole may be formed asynchronously. The first connecting hole and the second connecting hole may also not be formed using the same mask layer for etching.

[0089] like Figure 16 and Figure 17 In step S60, a first conductive structure 110 is formed in the first connecting hole 1005 and a second conductive structure 120 is formed in the second connecting hole 1010. The first conductive structure 110 is electrically connected to the sidewalls of each odd-numbered conductive layer 101 and the exposed surfaces of each odd-numbered conductive layer 101 from the first connecting hole 1005; the second conductive structure 120 is electrically connected to the sidewalls of each even-numbered conductive layer 101 and the exposed surfaces of each even-numbered conductive layer 101 from the second connecting hole 1010.

[0090] In some embodiments, the first conductive structure 110 and the second conductive structure 120 are formed simultaneously.

[0091] An adhesive layer 111 can be first formed in the first connecting hole 1005 and the second connecting hole 1010 respectively. The adhesive layer 111 can be formed by atomic layer deposition (ALD) to achieve good coverage.

[0092] The adhesive layer 111 can be made of metal materials with good adhesion, such as TiN and TaN.

[0093] Then, conductive bodies 112 are respectively provided in the first connecting hole 1005 and the second connecting hole 1010. The conductive body 112 in the first connecting hole 1005 and the adhesive layer 113 together form the first conductive structure 110. The conductive body 112 in the second connecting hole 1010 and the adhesive layer 113 together form the second conductive structure 120.

[0094] The conductive body 112 can be made of metals such as copper (Cu) and tungsten (W).

[0095] The conductive body 112 can be produced by electroplating. After electroplating the conductive body material onto the adhesive layer 111, chemical mechanical polishing (CMP) is performed to form a first conductive structure 110 and a second conductive structure 120 that are flush with the top dielectric layer 103.

[0096] In other embodiments, the first conductive structure and the second conductive structure may also be formed by directly filling the conductive body 112.

[0097] It should be noted that in some other embodiments, the first conductive structure and the second conductive structure may be formed asynchronously.

[0098] At this point, the manufacturing of the MIM stacked capacitor with the stepped via is complete.

[0099] It should be noted that, in combination Figure 2 , Figure 3 as well as Figure 16 As shown, when fabricating stacked capacitors using the above-described method, each conductive layer requires photolithography and etching to form the pattern needed for an odd (even) number of conductive layers. A top view of the pattern is shown below. Figure 16 As shown, the sectional view is as follows Figure 2 As shown in Figure 3, two types of patterned metal layers are continuously stacked to form the capacitor body 1. The capacitor body 1 has an insulating spacer region 1031 around which the conductive material is etched away. This region is then filled by the top dielectric layer 103. Accordingly, when multiple stacked capacitors are formed simultaneously, the conductive layers of different stacked capacitors are located in different regions and are not connected in this step. That is, when the conductive layers are patterned, the capacitor region is already divided, and there is no need for further photolithography and etching to divide the capacitor region.

[0100] Understandable Figure 16The third direction y shown is perpendicular to each other or has other non-zero angles between each other with respect to the first direction x and the second direction y.

[0101] It is understandable that the above-described method for fabricating stacked capacitors is applicable to fabricating multiple stacked capacitors simultaneously on a wafer.

[0102] Please refer to Figure 18 and Figure 19 As shown, this application also provides a stacked capacitor 100, which includes a base dielectric layer 2, a capacitor body 1 located on the base dielectric layer 2, a top dielectric layer 103, a first connection hole 1005, a first conductive structure 110, a second connection hole 1010 and a second conductive structure 120.

[0103] The material of the base dielectric layer 2 can be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride, to provide a platform for the subsequent manufacturing of stacked capacitors (and MIM stacked capacitors).

[0104] It is understood that the stacked capacitor can be a capacitor structure formed inside the chip or on the chip surface. In the implementation where the stacked capacitor is formed inside the chip or on the chip surface, the base dielectric layer 2 can also be used to isolate the previous metal interconnect structure in the back-end of line (BEOL) process, that is, to electrically isolate the stacked capacitor from the chip.

[0105] The base dielectric layer 2 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods.

[0106] The base dielectric layer 2 may have mutually opposing surfaces 21 and 22.

[0107] The capacitor body 1 includes multiple stacked conductive layers 101 and spacer dielectric layers 102 located between each pair of adjacent conductive layers 101. Each conductive layer 101, from the surface of the base dielectric layer 2 towards the conductive layer 101 furthest from the base dielectric layer 2, includes alternating odd-numbered and even-numbered conductive layers 101. The stacked capacitor has a first connection region Q1, a conductive layer stack region Q2, and a second connection region Q2 arranged along a first direction x. Each odd-numbered conductive layer 101 is located in the first connection region Q1 and the conductive layer stack region Q2, and each even-numbered conductive layer 101 is located in the second connection region Q2 and the conductive layer stack region Q2.

[0108] Combination Figure 19As shown, the capacitor body 1 includes multiple stacked layers: a first conductive layer 1011, a second conductive layer 1012, a third conductive layer 1013, a fourth conductive layer 1014, a fifth conductive layer 1015, and a sixth conductive layer 1016. A spacer dielectric layer 102 is formed between each adjacent pair of conductive layers 1011, 1012, 1013, 1014, 1015, and 1016.

[0109] In the direction from the surface 21 of the base dielectric layer 2 toward the sixth conductive layer 1016, which is furthest from the base dielectric layer 2, the conductive layer 101 includes odd-numbered conductive layers such as the first conductive layer 1011, the third conductive layer 1013, and the fifth conductive layer 1015, and even-numbered conductive layers such as the second conductive layer 1012, the fourth conductive layer 1014, and the sixth conductive layer 1016.

[0110] The conductive material layers can be deposited layer by layer and patterned by etching to form the corresponding conductive layers 101.

[0111] In some embodiments, the conductive layer 101 may be made of a metallic material, such as aluminum. Of course, in other embodiments, the material of each conductive layer may also be selected from, but is not limited to, etchable metals such as titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, zirconia, molybdenum, and hafnium.

[0112] In some embodiments, the thickness of the conductive layer 101 can be 10nm-100nm. For example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm.

[0113] In some embodiments, the material of the spacer dielectric layer 102 may be any one or more mixed materials selected from, but not limited to, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0114] In some embodiments, the thickness of the spacer dielectric layer 102 located between two adjacent conductive layers 101 in the conductive stack region Q2 is 5nm-50nm. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0115] It is understandable that the thickness of the spacer dielectric layer 102 can be 5nm-50nm in each region. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0116] It is understandable that the materials of each conductive layer can be the same or different. The thickness of each conductive layer 101 can be the same or different. The materials of each spacer dielectric layer 102 can be the same or different. The thickness of each spacer dielectric layer 102 can be the same or different.

[0117] In some embodiments, among the odd-numbered conductive layers 101, the odd-numbered conductive layer 101 closest to the base dielectric layer 2 is flat, and the other odd-numbered conductive layers 101 include a first flat portion, a second flat portion, and a first connecting portion connecting the first flat portion and the second flat portion; wherein the distance between the first flat portion and the base dielectric layer 2 is less than the distance between the second flat portion and the base dielectric layer 2. That is, the second flat portion is higher than the first flat portion.

[0118] For example, the third conductive layer 1013 includes a first flat portion 10131, a second flat portion 10132, and a first connecting portion 10133. The second flat portion 10132 is higher than the first flat portion 10131.

[0119] In some embodiments, each even-numbered conductive layer 101 includes a third flat portion, a fourth flat portion, and a second connecting portion connecting the third flat portion and the fourth flat portion; wherein the distance between the third flat portion and the base dielectric layer 2 is less than the distance between the fourth flat portion and the base dielectric layer 2. That is, the fourth flat portion is higher than the third flat portion.

[0120] For example, the second conductive layer 1012 includes a third flat portion 10121, a fourth flat portion 10122, and a second connecting portion 10123. The fourth flat portion 10122 is higher than the third flat portion 10121.

[0121] The top dielectric layer 103 is located on the side of the capacitor body 1 that is away from the base dielectric layer 2.

[0122] The first connection hole 1005 is located in the first connection area Q1 and is stepped. The first connection hole 1005 penetrates the top dielectric layer 103, penetrates each odd-numbered conductive layer 101 above the odd-numbered conductive layer 101 closest to the base dielectric layer 2, and penetrates the spacer dielectric layer 102 between each odd-numbered conductive layer 101. In each pair of adjacent odd-numbered conductive layers 101, the orthographic projection of the odd-numbered conductive layer 101 facing away from the base dielectric layer 2 on the surface of the base dielectric layer 2 falls into the orthographic projection of the odd-numbered conductive layer 101 close to the base dielectric layer 2 on the surface of the base dielectric layer 2. At least one of the odd-numbered conductive layers 101 has a portion of its surface facing away from the base dielectric layer 2 exposed in the first connection hole 1005.

[0123] The first conductive structure 110 is located in the first connection hole 1005, and the first conductive structure 110 is electrically connected to the sidewalls of each odd-numbered conductive layer 101 and the surface of each odd-numbered conductive layer 101 exposed from the first connection hole 1005.

[0124] In some embodiments, the first conductive structure 110 includes a conductive body 112 (i.e., a first conductive body) and an adhesive layer 111 (i.e., a first adhesive layer). The conductive body 112 fills the first connection hole 1005; the adhesive layer 111 is located between the conductive body 112 and the inner wall of the first connection hole 1005.

[0125] The adhesive layer 111 can be made of metal materials with good adhesion, such as TiN and TaN.

[0126] The conductive body 112 can be made of metals such as copper (Cu) and tungsten (W).

[0127] The second connection hole 1010 is located in the second connection area Q2 and is stepped. The second connection hole 1010 penetrates the top dielectric layer 103, penetrates each even-numbered conductive layer 101 above the even-numbered conductive layer 101 closest to the base dielectric layer 2, and penetrates the spacer dielectric layer 102 between each even-numbered conductive layer 101. In each pair of adjacent even-numbered conductive layers 101, the orthographic projection of the even-numbered conductive layer 101 facing away from the base dielectric layer 2 on the surface of the base dielectric layer 2 falls within the orthographic projection of the even-numbered conductive layer 101 close to the base dielectric layer 2 on the surface of the base dielectric layer 2. At least one even-numbered conductive layer 101 has a partial exposed surface on the side facing away from the base dielectric layer 2 in the second connection hole 1010.

[0128] The second conductive structure 120 is located in the second connection hole 1010, and the second conductive structure 120 is electrically connected to the sidewalls of each even-numbered conductive layer 101 and the surface of each even-numbered conductive layer 101 exposed from the second connection hole 1010.

[0129] In some embodiments, the second conductive structure 120 includes a conductive body 112 (i.e., a second conductive body) and an adhesive layer 111 (i.e., a second adhesive layer). The conductive body 112 fills the second connection hole 1010. The adhesive layer 111 is located between the conductive body 112 and the inner wall of the second connection hole 1010.

[0130] The example shows that the conductive layer 101 has 6 layers. It is understood that in some other embodiments, the stacked capacitor may also include other multiple conductive layers 101, such as 3 layers, 4 layers, 5 layers, 7 layers, 8 layers, etc.

[0131] This application also provides a semiconductor device. The semiconductor device includes the stacked capacitor 100 as described above.

[0132] In some embodiments, the semiconductor device further includes a chip, and the stacked capacitor 100 is disposed outside the chip (e.g., on the surface of the chip or on the surface of the chip through other intermediate structural layers) or inside the chip.

[0133] The chips mentioned include, but are not limited to, high-performance chips such as CPU chips, GPU chips, FPGA chips, 5G modem chips, system-on-a-chip (SoC), power management chips (PMIC), and 2.5D / 3D chiplets.

[0134] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A stacked capacitor, characterized by, include: Base dielectric layer; A capacitor body located on a base dielectric layer, the capacitor body comprising multiple stacked conductive layers and spacer dielectric layers located between each adjacent pair of conductive layers; in each conductive layer, from the surface of the base dielectric layer toward the conductive layer farthest from the base dielectric layer, the multiple conductive layers comprise alternately arranged odd-numbered conductive layers and even-numbered conductive layers; wherein, the stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a first direction; each odd-numbered conductive layer is located in the first connection region and the conductive layer stack region, and each even-numbered conductive layer is located in the second connection region and the conductive layer stack region; A top dielectric layer is located on the side of the capacitor body that is away from the base dielectric layer. The first connection hole is located in the first connection area and is stepped. The first connection hole penetrates the top dielectric layer, penetrates each odd-numbered conductive layer above the odd-numbered conductive layer closest to the base dielectric layer, and penetrates the spacer dielectric layer between each odd-numbered conductive layer. In each pair of adjacent odd-numbered conductive layers, the orthographic projection of the odd-numbered conductive layer away from the base dielectric layer on the surface of the base dielectric layer falls into the orthographic projection of the odd-numbered conductive layer close to the base dielectric layer on the surface of the base dielectric layer. Furthermore, at least one of the odd-numbered conductive layers has a portion of its surface on the side away from the base dielectric layer exposed in the first connection hole. A first conductive structure is located in the first connecting hole, and the first conductive structure is electrically connected to the sidewalls of each odd-numbered conductive layer and the exposed surfaces of each odd-numbered conductive layer from the first connecting hole. The second connection hole is located in the second connection area and is stepped. The second connection hole penetrates the top dielectric layer, penetrates each even-numbered conductive layer above the even-numbered conductive layer closest to the base dielectric layer, and penetrates the spacer dielectric layer between each even-numbered conductive layer. In each pair of adjacent even-numbered conductive layers, the orthographic projection of the even-numbered conductive layer away from the base dielectric layer on the surface of the base dielectric layer falls within the orthographic projection of the even-numbered conductive layer close to the base dielectric layer on the surface of the base dielectric layer. Furthermore, at least one even-numbered conductive layer has a portion of its surface on the side away from the base dielectric layer exposed in the second connection hole. The second conductive structure is located in the second connection hole, and the second conductive structure is electrically connected to the sidewalls of each even-numbered conductive layer and the exposed surfaces of each even-numbered conductive layer from the second connection hole.

2. The stacked capacitor of claim 1, wherein, The first conductive structure includes a first conductive body and a first adhesive layer; the first conductive body fills the first connection hole; the first adhesive layer is located between the first conductive body and the inner wall of the first connection hole; and / or, The second conductive structure includes a second conductive body and a second adhesive layer; the second conductive body is filled in the second connection hole; the second adhesive layer is located between the second conductive body and the inner wall of the second connection hole.

3. The stacked capacitor of claim 1, wherein, Each of the conductive layers is a metal layer.

4. The stacked capacitor as described in claim 1, characterized in that, The thickness of each of the conductive layers is the same.

5. The stacked capacitor as described in claim 1, characterized in that, In each odd-numbered conductive layer, the odd-numbered conductive layer closest to the base dielectric layer is flat, and each other odd-numbered conductive layer includes a first flat portion, a second flat portion, and a first connecting portion connecting the first flat portion and the second flat portion; wherein the distance between the first flat portion and the base dielectric layer is less than the distance between the second flat portion and the base dielectric layer.

6. The stacked capacitor as described in claim 1, characterized in that, Each even-numbered conductive layer includes a third flat portion, a fourth flat portion, and a second connecting portion connecting the third flat portion and the fourth flat portion; wherein the distance between the third flat portion and the base dielectric layer is less than the distance between the fourth flat portion and the base dielectric layer.

7. The stacked capacitor as described in claim 1, characterized in that, The thickness of the conductive layer is 10nm-100nm.

8. The stacked capacitor as described in claim 1, characterized in that, In the conductive stack region, the thickness of the spacer dielectric layer located between two adjacent conductive layers is 5nm-50nm.

9. A semiconductor device, characterized in that, The semiconductor device includes a stacked capacitor as described in any one of claims 1 to 8.

10. The semiconductor device as claimed in claim 9, characterized in that, The semiconductor device further includes a chip, and the stacked capacitor is disposed outside the chip or inside the chip.

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