A stacked capacitor and semiconductor device

Abstract

This application provides a stacked capacitor and a semiconductor device. The stacked capacitor includes a base dielectric layer, a capacitor body, a top dielectric layer, and first and second conductive structures. The capacitor body includes stacked conductive layers and spacer dielectric layers located between adjacent conductive layers; the stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region; odd-numbered conductive layers are located in the first connection region and the conductive layer stack region, and even-numbered conductive layers are located in the second connection region and the conductive layer stack region; a first connection hole penetrates each odd-numbered conductive layer and each spacer dielectric layer through a first hole portion and a second hole portion recessed from the inner wall of each spacer dielectric layer in the first hole portion; a second connection hole penetrates each even-numbered conductive layer and each spacer dielectric layer through a third portion and a fourth hole portion recessed from the interior of each spacer dielectric layer in the second hole portion; a first conductive structure fills the first connection hole, and a second conductive structure fills the second connection hole.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a stacked capacitor and semiconductor device. Background Technology

[0002] Capacitors are one of the most fundamental and widely used passive components in integrated circuits. Common types of capacitors include metal-oxide-semiconductor (MOS) capacitors, PN junction capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and metal-insulator-metal (MIM) capacitors.

[0003] Among these capacitor types, MIM capacitors are typically manufactured in the back-end ofline (BEOL) process of integrated circuits, above the metal interconnect layer. This structure allows for a greater distance between the MIM capacitor and the silicon substrate, thus significantly reducing parasitic capacitance introduced by the substrate. Simultaneously, MIM capacitors exhibit good frequency stability and temperature characteristics, and their manufacturing process is highly compatible with current integrated circuit processes. For these reasons, MIM capacitors have become the mainstream capacitor technology in passive chip components.

[0004] As Moore's Law continues to advance, the demands on capacitor density in integrated circuits are increasing. High-density capacitors play a crucial role in high-performance computing chips (such as CPUs, GPUs, and FPGAs), mobile communication chips (such as 5G modems and system-on-a-chip (SoCs)), power management chips (PMICs), and advanced packaging fields like 2.5D / 3D chiplets. Currently, the most mainstream technology for implementing high-density capacitors in BEOLs (Block Arrays) is the use of MIM (Metal Injection Molding) capacitors with a stacked structure. Improving the performance of stacked capacitors has become a major focus. Summary of the Invention

[0005] This application provides a stacked capacitor, which includes: Base dielectric layer; A capacitor body is located on the base dielectric layer; the capacitor body includes multiple stacked conductive layers and spacer dielectric layers located between each adjacent pair of conductive layers; in each conductive layer, from the surface of the base dielectric layer toward the conductive layer farthest from the base dielectric layer, the multiple conductive layers include alternating odd-numbered conductive layers and even-numbered conductive layers; wherein, the stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a first direction; each odd-numbered conductive layer is located in the first connection region and the conductive layer stack region, and each even-numbered conductive layer is located in the second connection region and the conductive layer stack region; A top dielectric layer, which is located on the side of the capacitor body away from the base dielectric layer; The first connection hole is located in the first connection area and includes a first hole portion and a second hole portion that are connected. The first hole portion penetrates each odd-numbered conductive layer and each spacer dielectric layer, and the second hole portion is recessed from the inner wall of the spacer dielectric layer of the first hole portion. The second connection hole is located in the second connection area and includes a third hole and a fourth hole that are connected. The third hole penetrates each even-numbered conductive layer and each spacer dielectric layer, and the fourth hole is recessed from the interior of the second hole by each spacer dielectric layer. A first conductive structure is filled in the first connecting hole, and the first conductive structure is electrically connected to the sidewalls of each odd-numbered conductive layer and the surface of each odd-numbered conductive layer exposed from the second hole. The second conductive structure is filled in the second connecting hole and is electrically connected to the sidewalls of each even-numbered conductive layer and the exposed surfaces of each even-numbered conductive layer from the fourth hole.

[0006] In some embodiments, the first conductive structure includes a first conductive body and a first adhesive layer; the first adhesive layer is attached to the first hole and fills the second hole, the first conductive body fills the first connection hole, and the first adhesive layer is located between the first conductive body and the inner wall of the first connection hole.

[0007] In some embodiments, the second conductive structure includes a second conductive body and a second adhesive layer; the second adhesive layer is attached to the third hole and fills the fourth hole, the second conductive body is filled in the second connection hole, and the second adhesive layer is located between the second conductive body and the inner wall of the second connection hole.

[0008] In some embodiments, each of the conductive layers is a metal layer of the same material.

[0009] In some embodiments, among the odd-numbered conductive layers, the odd-numbered conductive layer closest to the base dielectric layer is flat, and the remaining odd-numbered conductive layers include a first flat portion, a second flat portion, and a first connecting portion connecting the first flat portion and the second flat portion; wherein the distance between the first flat portion and the base dielectric layer is less than the distance between the second flat portion and the base dielectric layer; the second flat portion is located in the conductive layer stack region, and at least a portion of the first flat portion is located in the first connecting region; Each even-numbered conductive layer includes a third flat portion, a fourth flat portion, and a second connecting portion connecting the third flat portion and the fourth flat portion; wherein the distance between the third flat portion and the base dielectric layer is less than the distance between the fourth flat portion and the base dielectric layer; the fourth flat portion is located in the conductive layer stack region, and at least a portion of the third flat portion is located in the second connecting region.

[0010] In some embodiments, the thickness of the conductive layer is 10 nm-100 nm; In the conductive stack region, the thickness of the spacer dielectric layer located between two adjacent conductive layers is 5nm-50nm.

[0011] In some embodiments, the depth of the second hole recess is 2-4 times the thickness of the spacer dielectric layer.

[0012] In some embodiments, the depth of the fourth hole recess is 2-4 times the thickness of the spacer dielectric layer.

[0013] This application also provides a semiconductor device, which includes stacked capacitors as described above.

[0014] In some embodiments, the semiconductor device further includes a chip, and the stacked capacitors are disposed outside the chip or inside the chip.

[0015] The main technical effects achieved by the embodiments of this application are: The stacked capacitor and semiconductor device provided in this application increase the contact area between each conductive structure and the connected conductive layer by configuring the first connection hole connecting each odd-numbered conductive layer as a first hole portion penetrating each odd-numbered conductive layer and the spacer dielectric layer and a second hole portion recessed from the inner wall of each spacer dielectric layer in the first hole portion, and configuring the second connection hole connecting each even-numbered conductive layer as a third hole portion penetrating each even-numbered conductive layer and the spacer dielectric layer and a fourth hole portion recessed from the inner wall of each spacer dielectric layer in the second hole portion. This increases the contact area between each conductive structure and the connected conductive layer, which helps to reduce contact resistance and improve the reliability of the stacked capacitor. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating a method for fabricating a stacked capacitor according to an exemplary embodiment of this application; Figures 2 to 9 These are structural diagrams corresponding to different processes used in fabricating stacked capacitors using an exemplary embodiment of this application. Figure 10 This is a top view of a stacked capacitor provided in an exemplary embodiment of this application; Figure 11 It is along Figure 10 The cross-sectional view of the stacked capacitors obtained by section line AA shown. Detailed Implementation

[0017] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0018] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture; if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0019] The following is in conjunction with the appendix Figures 1 to 11 The following describes some embodiments of this application in detail. Unless otherwise specified, the embodiments and features described below can be combined with each other.

[0020] Please refer to Figure 1 This application provides a method for fabricating stacked capacitors, which includes the following steps S10 to S50: In step S10, a base dielectric layer is provided; In step S20, a capacitor body is formed on the base dielectric layer. The capacitor body includes multiple stacked conductive layers and spacer dielectric layers located between each pair of adjacent conductive layers. In each conductive layer, from the surface of the base dielectric layer toward the conductive layer farthest from the base dielectric layer, the multiple conductive layers include alternating odd-numbered conductive layers and even-numbered conductive layers. The stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a first direction. Each odd-numbered conductive layer is located in the first connection region and the conductive layer stack region, and each even-numbered conductive layer is located in the second connection region and the conductive layer stack region. In step S30, a top dielectric layer is formed, which is located on the side of the capacitor body away from the base dielectric layer; In step S40, a first connecting hole and a second connecting hole are formed; the first connecting hole is located in the first connecting area and includes a first hole portion and a second hole portion that are connected; the first hole portion penetrates each odd-numbered conductive layer and each spacer dielectric layer, and the second hole portion is recessed from the inner wall of each spacer dielectric layer in the first hole portion; the second connecting hole is located in the second connecting area and includes a third hole portion and a fourth hole portion that are connected; the third hole portion penetrates each even-numbered conductive layer and each spacer dielectric layer, and the fourth hole portion is recessed from the interior of each spacer dielectric layer in the second hole portion; In step S50, a first conductive structure and a second conductive structure are formed; the first conductive structure fills the first connecting hole, the second conductive structure fills the second connecting hole, and the first conductive structure is electrically connected to the sidewalls of each odd-numbered conductive layer and the surface of each odd-numbered conductive layer exposed from the second hole; the second conductive structure is electrically connected to the sidewalls of each even-numbered conductive layer and the surface of each even-numbered conductive layer exposed from the fourth hole.

[0021] The following is combined with Figures 2 to 9 Taking a 6-layer conductive layer as an example, the fabrication method of the above-mentioned stacked capacitor will be described in detail. It is understood that the conductive layer can also be multiple layers, such as 3, 4, 5, 7, 8, etc.

[0022] In step S10, a base dielectric layer 2 is provided.

[0023] The material of the base dielectric layer 2 can be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride, to provide a platform for the subsequent manufacturing of stacked capacitors (and MIM stacked capacitors).

[0024] It is understood that the stacked capacitor can be a capacitor structure formed inside the chip or on the chip surface. In the implementation where the stacked capacitor is formed inside the chip or on the chip surface, the base dielectric layer 2 can also be used to isolate the previous metal interconnect structure in the back-end of line (BEOL) process, that is, to electrically isolate the stacked capacitor from the chip.

[0025] The base dielectric layer 2 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods.

[0026] The base dielectric layer 2 may have mutually opposing surfaces 21 and 22.

[0027] Combination Figures 2 to 4As shown, in step S20, a capacitor body 1 is formed on the base dielectric layer 2.

[0028] The capacitor body 1 is disposed on the surface 21 of the base dielectric layer 2.

[0029] The capacitor body 1 includes multiple stacked conductive layers 101 and spacer dielectric layers 102 located between each adjacent pair of conductive layers 101. In each conductive layer 101, from the surface of the base dielectric layer 2 towards the conductive layer 101 furthest from the base dielectric layer 2, i.e., in the thickness direction of the stacked capacitor (i.e., the second direction z), the multiple conductive layers 101 include alternating odd-numbered and even-numbered conductive layers. The stacked capacitor has a first connection region Q1, a conductive layer stack region Q2, and a second connection region Q3 arranged along the first direction x. Each odd-numbered conductive layer 101 is located in the first connection region Q1 and the conductive layer stack region Q2, and each even-numbered conductive layer 101 is located in the second connection region Q3 and the conductive layer stack region Q2.

[0030] The first direction x and the second direction z are perpendicular to each other. Of course, they can also have other non-zero angles.

[0031] Combination Figure 4 As shown, the capacitor body 1 includes multiple stacked layers: a first conductive layer 1011, a second conductive layer 1012, a third conductive layer 1013, a fourth conductive layer 1014, a fifth conductive layer 1015, and a sixth conductive layer 1016. A spacer dielectric layer 102 is formed between each adjacent pair of conductive layers 1011, 1012, 1013, 1014, 1015, and 1016. Figure 4 As shown, from the base dielectric layer 2 upwards, the spacer dielectric layer 102 includes a first spacer dielectric layer 1021, a second spacer dielectric layer 1022, a third spacer dielectric layer 1023, a fourth spacer dielectric layer 1024, and a fifth spacer dielectric layer 1025.

[0032] In the direction from the surface 21 of the base dielectric layer 2 toward the sixth conductive layer 1016, which is furthest from the base dielectric layer 2, the conductive layer 101 includes odd-numbered conductive layers such as the first conductive layer 1011, the third conductive layer 1013, and the fifth conductive layer 1015, and even-numbered conductive layers such as the second conductive layer 1012, the fourth conductive layer 1014, and the sixth conductive layer 1016.

[0033] Conductive material layers can be deposited layer by layer, and each layer can be patterned by etching to form the corresponding conductive layer 101. The following is a combination of... Figures 2 to 4 The formation of capacitor body 1 is described in detail.

[0034] Combination Figure 2 As shown, the first conductive layer 1011 is formed.

[0035] First, a first conductive material layer can be deposited on the base dielectric layer 2. A mask layer (such as photoresist) is set on the first conductive material layer, and the photoresist above the area to be etched is etched to form the required opening. The conductive material layer is patterned by etching, and after removing the mask layer, the first conductive layer 1011 is formed.

[0036] The first conductive material layer can be formed by deposition, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0037] The material of the first conductive layer 1011 can be a metallic material, such as aluminum. Of course, in some other embodiments, the material of the first conductive layer can also be selected from, but is not limited to, titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, zirconia, molybdenum, hafnium, and other etchable metals.

[0038] The thickness of the first conductive layer 1011 can be 5nm-100nm. For example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, and 100nm.

[0039] Combination Figure 3 As shown, a first spacer dielectric layer 1021 is then formed on the first conductive layer 1011.

[0040] The first spacer dielectric layer 1021 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods.

[0041] The first spacer dielectric layer 1021 covers the surface of the first conductive layer 1011 away from the base dielectric layer 2, covers the sidewall of the first conductive layer 1011 facing the second connection area Q3, and covers the area on the surface 21 of the base dielectric layer 2 exposed from the first conductive layer 1011.

[0042] The thickness of the first spacer dielectric layer 1021 is basically consistent in other areas except for the corner portion of the sidewall covering the conductive layer 101.

[0043] The material of the first spacer dielectric layer 1021 can be any one or more of the following materials: HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.

[0044] In some embodiments, the thickness of the first spacer dielectric layer 1021 can be 5nm-50nm. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0045] Continue to combine Figure 3 Then, a second conductive layer 1012 is formed on the first spacer dielectric layer 1021.

[0046] The second conductive layer 1012 can be configured in the same way as the first conductive layer 1011, as described above.

[0047] Combination Figure 4 As shown, a second spacer dielectric layer 1022, a third conductive layer 1013, a third spacer dielectric layer 1023, a fourth conductive layer 1014, a fourth spacer dielectric layer 1024, a fifth conductive layer 1015, a fifth spacer dielectric layer 1025, and a sixth conductive layer 1016 are sequentially disposed on the second conductive layer 1012, thereby forming the capacitor body 1.

[0048] It is understandable that the thickness of each conductive layer 101 can be the same. The thickness of each conductive layer 101 can be 5nm-100nm. For example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, and 100nm.

[0049] The material of each conductive layer 101 can be the same. For example, the material of each conductive layer 101 can be a metal, such as aluminum. Of course, in some other embodiments, the material of each conductive layer can also be selected from, but is not limited to, etchable metals such as titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, zirconia, molybdenum, and hafnium.

[0050] The thickness of each spacer dielectric layer 102 can be the same. The thickness of each spacer dielectric layer 102 can be 5nm-50nm. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0051] The materials of each spacer dielectric layer can be the same. For example, the materials of each spacer dielectric layer can be any one or more of the following materials: HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.

[0052] It is understood that in some other embodiments, the materials of the conductive layers may also be different. The thickness of each conductive layer 101 may also be different. The materials of each spacer dielectric layer 102 may also be different. The thickness of each spacer dielectric layer 102 may also be different.

[0053] like Figure 5 As shown, in step S30, a top dielectric layer 3 is formed, which is located on the side of the capacitor body 1 away from the base dielectric layer 2.

[0054] The material of the top dielectric layer 3 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride.

[0055] The top dielectric layer 3 is relatively thick, at least greater than the thickness of a single spacer dielectric layer. The thickness of the top dielectric layer 3 can be greater than the thickness of a single conductive layer.

[0056] For stacked capacitors that are away from the base dielectric layer 2 (which can be understood as the top of the stacked capacitors) and require the subsequent installation of other metal interconnect structures, the top dielectric layer 3 can be used to isolate the metal interconnect structures in the back-end ofline (BEOL) process on top of the stacked capacitors.

[0057] like Figure 6 and Figure 7 As shown, in step S40, a first connecting hole 1001 and a second connecting hole 1002 are formed.

[0058] The first connection hole 1001 is located in the first connection area Q1. The first connection hole 1001 includes a first hole portion 10011 and a second hole portion 10012 that are connected. The first hole portion 10011 penetrates each odd-numbered conductive layer 101 and each spacer dielectric layer 102, and the second hole portion 10012 is recessed into the inner wall of each spacer dielectric layer 102 in the first hole portion 10011. The conductive layers 101 on the upper and lower sides of the second hole portion 10012 can be exposed through the second hole portion 10012.

[0059] like Figure 6 and Figure 7 As shown, forming the first connection hole 1001 may include the following steps S41 and S42.

[0060] In step S41, the first hole 10011 is formed by etching in the first connection area Q1.

[0061] This step S41 can be performed using dry etching. Alternatively, physical etching can be used, such as plasma etching with inert gases like argon. Or, chemical-physical etching can be performed using Cl-type gases (such as Cl2, BCl3, etc.) or F-type gases (such as F2). In this step S41, the top dielectric layer 3, all odd-numbered conductive layers 101, and all spacer dielectric layers 102 can be etched in one step, directly etching down to the bottom dielectric layer 2. Figure 6 As shown. When etching to form the first hole 10011, the etching depth of the base dielectric layer 2 can be controlled within tens of nanometers, such as 5nm, 8nm, 10nm, 12nm, and 15nm.

[0062] The cross-sectional dimensions of the first hole 10011 can be several hundred nanometers. For example, the length of the cross-section of the first hole 10011 in the first direction x and the length in the third direction y can both be several hundred nanometers.

[0063] The first hole 10011 may be a rectangular opening. Of course, in other embodiments, the first hole 10011 may also be a regular or irregular shape with a circular, elliptical, or other similar cross-section.

[0064] The third direction y can be perpendicular to each other in pairs with the first direction x and the second direction z, or they can have other non-zero angles between them.

[0065] It is understandable that the etching gas in step S41 can be selected based on the specific materials of the conductive layer 101, the spacer dielectric layer 102, and the top dielectric layer 3.

[0066] In some other embodiments, etching can also be performed in stages, using etching gases adapted to the top dielectric layer 3, the odd-numbered conductive layers 101, and the spacer dielectric layers respectively to form the first hole 10011.

[0067] In step S42, the second hole 10012 is formed by further etching in the first hole 10011.

[0068] This step S42 can be etched using methods such as dry etching or wet etching. During etching in this step S42, depending on the materials of the conductive layer 101, the spacer dielectric layer 102, and the top dielectric layer 3, an etching gas or etching liquid capable of etching away the spacer dielectric layer 102 without etching the conductive layer 101 can be introduced into the first hole 10011 for etching.

[0069] In the case of dry etching, assuming the conductive layer 101 is made of Al and the spacer dielectric layer 102 is made of SiN, step S42 can use a Class F gas, which cannot be etched on Al, to dry etch the spacer dielectric layer 102 to form the second via 10012. Thus, in step S42, the etched spacer dielectric layer 102 exposed from the first via 10011 can be laterally etched by the Class F gas, while Al remains unetched, thereby forming the second via 10012.

[0070] Taking a wet etching process with TiN as the conductive layer 101 and Al2O3 as the spacer dielectric layer 102 as an example, considering that TiN can remain stable in dilute sulfuric acid and Al2O3 can dissolve in dilute sulfuric acid, in step S42, dilute sulfuric acid solution can be used to laterally etch the spacer dielectric layer 102 in the first hole 10011 to form the second hole 10012.

[0071] In step S42, the depth of the lateral etching spacer dielectric layer 102 depends on the pore-filling capability of the subsequent first conductive structure (such as the pore-filling capability of the first adhesive layer) to ensure good contact between the subsequent first conductive structure and the conductive layer.

[0072] In some embodiments, the depth D1 of the recess in the second hole 10012 can be 2-4 times the thickness of the spacer dielectric layer 102, so as to effectively increase the contact area between the conductive layer 101 and the subsequently disposed first conductive structure, and to ensure that the first conductive structure can be well filled in the second hole 10012, thereby ensuring the contact performance between the conductive layer 101 and the subsequently disposed first conductive structure.

[0073] The second connection hole 1002 is located in the second connection area Q3. The second connection hole 1002 includes a connected third hole portion 10021 and a fourth hole portion 10022. The third hole portion 10021 penetrates each even-numbered conductive layer 101 and each spacer dielectric layer 102, and the fourth hole portion 10022 is recessed from the spacer dielectric layer 102 inside the second hole portion 10012. The conductive layers 101 on the upper and lower sides of the fourth hole portion 10022 can be exposed from the fourth hole portion 10022.

[0074] like Figure 6 and Figure 7 As shown, forming the second connection hole 1002 may include the following steps S43 and S44.

[0075] In step S43, the third hole 10021 is formed by etching in the second connection area Q3.

[0076] This step S43 can be performed using dry etching. Alternatively, physical etching can be used, such as plasma etching with inert gases like argon. Or, chemical-physical etching can be performed using Cl-type gases (such as Cl2, BCl3, etc.) or F-type gases (such as F2). In this step S43, the top dielectric layer 3, all even-numbered conductive layers 101, and all spacer dielectric layers 102 can be etched in one step, directly etching down to the bottom dielectric layer 2. Figure 6 As shown. When etching to form the third hole 10021, the etching depth of the base dielectric layer 2 can be controlled within tens of nanometers, such as 5nm, 8nm, 10nm, 12nm, and 15nm.

[0077] The cross-sectional dimensions of the third hole 10021 can be several hundred nanometers. For example, the length of the cross-section of the third hole 10021 in the first direction x and the length in the third direction y can both be several hundred nanometers.

[0078] The third hole 10021 can be a rectangular opening. Of course, in other embodiments, the third hole 10021 can also be a regular or irregular shape with a circular, elliptical, or other similar cross-section.

[0079] It is understandable that the etching gas in step S43 can be selected based on the specific materials of the conductive layer 101, the spacer dielectric layer 102, and the top dielectric layer 3.

[0080] In some other embodiments, etching can also be performed in stages, using etching gases adapted to the top dielectric layer 3, the even-numbered conductive layers 101, and the spacer dielectric layers respectively to form the third hole 10021.

[0081] In step S44, the fourth hole 10022 is formed by further etching in the third hole 10021.

[0082] This step S44 can be etched using methods such as dry etching or wet etching. During etching in this step S44, depending on the materials of the conductive layer 101, the spacer dielectric layer 102, and the top dielectric layer 3, an etching gas or etching liquid capable of etching away the spacer dielectric layer 102 without etching the conductive layer 101 can be introduced into the third hole 10021 for etching.

[0083] In the case of dry etching, assuming the conductive layer 101 is made of Al and the spacer dielectric layer 102 is made of SiN, step S44 can use a Class F gas, which cannot be etched on Al, to dry etch the spacer dielectric layer 102 to form the fourth hole 10022. Thus, in step S44, the etched spacer dielectric layer 102 exposed from the third hole 10021 can be laterally etched by the Class F gas, while Al is not etched, thereby forming the fourth hole 10022.

[0084] Taking a wet etching process with TiN as the conductive layer 101 and Al2O3 as the spacer dielectric layer 102 as an example, considering that TiN can remain stable in dilute sulfuric acid and Al2O3 can dissolve in dilute sulfuric acid, in step S42, dilute sulfuric acid solution can be used to laterally etch the spacer dielectric layer 102 in the third hole 10021 to form the fourth hole 10022.

[0085] In step S44, the depth of the lateral etching spacer dielectric layer 102 depends on the pore-filling capability of the subsequent second conductive structure (such as the pore-filling capability of the second adhesive layer) to ensure good contact between the subsequent second conductive structure and the conductive layer.

[0086] In some embodiments, the depth D2 of the recess in the fourth hole 10022 can be 2-4 times the thickness of the spacer dielectric layer 102, so as to effectively increase the contact area between the conductive layer 101 and the subsequently disposed second conductive structure, and to ensure that the second conductive structure can be well filled in the fourth hole 10022, thereby ensuring the contact performance between the conductive layer 101 and the subsequently disposed second conductive structure.

[0087] In some embodiments, the first connection hole 1001 and the second connection hole 1002 are formed simultaneously.

[0088] The first hole 10011 and the third hole 10021 can be formed simultaneously, and the second hole 10012 and the fourth hole 10022 can be formed simultaneously. That is, steps S41 and S43 are performed simultaneously, and steps S44 and S42 are performed simultaneously.

[0089] It is understood that the etching of the first connection hole 1001 and the second connection hole 1002 can be achieved by first forming a mask layer (such as photoresist) on the surface of the top dielectric layer 3, and forming through holes corresponding to the first connection hole 1001 and the second connection hole 1002 respectively. In this way, the same mask layer 200 can be used to form the first connection hole 1001 and the second connection hole 1002.

[0090] It is understood that in some other embodiments, the first connecting hole and the second connecting hole may be formed asynchronously. The first connecting hole and the second connecting hole may also not be formed using the same mask layer for etching.

[0091] like Figure 8 and Figure 9As shown, in step S50, a first conductive structure 1201 and a second conductive structure 1202 are formed. The first conductive structure 1201 fills the first connecting hole 1001 and is electrically connected to the sidewalls of each odd-numbered conductive layer 101 and the exposed surfaces of each odd-numbered conductive layer 101 from the second hole portion 10012. The second conductive structure 1202 fills the second connecting hole 1002 and is electrically connected to the sidewalls of each even-numbered conductive layer 101 and the exposed surfaces of each even-numbered conductive layer 101 from the fourth hole portion 10022.

[0092] In some embodiments, forming the first conductive structure 1201 may include the following steps S51 and S52: like Figure 8 As shown, in step S51, a first adhesive layer 121 is formed, which is attached to the first hole 10011 and fills the second hole 10012.

[0093] The first adhesive layer 121 can be formed by atomic layer deposition (ALD) to achieve good coverage.

[0094] The first adhesive layer 121 can be made of a conductive material with good adhesion, such as Ti, TiN, Ta, or TaN. The first adhesive layer 121 can also serve as a seed layer and a barrier layer.

[0095] like Figure 9 As shown, in step S52, a first conductive body 122 is formed, the first conductive body 122 is filled in the first connection hole 1001, and the first adhesive layer 121 is located between the first conductive body 122 and the inner wall of the first connection hole 1001.

[0096] The material of the first conductive body 122 can be metals such as copper (Cu) or tungsten (W).

[0097] The first conductive body 122 can be produced by electroplating. After electroplating the first conductive body material on the first adhesive layer 121, chemical mechanical polishing (CMP) is performed to form a first conductive structure 1201 that is flush with the top dielectric layer 3.

[0098] The first conductive body 122 in the first connection hole 1001 and the first adhesive layer 121 together form the first conductive structure 1201.

[0099] In some embodiments, forming the second conductive structure 1202 may include the following steps S53 and S54: like Figure 8As shown, in step S53, a second adhesive layer 123 is formed, which is attached to the third hole 10021 and fills the fourth hole 10022.

[0100] The second adhesive layer 123 can be formed by atomic layer deposition (ALD) to achieve good coverage.

[0101] The second adhesive layer 123 can be made of a conductive material with good adhesion, such as Ti, TiN, Ta, or TaN. The second adhesive layer 123 can also serve as a seed layer and a barrier layer.

[0102] like Figure 9 As shown, in step S54, a second conductive body 124 is formed, the second conductive body 124 is filled in the second connection hole 1002, and the second adhesive layer 123 is located between the second conductive body 124 and the inner wall of the second connection hole 1002.

[0103] The material of the first conductive body 122 can be metals such as copper (Cu) or tungsten (W).

[0104] The second conductive body 124 can be formed by electroplating the first conductive body material onto the second adhesive layer 123 and then performing chemical mechanical polishing (CMP) to form a second conductive structure 1202 that is flush with the top dielectric layer 3.

[0105] The second conductive body 124 in the second connection hole 1002 and the second adhesive layer 123 together form the second conductive structure 1202.

[0106] It should be noted that, in some other embodiments, the first conductive structure and the second conductive structure may also be formed by directly filling the first conductive body and the second conductive body, respectively.

[0107] In some embodiments, the first conductive structure 1201 and the second conductive structure 1202 are formed simultaneously.

[0108] For both the first conductive structure and the second conductive bond having an adhesive layer and a conductive body, the first adhesive layer 121 and the second adhesive layer 123 are formed simultaneously, and the first conductive body 122 and the second conductive body 124 are formed simultaneously. That is, steps S51 and S53 are formed simultaneously, and steps S52 and S54 are formed simultaneously.

[0109] like Figure 8 As shown, an adhesive material layer 1210 can be formed first, and the thickness of the adhesive material layer 1210 on the surface of the top dielectric layer 3 facing away from the bottom dielectric layer 2 can be etched away. The first adhesive layer 121 and the second adhesive layer 123 can be formed simultaneously.

[0110] Of course, in some other embodiments, the first conductive structure and the second conductive structure may be formed asynchronously.

[0111] This application also provides a stacked capacitor, including a base dielectric layer 2, a capacitor body 1 located on the base dielectric layer 2, a top dielectric layer 3, a first connection hole 1001, a first conductive structure 1201, a second connection hole 1002, and a second conductive structure 1202.

[0112] The material of the base dielectric layer 2 can be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6). For example, silicon oxide, silicon nitride, or silicon oxynitride, etc., to provide a platform for the subsequent manufacturing of stacked capacitors (and MIM stacked capacitors).

[0113] It is understood that the stacked capacitor can be a capacitor structure formed inside the chip or on the chip surface. In the implementation where the stacked capacitor is formed inside the chip or on the chip surface, the base dielectric layer 2 can also be used to isolate the previous metal interconnect structure in the back-end of line (BEOL) process, that is, to electrically isolate the stacked capacitor from the chip.

[0114] The base dielectric layer 2 can be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods.

[0115] The base dielectric layer 2 may have mutually opposing surfaces 21 and 22.

[0116] The capacitor body 1 includes multiple stacked conductive layers 101 and spacer dielectric layers 102 located between each pair of adjacent conductive layers 101. Each conductive layer 101, from the surface of the base dielectric layer 2 towards the conductive layer 101 furthest from the base dielectric layer 2, includes alternating odd-numbered and even-numbered conductive layers 101. The stacked capacitor has a first connection region Q1, a conductive layer stack region Q2, and a second connection region Q3 arranged along a first direction x. Each odd-numbered conductive layer 101 is located in the first connection region Q1 and the conductive layer stack region Q2, and each even-numbered conductive layer 101 is located in the second connection region Q3 and the conductive layer stack region Q2.

[0117] Combination Figure 11As shown, the capacitor body 1 includes multiple stacked layers: a first conductive layer 1011, a second conductive layer 1012, a third conductive layer 1013, a fourth conductive layer 1014, a fifth conductive layer 1015, and a sixth conductive layer 1016. A spacer dielectric layer 102 is formed between each adjacent pair of conductive layers 1011, 1012, 1013, 1014, 1015, and 1016. Figure 4 As shown, from the base dielectric layer 2 upwards, the spacer dielectric layer 102 includes a first spacer dielectric layer 1021, a second spacer dielectric layer 1022, a third spacer dielectric layer 1023, a fourth spacer dielectric layer 1024, and a fifth spacer dielectric layer 1025.

[0118] In the direction from the surface 21 of the base dielectric layer 2 toward the sixth conductive layer 1016, which is furthest from the base dielectric layer 2, the conductive layer 101 includes odd-numbered conductive layers such as the first conductive layer 1011, the third conductive layer 1013, and the fifth conductive layer 1015, and even-numbered conductive layers such as the second conductive layer 1012, the fourth conductive layer 1014, and the sixth conductive layer 1016.

[0119] The conductive material layers can be deposited layer by layer and patterned by etching to form the corresponding conductive layers 101.

[0120] In some embodiments, the conductive layer 101 may be made of a metallic material, such as aluminum. Of course, in other embodiments, the material of each conductive layer may also be selected from, but is not limited to, etchable metals such as titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, zirconia, molybdenum, and hafnium.

[0121] In some embodiments, the thickness of the conductive layer 101 can be 10nm-100nm. For example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm.

[0122] In some embodiments, the material of the spacer dielectric layer 102 may be any one or more mixed materials selected from, but not limited to, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0123] In some embodiments, the thickness of the spacer dielectric layer 102 located between two adjacent conductive layers 101 in the conductive stack region Q2 is 5nm-50nm. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0124] It is understandable that the thickness of the spacer dielectric layer 102 can be 5nm-50nm in each region. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0125] It is understood that the materials of each conductive layer can be the same or different. The thickness of each conductive layer 101 can be the same or different. The materials of each spacer dielectric layer 102 can be the same or different. The thickness of each spacer dielectric layer 102 can be the same or different. When all the conductive layers 101 are metal layers of the same material, it facilitates the one-step etching formation of the first connecting hole and the second connecting hole.

[0126] In some embodiments, among the odd-numbered conductive layers 101, the odd-numbered conductive layer 101 closest to the base dielectric layer 2 is flat, and the remaining odd-numbered conductive layers 101 include a first flat portion, a second flat portion, and a first connecting portion connecting the first flat portion and the second flat portion; wherein the distance between the first flat portion and the base dielectric layer 2 is less than the distance between the second flat portion and the base dielectric layer 2; the second flat portion is located in the conductive layer stack region Q2, and at least a portion of the first flat portion is located in the first connecting region Q1.

[0127] For example, the third conductive layer 1013 includes a first flat portion 10131, a second flat portion 10132, and a first connecting portion 10133. The second flat portion 10132 is higher than the first flat portion 10131.

[0128] Each even-numbered conductive layer 101 includes a third flat portion, a fourth flat portion, and a second connecting portion connecting the third flat portion and the fourth flat portion; wherein the distance between the third flat portion and the base dielectric layer 2 is less than the distance between the fourth flat portion and the base dielectric layer 2; the fourth flat portion is located in the conductive layer stack region Q2, and at least a portion of the third flat portion is located in the second connecting region Q3.

[0129] For example, the second conductive layer 1012 includes a third flat portion 10121, a fourth flat portion 10122, and a second connecting portion 10123. The fourth flat portion 10122 is higher than the third flat portion 10121.

[0130] It is understandable that the first spacer dielectric layer 1021 has a consistent thickness in all areas except for the corner portion of the sidewall covering the conductive layer 101.

[0131] Except at the connection portion, the thickness of the same conductive layer 101 is consistent in all straight portions.

[0132] The top dielectric layer 3 is located on the side of the capacitor body 1 that is away from the base dielectric layer 2.

[0133] The material of the top dielectric layer 3 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride.

[0134] The top dielectric layer 3 is relatively thick, at least greater than the thickness of a single spacer dielectric layer. The thickness of the top dielectric layer 3 can be greater than the thickness of a single conductive layer.

[0135] For stacked capacitors that are away from the base dielectric layer 2 (which can be understood as the top of the stacked capacitors) and require the subsequent installation of other metal interconnect structures, the top dielectric layer 3 can be used to isolate the metal interconnect structures in the back-end ofline (BEOL) process on top of the stacked capacitors.

[0136] The first connection hole 1001 is located in the first connection area Q1 and includes a first hole portion 10011 and a second hole portion 10012 that are connected. The first hole portion 10011 penetrates each odd-numbered conductive layer 101 and each spacer dielectric layer 102, and the second hole portion 10012 is recessed into the inner wall of each spacer dielectric layer 102 of the first hole portion 10011. The conductive layers 101 on the upper and lower sides of the second hole portion 10012 can be exposed through the second hole portion 10012.

[0137] In some embodiments, the depth D1 of the recess in the second hole 10012 can be 2-4 times the thickness of the spacer dielectric layer 102, so as to effectively increase the contact area between the conductive layer 101 and the subsequently disposed first conductive structure, and to ensure that the first conductive structure can be well filled in the second hole 10012, thereby ensuring the contact performance between the conductive layer 101 and the subsequently disposed first conductive structure.

[0138] The second connection hole 1002 is located in the second connection area Q3 and includes a connected third hole portion 10021 and a fourth hole portion 10022. The third hole portion 10021 penetrates each even-numbered conductive layer 101 and each spacer dielectric layer 102. The fourth hole portion 10022 is recessed into the second hole portion 10012 from each spacer dielectric layer 102. The conductive layers 101 on the upper and lower sides of the fourth hole portion 10022 can be exposed from the fourth hole portion 10022.

[0139] In some embodiments, the depth D2 of the recess in the fourth hole 10022 can be 2-4 times the thickness of the spacer dielectric layer 102, so as to effectively increase the contact area between the conductive layer 101 and the subsequently disposed second conductive structure, and to ensure that the second conductive structure can be well filled in the fourth hole 10022, thereby ensuring the contact performance between the conductive layer 101 and the subsequently disposed second conductive structure.

[0140] The first conductive structure 1201 is filled in the first connection hole 1001, and the first conductive structure 1201 is electrically connected to the sidewalls of each odd-numbered conductive layer 101 and the surface of each odd-numbered conductive layer 101 exposed from the second hole portion 10012.

[0141] The second conductive structure 1202 is filled in the second connection hole 1002, and the second conductive structure 1202 is electrically connected to the sidewalls of each even-numbered conductive layer 101 and the surface of each even-numbered conductive layer 101 exposed from the fourth hole 10022.

[0142] The first conductive structure 1201 includes a first conductive body 122 and a first adhesive layer 121; the first adhesive layer 121 is attached to the first hole 10011 and fills the second hole 10012, the first conductive body 122 is filled in the first connecting hole 1001, and the first adhesive layer 121 is located between the first conductive body 122 and the inner wall of the first connecting hole 1001.

[0143] The first adhesive layer 121 can be made of a conductive material with good adhesion, such as Ti, TiN, Ta, or TaN. The first adhesive layer 121 can also serve as a seed layer and a barrier layer.

[0144] The material of the first conductive body 122 can be metals such as copper (Cu) or tungsten (W).

[0145] The second conductive structure 1202 includes a second conductive body 124 and a second adhesive layer 123. The second adhesive layer 123 is attached to the third hole 10021 and fills the fourth hole 10022. The second conductive body 124 fills the second connecting hole 1002. The second adhesive layer 123 is located between the second conductive body 124 and the inner wall of the second connecting hole 1002.

[0146] The second adhesive layer 123 can be made of a conductive material with good adhesion, such as Ti, TiN, Ta, or TaN. The second adhesive layer 123 can also serve as a seed layer and a barrier layer.

[0147] The material of the second conductive body 124 can be metals such as copper (Cu) or tungsten (W).

[0148] It should be noted that in some other embodiments, the first conductive structure and the second conductive structure may also include only the first conductive body and the second conductive body, respectively.

[0149] The example shows that the conductive layer 101 has 6 layers. It is understood that in some other embodiments, the stacked capacitor may also include other multiple conductive layers 101, such as 3 layers, 4 layers, 5 layers, 7 layers, 8 layers, etc.

[0150] It should be noted that the first connection area Q1 may be provided with one or more first connection holes 1001 to provide multiple first conductive structures 1201. Compared with providing a single first connection hole 1001, providing multiple first connection holes 1001 can increase the contact area between the first conductive structure 1201 and the conductive layer, reduce contact resistance, and improve capacitance performance. The second connection area Q3 may be provided with one or more second connection holes 1002 to provide multiple second conductive structures 1202. Compared with providing a single second connection hole 1002, providing multiple second connection holes 1002 can increase the contact area between the second conductive structure 1202 and the conductive layer, reduce contact resistance, and improve capacitance performance.

[0151] This application also provides a semiconductor device. The semiconductor device includes the stacked capacitor 100 as described above.

[0152] In some embodiments, the semiconductor device further includes a chip, and the stacked capacitor 100 is disposed outside the chip (e.g., on the surface of the chip or on the surface of the chip through other intermediate structural layers) or inside the chip.

[0153] The chips mentioned include, but are not limited to, high-performance chips such as CPU chips, GPU chips, FPGA chips, 5G modem chips, system-on-a-chip (SoC), power management chips (PMIC), and 2.5D / 3D chiplets.

[0154] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A stacked capacitor, characterized by, include: Base dielectric layer; A capacitor body is located on the base dielectric layer; the capacitor body includes multiple stacked conductive layers and spacer dielectric layers located between each adjacent pair of conductive layers; in each conductive layer, from the surface of the base dielectric layer toward the conductive layer farthest from the base dielectric layer, the multiple conductive layers include alternating odd-numbered conductive layers and even-numbered conductive layers; wherein, the stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a first direction; each odd-numbered conductive layer is located in the first connection region and the conductive layer stack region, and each even-numbered conductive layer is located in the second connection region and the conductive layer stack region; A top dielectric layer, which is located on the side of the capacitor body away from the base dielectric layer; The first connection hole is located in the first connection area and includes a first hole portion and a second hole portion that are connected. The first hole portion penetrates each odd-numbered conductive layer and each spacer dielectric layer, and the second hole portion is recessed from the inner wall of the spacer dielectric layer of the first hole portion. The second connection hole is located in the second connection area and includes a third hole and a fourth hole that are connected. The third hole penetrates each even-numbered conductive layer and each spacer dielectric layer, and the fourth hole is recessed from the interior of the second hole by each spacer dielectric layer. A first conductive structure is filled in the first connecting hole, and the first conductive structure is electrically connected to the sidewalls of each odd-numbered conductive layer and the surface of each odd-numbered conductive layer exposed from the second hole. The second conductive structure is filled in the second connecting hole and is electrically connected to the sidewalls of each even-numbered conductive layer and the exposed surfaces of each even-numbered conductive layer from the fourth hole.

2. The stacked capacitor of claim 1, wherein, The first conductive structure includes a first conductive body and a first adhesive layer; the first adhesive layer is attached to the first hole and fills the second hole, the first conductive body fills the first connection hole, and the first adhesive layer is located between the first conductive body and the inner wall of the first connection hole.

3. The stacked capacitor of claim 1, wherein, The second conductive structure includes a second conductive body and a second adhesive layer; the second adhesive layer is attached to the third hole and fills the fourth hole, the second conductive body is filled in the second connecting hole, and the second adhesive layer is located between the second conductive body and the inner wall of the second connecting hole.

4. The stacked capacitor of claim 1, wherein, Each of the conductive layers is a metal layer made of the same material.

5. The stacked capacitor as described in claim 1, characterized in that, In each odd-numbered conductive layer, the odd-numbered conductive layer closest to the base dielectric layer is flat, and the remaining odd-numbered conductive layers include a first flat portion, a second flat portion, and a first connecting portion connecting the first flat portion and the second flat portion; wherein the distance between the first flat portion and the base dielectric layer is less than the distance between the second flat portion and the base dielectric layer; the second flat portion is located in the conductive layer stack region, and at least a portion of the first flat portion is located in the first connecting region; Each even-numbered conductive layer includes a third flat portion, a fourth flat portion, and a second connecting portion connecting the third flat portion and the fourth flat portion; wherein the distance between the third flat portion and the base dielectric layer is less than the distance between the fourth flat portion and the base dielectric layer; the fourth flat portion is located in the conductive layer stack region, and at least a portion of the third flat portion is located in the second connecting region.

6. The stacked capacitor as described in claim 1, characterized in that, The thickness of the conductive layer is 10nm-100nm; In the conductive stack region, the thickness of the spacer dielectric layer located between two adjacent conductive layers is 5nm-50nm.

7. The stacked capacitor as described in claim 1, characterized in that, The depth of the second hole is 2-4 times the thickness of the spacer dielectric layer.

8. The stacked capacitor as described in claim 1, characterized in that, The depth of the fourth hole recess is 2-4 times the thickness of the spacer dielectric layer.

9. A semiconductor device, characterized in that, The semiconductor device includes a stacked capacitor as described in any one of claims 1 to 8.

10. The semiconductor device as claimed in claim 9, characterized in that, The semiconductor device further includes a chip, and the stacked capacitor is disposed outside the chip or inside the chip.

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