A stacked capacitor and semiconductor device

Abstract

This application provides a stacked capacitor and a semiconductor device. The stacked capacitor includes a base dielectric layer, a capacitor body, a top dielectric layer, and first and second conductive structures; the capacitor body includes stacked conductive layers and spacer dielectric layers located between adjacent conductive layers; the stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region; odd-numbered conductive layers are located in the first connection region and the conductive layer stack region, and even-numbered conductive layers are located in the second connection region and the conductive layer stack region; each pair of adjacent conductive layers is made of a different material; a first connection hole penetrates each odd-numbered conductive layer and each spacer dielectric layer; a second connection hole penetrates each even-numbered conductive layer and each spacer dielectric layer; a first conductive structure fills the first connection hole, and a second conductive structure fills the second connection hole.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a stacked capacitor and semiconductor device. Background Technology

[0002] Capacitors are among the most fundamental and widely used passive components in integrated circuits. Common capacitor types include metal-oxide-semiconductor (MOS) capacitors, PN junction capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and metal-insulator-metal (MIM) capacitors. Among these types, MIM capacitors are typically manufactured in the back-end of line (BEOL) process of integrated circuits, above the metal interconnect layer. This structure allows for a greater distance between the MIM capacitor and the silicon substrate, significantly reducing parasitic capacitance introduced by the substrate. Simultaneously, MIM capacitors possess excellent frequency stability and temperature characteristics, and their manufacturing process is highly compatible with current integrated circuit technologies. Therefore, MIM capacitors have become the mainstream capacitor technology among passive components in chips. With the continuous advancement of Moore's Law, the requirements for capacitor density in integrated circuits are increasing daily. High-density capacitors play a crucial role in various applications, including high-performance computing chips (such as CPU chips, GPU chips, and FPGA chips), mobile communication chips (such as 5G modem chips and system-on-a-chip (SoC)), power management chips (PMIC), and advanced packaging fields like 2.5D / 3D chiplets. Currently, the most mainstream technology for implementing high-density capacitors in BEOL (Block Array of Electrode Components) is the use of MIM (Metal Injection Molding) capacitors with a stacked structure. Improving the performance of stacked capacitors has become a major focus. Summary of the Invention

[0003] This application embodiment provides a stacked capacitor, the stacked capacitor comprising: Base dielectric layer; A capacitor body is located on the base dielectric layer; the capacitor body includes multiple stacked conductive layers and spacer dielectric layers located between each adjacent pair of conductive layers; in each conductive layer, from the surface of the base dielectric layer toward the conductive layer farthest from the base dielectric layer, the multiple conductive layers include alternating odd-numbered conductive layers and even-numbered conductive layers; wherein the stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a first direction; each odd-numbered conductive layer is located in the first connection region and the conductive layer stack region, and each even-numbered conductive layer is located in the second connection region and the conductive layer stack region; wherein each adjacent pair of conductive layers is made of a different material.

[0004] A top dielectric layer, which is located on the side of the capacitor body away from the base dielectric layer; The first connection hole is located in the first connection area and penetrates each odd-numbered conductive layer and each spaced dielectric layer; The second connection hole is located in the second connection area and penetrates each even-numbered conductive layer and each spacer dielectric layer; A first conductive structure is filled in the first connecting hole, and the first conductive structure is electrically connected to the sidewalls of each odd-numbered conductive layer. The second conductive structure is filled in the second connecting hole and is electrically connected to the sidewalls of each even-numbered conductive layer.

[0005] In some embodiments, the first conductive structure includes a first conductive body and a first adhesive layer; the first adhesive layer is attached to the inner wall of the first connection hole, the first conductive body is filled in the first connection hole, and the first adhesive layer is located between the first conductive body and the inner wall of the first connection hole.

[0006] In some embodiments, the second conductive structure includes a second conductive body and a second adhesive layer; the second adhesive layer is attached to the inner wall of the second connection hole, the second conductive body is filled in the second connection hole, and the second adhesive layer is located between the second conductive body and the inner wall of the second connection hole.

[0007] In some embodiments, the conductive layer material of each odd-numbered layer is the same, and the conductive material of each even-numbered layer is the same.

[0008] In some embodiments, among the odd-numbered conductive layers, the odd-numbered conductive layer closest to the base dielectric layer is flat, and the remaining odd-numbered conductive layers include a first flat portion, a second flat portion, and a first connecting portion connecting the first flat portion and the second flat portion; wherein the distance between the first flat portion and the base dielectric layer is less than the distance between the second flat portion and the base dielectric layer; the second flat portion is located in the conductive layer stack region, and at least a portion of the first flat portion is located in the first connecting region.

[0009] In some embodiments, each even-numbered conductive layer includes a third flat portion, a fourth flat portion, and a second connecting portion connecting the third flat portion and the fourth flat portion; wherein the distance between the third flat portion and the base dielectric layer is less than the distance between the fourth flat portion and the base dielectric layer; the fourth flat portion is located in the conductive layer stack region, and at least a portion of the third flat portion is located in the second connecting region.

[0010] In some embodiments, the thickness of the conductive layer is 10nm-100nm.

[0011] In some embodiments, in the conductive stack region, the thickness of the spacer dielectric layer located between two adjacent conductive layers is 5 nm-50 nm.

[0012] This application also provides a semiconductor device, which includes stacked capacitors as described above.

[0013] In some embodiments, the semiconductor device further includes a chip, and the stacked capacitors are disposed outside the chip or inside the chip.

[0014] The main technical effects achieved by the embodiments of this application are: The stacked capacitors and semiconductor devices provided in this application have different materials for each pair of adjacent conductive layers. This makes it less likely to damage the conductive layers formed by the previous etching process when etching to form conductive layers other than the conductive layer closest to the base dielectric layer, which is beneficial to improving the performance of the stacked capacitors. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating a method for fabricating a stacked capacitor according to an exemplary embodiment of this application; Figures 2 to 7 This is a structural diagram corresponding to different processes for preparing a stacked capacitor using an exemplary embodiment of this application. Figures 8 to 11 This is a structural diagram corresponding to different processes for preparing another stacked capacitor using a stacked capacitor preparation method provided in an exemplary embodiment of this application; Figures 12 to 19 This is a cross-sectional view of a structure corresponding to a different process for preparing another stacked capacitor using a stacked capacitor preparation method provided in an exemplary embodiment of this application. Detailed Implementation

[0016] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0017] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture; if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0018] The following is in conjunction with the appendix Figures 1 to 19 The present application provides a detailed description of some embodiments. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0019] Please refer to Figure 1 This application provides a method for fabricating stacked capacitors, which includes the following steps S10 to S50: In step S10, a base dielectric layer is provided; In step S20, a capacitor body is formed on the base dielectric layer. The capacitor body includes multiple stacked conductive layers and spacer dielectric layers located between each pair of adjacent conductive layers. In each conductive layer, from the surface of the base dielectric layer toward the conductive layer furthest from the base dielectric layer, the multiple conductive layers include alternating odd-numbered and even-numbered conductive layers. The stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a first direction. Each odd-numbered conductive layer is located in the first connection region and the conductive layer stack region, and each even-numbered conductive layer is located in the second connection region and the conductive layer stack region. Each conductive layer is formed using an etching process. When etching each conductive layer other than the conductive layer closest to the base dielectric layer, the spacer dielectric layer below the etched conductive layer is used as the etching stop layer, or the conductive layer formed in the previous etching process is used as the etching stop layer. In step S30, a top dielectric layer is formed, which is located on the side of the capacitor body away from the base dielectric layer; In step S40, a first connection hole and a second connection hole are formed; the first connection hole is located in the first connection area and penetrates each odd-numbered conductive layer and each spacer dielectric layer; the second connection hole is located in the second connection area and penetrates each even-numbered conductive layer and each spacer dielectric layer. In step S50, a first conductive structure and a second conductive structure are formed; the first conductive structure fills the first connecting hole, the second conductive structure fills the second connecting hole, the first conductive structure is electrically connected to the sidewalls of each odd-numbered conductive layer, and the second conductive structure is electrically connected to the sidewalls of each even-numbered conductive layer.

[0020] The following is combined Figures 2 to 19 Taking a 4-layer conductive layer as an example, the fabrication method of the above-mentioned stacked capacitor will be described in detail. It is understood that the conductive layer can also be multiple layers, such as 3, 5, 6, 7, 8 layers, etc.

[0021] First, combine Figures 2 to 7 The method for fabricating the stacked capacitor described above is illustrated. Wherein, Figures 2 to 6 These are cross-sectional views corresponding to different processes used in fabricating a stacked capacitor 100 according to an exemplary embodiment of this application. Figure 7 This is a top view of a stacked capacitor provided in an exemplary embodiment of this application. Wherein, Figure 6 For along Figure 7 The sectional view obtained by section line AA shown.

[0022] In step S10, a base dielectric layer 2 is provided.

[0023] The material of the base dielectric layer 2 can be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride, to provide a platform for the subsequent manufacturing of stacked capacitors (and MIM stacked capacitors).

[0024] It is understood that the stacked capacitor can be a capacitor structure formed inside the chip or on the chip surface. In the implementation where the stacked capacitor is formed inside the chip or on the chip surface, the base dielectric layer 2 can also be used to isolate the previous metal interconnect structure in the back-end of line (BEOL) process, that is, to electrically isolate the stacked capacitor from the chip.

[0025] The base dielectric layer 2 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods.

[0026] The base dielectric layer 2 may have mutually opposing surfaces 21 and 22.

[0027] Combination Figures 2 to 4 As shown, in step S20, a capacitor body 1 is formed on the base dielectric layer 2.

[0028] The capacitor body 1 is disposed on the surface 21 of the base dielectric layer 2.

[0029] The capacitor body 1 includes multiple stacked conductive layers 101 and spacer dielectric layers 102 located between each adjacent pair of conductive layers 101. In each conductive layer 101, from the surface of the base dielectric layer 2 towards the conductive layer 101 furthest from the base dielectric layer 2, i.e., in the thickness direction of the stacked capacitor (i.e., the second direction z), the multiple conductive layers 101 include alternating odd-numbered and even-numbered conductive layers. The stacked capacitor has a first connection region Q1, a conductive layer stack region Q2, and a second connection region Q3 arranged along the first direction x. Each odd-numbered conductive layer 101 is located in the first connection region Q1 and the conductive layer stack region Q2, and each even-numbered conductive layer 101 is located in the second connection region Q3 and the conductive layer stack region Q2. Each conductive layer 101 is formed by an etching process. When etching each conductive layer 101 other than the conductive layer 101 closest to the base dielectric layer 2, the spacer dielectric layer 102 below the etched conductive layer 101 is used as the etching stop layer.

[0030] The first direction x and the second direction z are perpendicular to each other. Of course, they can also have other non-zero angles.

[0031] Combination Figure 4 As shown, the capacitor body 1 includes multiple stacked layers: a first conductive layer 1011, a second conductive layer 1012, a third conductive layer 1013, and a fourth conductive layer 1014. A spacer dielectric layer 102 is formed between each adjacent pair of conductive layers 1011, 1012, 1013, and 1014. Figure 4 As shown, the spacer dielectric layer 102 includes a first spacer dielectric layer 1021, a second spacer dielectric layer 1022, and a third spacer dielectric layer 1023.

[0032] In the direction from the surface 21 of the base dielectric layer 2 toward the fourth conductive layer 1014 which is furthest from the base dielectric layer 2, the conductive layer 101 includes odd-numbered conductive layers such as the first conductive layer 1011 and the third conductive layer 1013, and even-numbered conductive layers such as the second conductive layer 1012 and the fourth conductive layer 1014.

[0033] Conductive material layers can be deposited layer by layer, and each layer can be patterned by etching to form the corresponding conductive layer 101. The following is a combination of... Figures 2 to 4 The formation of capacitor body 1 is described in detail.

[0034] Combination Figure 2 As shown, the first conductive layer 1011 is formed.

[0035] First, a first conductive material layer can be deposited on the base dielectric layer 2. A mask layer (such as photoresist) is set on the first conductive material layer, and the photoresist above the area to be etched is etched to form the required opening. The conductive material layer is patterned by etching, and after removing the mask layer, the first conductive layer 1011 is formed.

[0036] In this etching step, dry etching can be used to pattern the conductive material layer. During etching, the base dielectric layer 2 can be used as the etching stop layer, so that the base dielectric layer 2 will not be etched or damaged.

[0037] The first conductive material layer can be formed by deposition, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0038] The first conductive layer 1011 can be made of metallic materials, such as titanium, chromium, nickel, tungsten, ruthenium, gypsum, molybdenum, hafnium, and other metals that can be etched by fluorine gases.

[0039] When TiN is used as the material of the first conductive layer, fluorine gas can be selected to etch the conductive material layer to form the first conductive layer 1011.

[0040] The thickness of the first conductive layer 1011 can be 5nm-100nm. For example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, and 100nm.

[0041] Combination Figure 3 As shown, a first spacer dielectric layer 1021 is then formed on the first conductive layer 1011.

[0042] The first spacer dielectric layer 1021 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods.

[0043] The first spacer dielectric layer 1021 covers the surface of the first conductive layer 1011 away from the base dielectric layer 2, covers the sidewall of the first conductive layer 1011 facing the second connection area Q3, and covers the area on the surface 21 of the base dielectric layer 2 exposed from the first conductive layer 1011.

[0044] The thickness of the first spacer dielectric layer 1021 is basically consistent in other areas except for the corner portion of the sidewall covering the conductive layer 101.

[0045] In some embodiments, the thickness of the first spacer dielectric layer 1021 can be 5nm-50nm. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0046] The material of the first spacer dielectric layer 1021 can be selected from materials that are not etched during the etching process to form the conductive layer 101. For example, Al2O3, which is difficult to etch with fluorine gases, or at least one of Al2O3 and HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, SrTiO3, and BaSrTiO can be selected. The first spacer dielectric layer 1021 formed can be an Al2O3 film layer, or a hybrid module formed by mixing Al2O3 with at least one of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, SrTiO3, and BaSrTiO, or a multilayer film layer formed by stacking Al2O3 film layers with at least one of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, SrTiO3, and BaSrTiO. For example, a layer of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, and HfTiO can be sandwiched between two Al2O3 film layers. A film formed from at least one of the following materials: Ta2O5, ZrO2, ZrSiO2, SrTiO3, and BaSrTiO.

[0047] Continue to combine Figure 3 Then, a second conductive layer 1012 is formed on the first spacer dielectric layer 1021.

[0048] The second conductive layer 1012 can be configured similarly to the first conductive layer 1011. A conductive material layer can be first deposited on the first spacer dielectric layer 1021, and the second conductive layer 1012 can be formed by etching. When etching the second conductive layer 1012, the first spacer dielectric layer 1021 is used as the etching stop layer.

[0049] Combination Figure 4 As shown, a second spacer dielectric layer 1022, a third conductive layer 1013, a third spacer dielectric layer 1023, and a fourth conductive layer 1014 are sequentially disposed on the second conductive layer 1012, thereby forming the capacitor body 1.

[0050] It is understandable that when etching to form the third conductive layer 1013, the second spacer dielectric layer 1022 is used as the etching stop layer. When etching to form the fourth conductive layer 1014, the third spacer dielectric layer 1023 is used as the etching stop layer.

[0051] It is understandable that the thickness of each conductive layer 101 can be the same. The thickness of each conductive layer 101 can be 5nm-100nm. For example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, and 100nm.

[0052] The material of each conductive layer 101 can be the same. For example, the material of each conductive layer 101 can be titanium, chromium, nickel, tungsten, ruthenium, gypsum, molybdenum, hafnium titanium, aluminum, chromium, nickel, tungsten, ruthenium, gypsum, molybdenum, hafnium, etc., which can be etched by fluorine gases.

[0053] The thickness of each spacer dielectric layer 102 can be the same. The thickness of each spacer dielectric layer 102 can be 5nm-50nm. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0054] The material of each spacer dielectric layer 102 can be the same. The material of each spacer dielectric layer can be referred to the relevant description of the first spacer dielectric layer 1021 above.

[0055] It is understood that in some other embodiments, the materials of the conductive layers may also be different. The thickness of each conductive layer 101 may also be different. The materials of each spacer dielectric layer 102 may also be different. The thickness of each spacer dielectric layer 102 may also be different.

[0056] like Figure 5 As shown, in step S30, a top dielectric layer 3 is formed. The top dielectric layer 3 is located on the side of the capacitor body 1 opposite to the base dielectric layer 2.

[0057] The material of the top dielectric layer 3 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride.

[0058] The top dielectric layer 3 is relatively thick, at least greater than the thickness of a single spacer dielectric layer. The thickness of the top dielectric layer 3 can be greater than the thickness of a single conductive layer.

[0059] For stacked capacitors that are away from the base dielectric layer 2 (which can be understood as the top of the stacked capacitors) and require the subsequent installation of other metal interconnect structures, the top dielectric layer 3 can be used to isolate the metal interconnect structures in the back-end ofline (BEOL) process on top of the stacked capacitors.

[0060] In step S40, a first connecting hole 1001 and a second connecting hole 1002 are formed.

[0061] The first connection hole 1001 is located in the first connection area Q1. The first connection hole 1001 penetrates each odd-numbered conductive layer 101 and each spacer dielectric layer 102.

[0062] This step S40 can be performed using dry etching. Alternatively, physical etching can be used, such as plasma etching with inert gases like argon. Or, chemical-physical etching can be performed using Cl-type gases (such as Cl2, BCl3, etc.) or F-type gases (such as F2). In this step S41, the top dielectric layer 3, all odd-numbered conductive layers 101, and all spacer dielectric layers 102 can be etched in one step, directly etching down to the bottom dielectric layer 2. When etching to form the first interconnect 1001, the etching depth of the bottom dielectric layer 2 can be controlled within tens of nanometers, such as 5nm, 8nm, 10nm, 12nm, or 15nm.

[0063] The cross-sectional dimensions of the first connecting hole 1001 can be several hundred nanometers. For example, the length of the cross-section of the first connecting hole 1001 in the first direction x and the length in the third direction y can both be several hundred nanometers.

[0064] The first connecting hole 1001 can be a rectangular opening. Of course, in other embodiments, the first connecting hole 1001 can also be a regular or irregular shape with a circular, elliptical, or other similar cross-section.

[0065] The third direction y can be perpendicular to each other in pairs with the first direction x and the second direction z, or they can have other non-zero angles between them.

[0066] It is understandable that the etching gas in step S40 can be selected based on the specific materials of the conductive layer 101, the spacer dielectric layer 102, and the top dielectric layer 3.

[0067] In some other embodiments, etching can also be performed in stages, using etching gases adapted to the top dielectric layer 3, the odd-numbered conductive layers 101, and the spacer dielectric layers respectively to form the first connection hole 1001 layer by layer.

[0068] The second connection hole 1002 is located in the second connection area Q3. The second connection hole 1002 penetrates each even-numbered conductive layer 101 and each spacer dielectric layer 102.

[0069] This step S40 can be performed using dry etching. Alternatively, physical etching can be used, such as plasma etching with inert gases like argon. Or, chemical-physical etching can be performed using Cl-type gases (such as Cl2, BCl3, etc.) or F-type gases (such as F2). In this step S43, the top dielectric layer 3, all even-numbered conductive layers 101, and all spacer dielectric layers 102 can be etched in one step, directly etching down to the bottom dielectric layer 2. When etching to form the second interconnect 1002, the etching depth of the bottom dielectric layer 2 can be controlled within tens of nanometers, such as 5nm, 8nm, 10nm, 12nm, or 15nm.

[0070] The cross-sectional dimensions of the second connecting hole 1002 can be several hundred nanometers. For example, the length of the cross-section of the second connecting hole 1002 in the first direction x and the length in the third direction y can both be several hundred nanometers.

[0071] The second connecting hole 1002 can be a rectangular opening. Of course, in other embodiments, the second connecting hole 1002 can also be a regular or irregular shape with a circular, elliptical, or other similar cross-section.

[0072] It is understandable that the etching gas in step S43 can be selected based on the specific materials of the conductive layer 101, the spacer dielectric layer 102, and the top dielectric layer 3.

[0073] In some other embodiments, etching can also be performed in stages, using etching gases adapted to the top dielectric layer 3, the even-numbered conductive layers 101, and the spacer dielectric layers respectively to form the second connection hole 1002.

[0074] In some embodiments, the first connection hole 1001 and the second connection hole 1002 are formed simultaneously. It is understood that the etching of the first connection hole 1001 and the second connection hole 1002 can be achieved by first forming a mask layer (such as photoresist) on the surface of the top dielectric layer 3, and then forming through holes corresponding to the first connection hole 1001 and the second connection hole 1002, respectively. Thus, the same mask layer can be used to form the first connection hole 1001 and the second connection hole 1002.

[0075] It is understood that in some other embodiments, the first connecting hole and the second connecting hole may be formed asynchronously. The first connecting hole and the second connecting hole may also not be formed using the same mask layer for etching.

[0076] like Figure 6As shown, in step S50, a first conductive structure 1201 and a second conductive structure 1202 are formed. The first conductive structure 1201 fills the first connecting hole 1001 and is electrically connected to the sidewalls of each odd-numbered conductive layer 101. The second conductive structure 1202 fills the second connecting hole 1002 and is electrically connected to the sidewalls of each even-numbered conductive layer 101.

[0077] In some embodiments, forming the first conductive structure 1201 may include the following steps S51 and S52: In step S51, a first adhesive layer 121 is formed, which is attached to the inner wall of the first connecting hole 1001.

[0078] The first adhesive layer 121 can be formed by atomic layer deposition (ALD) to achieve good coverage.

[0079] The first adhesive layer 121 can be made of a conductive material with good adhesion, such as Ti, TiN, Ta, or TaN. The first adhesive layer 121 can also serve as a seed layer and a barrier layer.

[0080] In step S52, a first conductive body 122 is formed, which fills the first connection hole 1001, and the first adhesive layer 121 is located between the first conductive body 122 and the inner wall of the first connection hole 1001.

[0081] The material of the first conductive body 122 can be metals such as copper (Cu) or tungsten (W).

[0082] The first conductive body 122 can be produced by electroplating. After electroplating the first conductive body material on the first adhesive layer 121, chemical mechanical polishing (CMP) is performed to form a first conductive structure 1201 that is flush with the top dielectric layer 3.

[0083] The first conductive body 122 in the first connection hole 1001 and the first adhesive layer 121 together form the first conductive structure 1201.

[0084] In some embodiments, forming the second conductive structure 1202 may include the following steps S53 and S54: In step S53, a second adhesive layer 123 is formed, which is attached to the inner wall of the second connecting hole 1002.

[0085] The second adhesion layer 123 can be formed by atomic layer deposition (ALD) to achieve good coverage.

[0086] The material of the second adhesive layer 123 can be a conductive material with good adhesion, such as Ti, TiN, Ta, TaN, etc. The second adhesive layer 123 can also serve as a seed layer and a barrier layer.

[0087] In step S54, a second conductive body 124 is formed, which fills the second connection hole 1002, and the second adhesive layer 123 is located between the second conductive body 124 and the inner wall of the second connection hole 1002.

[0088] The material of the first conductive body 122 can be metals such as copper (Cu) or tungsten (W).

[0089] The second conductive body 124 can be formed by electroplating the first conductive body material onto the second adhesive layer 123 and then performing chemical mechanical polishing (CMP) to form a second conductive structure 1202 that is flush with the top dielectric layer 3.

[0090] The second conductive body 124 in the second connection hole 1002 and the second adhesive layer 123 together form the second conductive structure 1202.

[0091] It should be noted that, in some other embodiments, the first conductive structure and the second conductive structure may also be formed by directly filling the first conductive body and the second conductive body, respectively.

[0092] In some embodiments, the first conductive structure 1201 and the second conductive structure 1202 are formed simultaneously.

[0093] For both the first conductive structure and the second conductive bond having an adhesive layer and a conductive body, the first adhesive layer 121 and the second adhesive layer 123 are formed simultaneously, and the first conductive body 122 and the second conductive body 124 are formed simultaneously. That is, steps S51 and S53 are formed simultaneously, and steps S52 and S54 are formed simultaneously.

[0094] An adhesive material layer can be formed first. After etching away the adhesive material layer 1210 located on the surface of the top dielectric layer 3 facing away from the bottom dielectric layer 2, the first adhesive layer 121 and the second adhesive layer 123 can be formed simultaneously.

[0095] Of course, in some other embodiments, the first conductive structure and the second conductive structure may be formed asynchronously.

[0096] It should be noted that the above Figures 2 to 7In the embodiment shown, when each of the conductive layers is made of the same material, when etching to form each conductive layer (i.e., the second conductive layer 1012 and the third conductive layer 1013) other than the conductive layer closest to the base dielectric layer 2 (i.e., the first conductive layer 1011), the spacer dielectric layer below the etched conductive layer is used as the etching stop layer.

[0097] Combination Figures 8 to 11 The method for fabricating the stacked capacitor described above is illustrated. Wherein, Figures 8 to 10 These are cross-sectional views corresponding to different processes used in fabricating a stacked capacitor 200 using an exemplary embodiment of this application. Figure 11 This is a top view of a stacked capacitor provided in an exemplary embodiment of this application. Wherein, Figure 10 For along Figure 11 The sectional view obtained by section line AA shown. This example is similar to the one described above. Figures 2 to 7 The embodiments shown are basically the same, and any similarities can be found in the above descriptions, which will not be repeated here. The difference lies in... Figures 8 to 11 In the embodiment shown, the conductive layer materials of each odd-numbered layer are the same, the conductive material of each even-numbered layer is the same, and the materials of the odd-numbered conductive layers and the even-numbered conductive layers are different.

[0098] In this embodiment, when etching to form conductive layers other than the conductive layer closest to the base dielectric layer, the spacer dielectric layer below the etched conductive layer is still used as the etching stop layer.

[0099] In some embodiments, the materials of the odd-numbered conductive layers (such as the first conductive layer 1011 and the third conductive layer 1013) may be Al or other metallic materials that can be dry-etched by chlorine (Cl) and bromine (Br) gases, but are difficult to dry-etch by F-type gases. The materials of the even-numbered conductive layers (such as the second conductive layer 1012 and the fourth conductive layer 1014) may be Mo or other metallic materials that can be etched by F-type gases, chlorine (Cl) gases, and are difficult to dry-etch by Br-type gases (based on the extremely high melting and boiling points of molybdenum bromide). In this embodiment, the materials of each spacer dielectric layer 102 are not limited, and can be controlled by controlling conditions such as etching time to make the spacer dielectric layer 102 an etching stop layer. Optionally, the material of each spacer dielectric layer 102 may be selected from one or a combination of materials such as Al2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, SrTiO3, ZrSiO4, BaSrTiO.

[0100] Combination Figures 12 to 19 The method for fabricating the stacked capacitor described above is illustrated. Wherein, Figures 12 to 19This is a cross-sectional view corresponding to different processes used in fabricating a stacked capacitor 300 according to an exemplary embodiment of this application. This example is related to the above... Figures 8 to 11 The embodiments shown are basically the same, and any similarities can be found in the above descriptions, which will not be repeated here. The difference lies in... Figures 12 to 19 In the embodiment shown, when etching to form conductive layers other than the conductive layer closest to the base dielectric layer, the conductive layer formed in the previous etching process is used as the etching stop layer.

[0101] like Figure 13 As shown, when etching to form the second conductive layer 1012, the first conductive layer 1011 is used as the etching stop layer. During etching, a mask layer 1000 is provided to protect areas that do not need to be etched.

[0102] like Figure 15 As shown, when etching to form the third conductive layer 1013, the second conductive layer 1012 is used as the etching stop layer. During etching, a mask layer 2000 is provided to protect areas that do not need to be etched.

[0103] like Figure 17 As shown, when etching to form the fourth conductive layer 1014, the third conductive layer 1013 is used as the etching stop layer. During etching, a mask layer 2000 is provided to protect areas that do not need to be etched.

[0104] It is understood that, in this embodiment, the etching gas used to form the even-numbered conductive layers can simultaneously etch the material of the even-numbered conductive layers and the spacer dielectric layer 102, but has difficulty etching the odd-numbered conductive layers. Conversely, the etching gas used to form the odd-numbered conductive layers can simultaneously etch the material of the odd-numbered conductive layers and the spacer dielectric layer 102, but has difficulty etching the even-numbered conductive layers.

[0105] In some embodiments, the materials of odd-numbered conductive layers (such as the first conductive layer 1011 and the third conductive layer 1013) may be Al or other metallic materials that can be dry-etched by chlorine (Cl) and bromine (Br) gases, but are difficult to dry-etch by fluorine (F) gases. The materials of even-numbered conductive layers (such as the second conductive layer 1012 and the fourth conductive layer 1014) may be Mo or other metallic materials that can be etched by fluorine (F) and chlorine (Cl) gases, but are difficult to dry-etch by bromine (Br) gases. The materials of each spacer dielectric layer 102 may be one or more materials or combinations thereof that can be simultaneously etched by bromine and fluorine gases, such as HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, HfSiO, HfSiON, and ZrSiO4.

[0106] It is understandable that the above Figures 8 to 11In the embodiment shown, if the material of the spacer dielectric layer 102 is selected to be similar to that of the dielectric layer 102, then... Figures 12 to 19 When the material selected for the spacer dielectric layer 102 in the above embodiments is the same, the above Figures 8 to 11 In the embodiment shown, the etching time for forming each conductive layer is less than Figures 12 to 19 The etching time for forming the same conductive layer in the illustrated embodiment. For example, HfSiO is used for etching the spacer dielectric layer 102. Figures 8 to 11 In the embodiment shown, the etching time for forming the second conductive layer is less than [a certain duration]. Figures 12 to 19 The etching time for etching to form the second conductive layer in the illustrated embodiment.

[0107] It should be noted that the above-described method for fabricating stacked capacitors can be used to fabricate stacked capacitors on wafers, and multiple stacked capacitors can be fabricated simultaneously.

[0108] It should also be noted that in the stacked capacitor formed in this application, each conductive layer is in direct contact with the adjacent spacer dielectric layer, without the addition of a separate etching stop layer.

[0109] Combination Figure 6 and Figure 7 , Figure 10 and Figure 11 as well as Figure 19 In conjunction with other accompanying drawings where necessary, this application also provides a stacked capacitor, including a base dielectric layer 2, a capacitor body 1 located on the base dielectric layer 2, a top dielectric layer 3, a first connection hole 1001, a first conductive structure 1201, a second connection hole 1002, and a second conductive structure 1202.

[0110] The material of the base dielectric layer 2 can be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6). For example, silicon oxide, silicon nitride, or silicon oxynitride, etc., to provide a platform for the subsequent manufacturing of stacked capacitors (and MIM stacked capacitors).

[0111] It is understood that the stacked capacitor can be a capacitor structure formed inside the chip or on the chip surface. In the implementation where the stacked capacitor is formed inside the chip or on the chip surface, the base dielectric layer 2 can also be used to isolate the previous metal interconnect structure in the back-end of line (BEOL) process, that is, to electrically isolate the stacked capacitor from the chip.

[0112] The base dielectric layer 2 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods.

[0113] The base dielectric layer 2 may have mutually opposing surfaces 21 and 22.

[0114] The capacitor body 1 includes multiple stacked conductive layers 101 and spacer dielectric layers 102 located between each adjacent pair of conductive layers 101. Each conductive layer 101, from the surface of the base dielectric layer 2 towards the conductive layer 101 furthest from the base dielectric layer 2, comprises alternating odd-numbered and even-numbered conductive layers 101. The stacked capacitor has a first connection region Q1, a conductive layer stack region Q2, and a second connection region Q3 arranged along a first direction x. Each odd-numbered conductive layer 101 is located in the first connection region Q1 and the conductive layer stack region Q2, and each even-numbered conductive layer 101 is located in the second connection region Q3 and the conductive layer stack region Q2. Each adjacent pair of conductive layers is made of a different material.

[0115] Each conductive layer 101 is formed by etching process. When etching each conductive layer 101 other than the conductive layer 101 closest to the base dielectric layer 2, the spacer dielectric layer 102 below the etched conductive layer 101 or the conductive layer 101 formed by the previous etching process is used as the etching stop layer.

[0116] Combination Figure 11 As shown, the capacitor body 1 includes multiple stacked layers: a first conductive layer 1011, a second conductive layer 1012, a third conductive layer 1013, and a fourth conductive layer 1014. A spacer dielectric layer 102 is formed between each adjacent pair of conductive layers 1011, 1012, 1013, and 1014. Figure 4 As shown, the spacer dielectric layer 102 includes a first spacer dielectric layer 1021, a second spacer dielectric layer 1022, and a third spacer dielectric layer 1023.

[0117] In the direction from the surface 21 of the base dielectric layer 2 toward the fourth conductive layer 1014 which is furthest from the base dielectric layer 2, the conductive layer 101 includes odd-numbered conductive layers such as the first conductive layer 1011 and the third conductive layer 1013, and even-numbered conductive layers such as the second conductive layer 1012 and the fourth conductive layer 1014.

[0118] The conductive material layers can be deposited layer by layer and patterned by etching to form the corresponding conductive layers 101.

[0119] It is understood that the materials of each conductive layer can be the same or different. The thickness of each conductive layer 101 can be the same or different. The materials of each spacer dielectric layer 102 can be the same or different. The thickness of each spacer dielectric layer 102 can be the same or different. When all the conductive layers 101 are metal layers of the same material, it facilitates the one-step etching formation of the first connecting hole and the second connecting hole.

[0120] like Figure 6 and Figure 7 In the stacked capacitor 100 shown, the material of each conductive layer 101 can be the same. For example, the material of each conductive layer 101 can be titanium, chromium, nickel, tungsten, ruthenium, citriium, molybdenum, hafnium titanium, aluminum, chromium, nickel, tungsten, ruthenium, citriium, molybdenum, hafnium, etc., which can be etched by fluorine gases.

[0121] The materials of each spacer dielectric layer 102 can be the same. For example, each spacer dielectric layer 102 can be made of a material that is not etched when the conductive layer 101 is formed. For example, Al2O3, which is difficult to etch with fluorine gases, or at least one of Al2O3 and HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, SrTiO3, and BaSrTiO can be used. The first spacer dielectric layer 1021 formed can be an Al2O3 film, or a hybrid module formed by mixing Al2O3 with at least one of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, SrTiO3, and BaSrTiO, or a multilayer film formed by stacking Al2O3 film with at least one of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, SrTiO3, and BaSrTiO. For example, a layer of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, and HfTiO can be sandwiched between two Al2O3 film layers. A film formed from at least one of the following materials: Ta2O5, ZrO2, ZrSiO2, SrTiO3, and BaSrTiO.

[0122] like Figure 10 and Figure 11In the stacked capacitor 200 shown, the odd-numbered conductive layers are made of the same material, the even-numbered conductive layers are made of the same material, and the odd-numbered conductive layers are made of different materials. For example, the odd-numbered conductive layers (such as the first conductive layer 1011 and the third conductive layer 1013) can be made of metal materials such as Al, which can be dry-etched by chlorine (Cl) and bromine (Br) gases, but are difficult to dry-etch by F-type gases. The even-numbered conductive layers (such as the second conductive layer 1012 and the fourth conductive layer 1014) can be made of metal materials such as Mo, which can be etched by F-type and chlorine (Cl) gases, but are difficult to dry-etch by Br-type gases (based on the extremely high melting and boiling points of molybdenum bromide). In this embodiment, the material of each spacer dielectric layer 102 is not limited and can be controlled by controlling conditions such as etching time to make the spacer dielectric layer 102 an etching stop layer. Optionally, the material of each spacer dielectric layer 102 may be selected from one or a combination of materials such as Al2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, SrTiO3, ZrSiO4, BaSrTiO.

[0123] like Figure 19 In the stacked capacitor 300 shown, the odd-numbered conductive layers are made of the same material, the even-numbered conductive layers are made of the same material, and the odd-numbered conductive layers are made of different materials than the even-numbered conductive layers. The odd-numbered conductive layers (such as the first conductive layer 1011 and the third conductive layer 1013) can be made of metal materials such as Al, which can be dry-etched by chlorine (Cl) and bromine (Br) gases, but are difficult to dry-etch by sulfuric acid (F) gases. The even-numbered conductive layers (such as the second conductive layer 1012 and the fourth conductive layer 1014) can be made of metal materials such as Mo, which can be etched by sulfuric acid (F) and chlorine (Cl) gases, but are difficult to dry-etch by bromine (Br) gases. Optionally, the material of each spacer dielectric layer 102 may be selected from one or a combination of materials such as Al2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, SrTiO3, ZrSiO4, BaSrTiO.

[0124] It should also be noted that in stacked capacitors 200 or 300, the materials of each even-numbered conductive layer and each odd-numbered conductive layer do not have to be exactly the same, as long as the materials of each adjacent conductive layer are different.

[0125] In some embodiments, the thickness of the conductive layer 101 can be 10nm-100nm. For example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm.

[0126] In some embodiments, the thickness of the spacer dielectric layer 102 located between two adjacent conductive layers 101 in the conductive stack region Q2 is 5nm-50nm. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0127] It is understandable that the thickness of the spacer dielectric layer 102 can be 5nm-50nm in each region. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0128] In some embodiments, among the odd-numbered conductive layers 101, the odd-numbered conductive layer 101 closest to the base dielectric layer 2 is flat, and the remaining odd-numbered conductive layers 101 include a first flat portion, a second flat portion, and a first connecting portion connecting the first flat portion and the second flat portion; wherein the distance between the first flat portion and the base dielectric layer 2 is less than the distance between the second flat portion and the base dielectric layer 2; the second flat portion is located in the conductive layer stack region Q2, and at least a portion of the first flat portion is located in the first connecting region Q1.

[0129] For example, the third conductive layer 1013 includes a first flat portion 10131, a second flat portion 10132, and a first connecting portion 10133. The second flat portion 10132 is higher than the first flat portion 10131.

[0130] Each even-numbered conductive layer 101 includes a third flat portion, a fourth flat portion, and a second connecting portion connecting the third flat portion and the fourth flat portion; wherein the distance between the third flat portion and the base dielectric layer 2 is less than the distance between the fourth flat portion and the base dielectric layer 2; the fourth flat portion is located in the conductive layer stack region Q2, and at least a portion of the third flat portion is located in the second connecting region Q3.

[0131] For example, the second conductive layer 1012 includes a third flat portion 10121, a fourth flat portion 10122, and a second connecting portion 10123. The fourth flat portion 10122 is higher than the third flat portion 10121.

[0132] It is understandable that the first spacer dielectric layer 1021 has a consistent thickness in all areas except for the corner portion of the sidewall covering the conductive layer 101.

[0133] Except at the connection portion, the thickness of the same conductive layer 101 is consistent in all straight portions.

[0134] The top dielectric layer 3 is located on the side of the capacitor body 1 that is away from the base dielectric layer 2.

[0135] The material of the top dielectric layer 3 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride.

[0136] The top dielectric layer 3 is relatively thick, at least greater than the thickness of a single spacer dielectric layer. The thickness of the top dielectric layer 3 can be greater than the thickness of a single conductive layer.

[0137] For stacked capacitors that are away from the base dielectric layer 2 (which can be understood as the top of the stacked capacitors) and require the subsequent installation of other metal interconnect structures, the top dielectric layer 3 can be used to isolate the metal interconnect structures in the back-end ofline (BEOL) process on top of the stacked capacitors.

[0138] The first connection hole 1001 is located in the first connection area Q1. The first connection hole 1001 penetrates each odd-numbered conductive layer 101 and each spacer dielectric layer 102.

[0139] The second connection hole 1002 is located in the second connection area Q3. The second connection hole 1002 penetrates each even-numbered conductive layer 101 and each spacer dielectric layer 102.

[0140] The first conductive structure 1201 is filled in the first connecting hole 1001, and the first conductive structure 1201 is electrically connected to the sidewalls of each odd-numbered conductive layer 101.

[0141] The second conductive structure 1202 is filled in the second connection hole 1002, and the second conductive structure 1202 is connected to the sidewalls of each even-numbered conductive layer 101.

[0142] The first conductive structure 1201 includes a first conductive body 122 and a first adhesive layer 121; the first adhesive layer 121 is attached to the inner wall of the first connection hole 1001, the first conductive body 122 is filled in the first connection hole 1001, and the first adhesive layer 121 is located between the first conductive body 122 and the inner wall of the first connection hole 1001.

[0143] The first adhesive layer 121 can be made of a conductive material with good adhesion, such as Ti, TiN, Ta, or TaN. The first adhesive layer 121 can also serve as a seed layer and a barrier layer.

[0144] The material of the first conductive body 122 can be metals such as copper (Cu) or tungsten (W).

[0145] The second conductive structure 1202 includes a second conductive body 124 and a second adhesive layer 123. The second adhesive layer 123 is attached to the inner wall of the second connection hole 1002, the second conductive body 124 is filled in the second connection hole 1002, and the second adhesive layer 123 is located between the second conductive body 124 and the inner wall of the second connection hole 1002.

[0146] The material of the second adhesive layer 123 can be a conductive material with good adhesion, such as Ti, TiN, Ta, TaN, etc. The second adhesive layer 123 can also serve as a seed layer and a barrier layer.

[0147] The material of the second conductive body 124 can be metals such as copper (Cu) or tungsten (W).

[0148] It should be noted that in some other embodiments, the first conductive structure and the second conductive structure may also include only the first conductive body and the second conductive body, respectively.

[0149] The example shows that the conductive layer 101 has 4 layers. It is understood that in some other embodiments, the stacked capacitor may also include other multiple conductive layers 101, such as 3 layers, 5 layers, 6 layers, 7 layers, 8 layers, etc.

[0150] It should be noted that the first connection area Q1 may be provided with one or more first connection holes 1001 to provide multiple first conductive structures 1201. Compared with providing a single first connection hole 1001, providing multiple first connection holes 1001 can increase the contact area between the first conductive structure 1201 and the conductive layer, reduce contact resistance, and improve capacitance performance. The second connection area Q3 may be provided with one or more second connection holes 1002 to provide multiple second conductive structures 1202. Compared with providing a single second connection hole 1002, providing multiple second connection holes 1002 can increase the contact area between the second conductive structure 1202 and the conductive layer, reduce contact resistance, and improve capacitance performance.

[0151] This application also provides a semiconductor device. The semiconductor device includes stacked capacitors 100, 200, or 300 as described above.

[0152] In some embodiments, the semiconductor device further includes a chip, and the stacked capacitors 100, 200 or 300 are disposed outside the chip (e.g., on the surface of the chip or on the surface of the chip through other intermediate structural layers) or inside the chip.

[0153] The chips include, but are not limited to, high-performance chips such as CPU chips, GPU chips, FPGA chips, 5G modem chips, system-on-a-chip (SoC), power management chips (PMIC), and 2.5D / 3D chiplets.

[0154] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A stacked capacitor, characterized in that, The stacked capacitors include: Base dielectric layer; A capacitor body is located on the base dielectric layer; the capacitor body includes multiple stacked conductive layers and spacer dielectric layers located between each adjacent pair of conductive layers; in each conductive layer, from the surface of the base dielectric layer toward the conductive layer farthest from the base dielectric layer, the multiple conductive layers include alternating odd-numbered conductive layers and even-numbered conductive layers; wherein the stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a first direction; each odd-numbered conductive layer is located in the first connection region and the conductive layer stack region, and each even-numbered conductive layer is located in the second connection region and the conductive layer stack region; wherein each adjacent pair of conductive layers is made of a different material; A top dielectric layer, which is located on the side of the capacitor body away from the base dielectric layer; The first connection hole is located in the first connection area and penetrates each odd-numbered conductive layer and each spaced dielectric layer; The second connection hole is located in the second connection area and penetrates each even-numbered conductive layer and each spacer dielectric layer; A first conductive structure is filled in the first connecting hole, and the first conductive structure is electrically connected to the sidewalls of each odd-numbered conductive layer. The second conductive structure is filled in the second connecting hole and is electrically connected to the sidewalls of each even-numbered conductive layer.

2. The stacked capacitor as described in claim 1, characterized in that, The first conductive structure includes a first conductive body and a first adhesive layer; the first adhesive layer is attached to the inner wall of the first connection hole, the first conductive body is filled in the first connection hole, and the first adhesive layer is located between the first conductive body and the inner wall of the first connection hole.

3. The stacked capacitor as described in claim 1, characterized in that, The second conductive structure includes a second conductive body and a second adhesive layer; the second adhesive layer is attached to the inner wall of the second connection hole, the second conductive body is filled in the second connection hole, and the second adhesive layer is located between the second conductive body and the inner wall of the second connection hole.

4. The stacked capacitor as described in claim 1, characterized in that, The conductive material is the same for all odd-numbered layers and the same for all even-numbered layers.

5. The stacked capacitor as described in claim 1, characterized in that, In each odd-numbered conductive layer, the odd-numbered conductive layer closest to the base dielectric layer is flat, and the remaining odd-numbered conductive layers include a first flat portion, a second flat portion, and a first connecting portion connecting the first flat portion and the second flat portion; wherein the distance between the first flat portion and the base dielectric layer is less than the distance between the second flat portion and the base dielectric layer; the second flat portion is located in the conductive layer stack region, and at least a portion of the first flat portion is located in the first connecting region.

6. The stacked capacitor as described in claim 1, characterized in that, Each even-numbered conductive layer includes a third flat portion, a fourth flat portion, and a second connecting portion connecting the third flat portion and the fourth flat portion; wherein the distance between the third flat portion and the base dielectric layer is less than the distance between the fourth flat portion and the base dielectric layer; the fourth flat portion is located in the conductive layer stack region, and at least a portion of the third flat portion is located in the second connecting region.

7. The stacked capacitor as described in claim 1, characterized in that, The thickness of the conductive layer is 10nm-100nm.

8. The stacked capacitor as described in claim 1, characterized in that, In the conductive stack region, the thickness of the spacer dielectric layer located between two adjacent conductive layers is 5nm-50nm.

9. A semiconductor device, characterized in that, The semiconductor device includes a stacked capacitor as described in any one of claims 1 to 8.

10. The semiconductor device as claimed in claim 9, characterized in that, The semiconductor device further includes a chip, and the stacked capacitor is disposed outside the chip or inside the chip.

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