A stacked capacitor and semiconductor device

Abstract

This application provides a stacked capacitor and a semiconductor device. The stacked capacitor includes a base dielectric layer and a main body layer located on the base dielectric layer. In the main body layer, the capacitor body includes multiple conductive layers and spacer dielectric layers. The capacitor body includes a first side and a second side facing each other. The capacitor body is provided with a through slot, which penetrates the capacitor body in a first direction and a second direction respectively, dividing the capacitor body into two functional regions. Each sub-functional region of each functional region includes a conductive layer stack region and a connection region. The through slot is stepped, and the area of ​​each conductive part away from the base dielectric layer and close to the through slot is exposed. The top dielectric layer is located on the side of the through slot and the capacitor body away from the base dielectric layer, and is provided with a first connection hole to a fourth connection hole. The conductive structure includes a first connection portion to a fourth connection portion. The first connection portion in the first opening is electrically connected to the third connection portion in the third opening, and the second connection portion in the second opening is electrically connected to the fourth connection portion in the fourth opening.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a stacked capacitor and semiconductor device. Background Technology

[0002] Capacitors are common and important passive electronic components in integrated circuits. Metal-insulator-metal (MIM) capacitors are typically formed on metal interconnect structures in the back-end of line (BEOL) process. This increases the distance between the MIM capacitor and the silicon substrate, thereby reducing the parasitic capacitance between the MIM capacitor and the silicon substrate. Furthermore, the performance of MIM capacitors is less affected by frequency and temperature. In addition, MIM capacitors are formed during the metal interconnect process, making the MIM formation process compatible with existing integrated circuit technologies. Therefore, MIM capacitors are gradually becoming the mainstream type of passive capacitor.

[0003] As Moore's Law continues to evolve, the requirements for capacitor density in integrated circuits are becoming increasingly stringent. This is particularly evident in high-performance chips such as CPUs, GPUs, and FPGAs; mobile chips including 5G modems, system-on-a-chip (SoC), power management chips (PMICs), and 2.5D / 3D chiplets, where there is a significant demand for high-density capacitors. Currently, a major mainstream structure for achieving high-density capacitors is stacked capacitors. Improving the performance of stacked capacitors has become a major focus. Utility Model Content

[0004] A first aspect of this application provides a stacked capacitor. The stacked capacitor includes: A base dielectric layer and a host layer located on the base dielectric layer, the host layer comprising: A capacitor body includes multiple stacked conductive layers and spacer dielectric layers located between any two adjacent conductive layers; in a first direction from the base dielectric layer to the capacitor body, the multiple conductive layers include alternating odd-numbered and even-numbered conductive layers; the capacitor body includes opposing first and second sides; the capacitor body is provided with a through-slot, which penetrates the capacitor body in the first direction and in a second direction from the first side to the second side, dividing the capacitor body into two functional regions; each functional region includes at least one sub-functional region, the sub-functional region including a conductive layer stack region and a connection region, the conductive layer including conductive portions located only in each conductive layer stack region; each conductive portion is flat; the through-slot is stepped, and the surface of each conductive portion away from the base dielectric layer, near the through-slot, is exposed. The top dielectric layer is partially located within the through-slot and partially located on the side of the capacitor body away from the base dielectric layer. The top dielectric layer is provided with a first connection hole and a second connection hole located in the connection area, and a plurality of third connection holes and a plurality of fourth connection holes located in the conductive layer stack area. The first connection hole and the second connection hole penetrate the top dielectric layer. Each of the third connection holes exposes a portion of the surface of an odd-numbered conductive layer, and each of the fourth connection holes exposes a portion of the surface of an even-numbered conductive layer. A conductive structure includes a first connecting portion located in a first connecting hole, a second connecting portion located in a second connecting hole, a third connecting portion located in a third connecting hole, and a fourth connecting portion located in a fourth connecting hole; the first connecting portion is electrically connected to each of the third connecting portions, and the second connecting portion is electrically connected to each of the fourth connecting portions.

[0005] In one embodiment, the stacked capacitor includes at least two stacked main layers and an isolation layer located between any two adjacent main layers; in the two adjacent main layers, a first connection portion that is further away from the base dielectric layer penetrates the isolation layer and is electrically connected to a first connection portion that is further away from the base dielectric layer, and a second connection portion that is further away from the base dielectric layer penetrates the isolation layer and is electrically connected to a second connection portion that is further away from the base dielectric layer.

[0006] In one embodiment, the surface of the top dielectric layer away from the base dielectric layer is provided with a plurality of first grooves and a plurality of second grooves. Each of the third connecting holes communicates with a first connecting hole through a first groove, and each of the fourth connecting holes communicates with a second connecting hole through a second groove. The conductive structure further includes a fifth connecting portion located in each of the first grooves and a sixth connecting portion located in each of the second grooves. Each of the fifth connecting portions is connected to the first connecting portion and a third connecting portion, and each of the sixth connecting portions is connected to the second connecting portion and a fourth connecting portion, respectively.

[0007] In one embodiment, each of the functional areas includes at least two sub-functional areas, and at least two of the sub-functional areas of the same functional area are arranged along the second direction.

[0008] In one embodiment, within the same sub-functional area, the first connection hole and the second connection hole are located on opposite sides of the conductive stacked area.

[0009] In one embodiment, the third connecting hole extends along the second direction and its length is the same as the length of the corresponding conductive portion; the first connecting hole extends along a third direction perpendicular to the first direction and the second direction; the fourth connecting hole extends along the second direction and its length is the same as the length of the corresponding conductive portion; the second connecting hole extends along a third direction perpendicular to the first direction and the second direction.

[0010] In one embodiment, the depth of the first groove and the depth of the second groove are both less than the distance between the conductive layer and the top dielectric layer that are furthest from the base dielectric layer.

[0011] In one embodiment, the thickness of the conductive layer ranges from 10 nm to 100 nm; the thickness of the spacer dielectric layer ranges from 5 nm to 50 nm.

[0012] A second aspect of this application provides a semiconductor device comprising the stacked capacitors described above.

[0013] In one embodiment, the semiconductor device further includes a chip, and the stacked capacitors are disposed outside the surface of the chip or inside the chip.

[0014] The main technical effects achieved by the embodiments of this application are: The stacked capacitor, its fabrication method, and semiconductor device provided in this application, by forming stepped through-grooves, expose the area of ​​each conductive part near the through-grooves on the surface away from the base dielectric layer. This allows for a larger contact area between the third connection part and the conductive parts of the odd-numbered conductive layers, and a larger contact area between the fourth connection part and the conductive parts of the even-numbered conductive layers. This helps reduce contact resistance and improve the performance of the stacked capacitor. Since the conductive layer is flat, there is no height difference between different areas of the same conductive layer, i.e., no steps are formed. This avoids the problem of conductive layer breakage caused by height differences between different areas of the conductive layer, thus improving the reliability of the stacked capacitor. Because the conductive layer is flat, the thickness of the spacer dielectric layer between adjacent conductive layers is uniform. This avoids the problem of electric field concentration caused by the thinner spacer dielectric layer at the step when there are steps in the conductive layer, effectively improving the breakdown characteristics of the stacked capacitor. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating a method for fabricating a stacked capacitor according to an exemplary embodiment of this application; Figures 2 to 43 This is a schematic diagram of different process steps in the fabrication method of stacked capacitors provided by an exemplary embodiment of this application. Detailed Implementation

[0016] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0017] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture; if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0018] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0019] Please refer to Figure 1 This application provides a method for preparing a stacked capacitor, the method comprising the following steps: forming a host layer on a base dielectric layer.

[0020] like Figure 1 As shown, the steps for forming the main body layer include the following steps S10 to S60.

[0021] In step S10, a capacitor body is formed; the capacitor body includes multiple stacked conductive layers and spacer dielectric layers located between any two adjacent conductive layers; in a first direction from the base dielectric layer to the capacitor body, the multiple conductive layers include alternating odd-numbered conductive layers and even-numbered conductive layers; each conductive layer is flat; the capacitor body includes opposing first and second sides.

[0022] In step S20, a through groove is formed, which penetrates the capacitor body in the first direction and in the second direction from the first side to the second side, dividing the capacitor body into two functional areas. Each functional area includes at least one sub-functional area, which includes a conductive layer stack area and a connection area. The through groove is stepped, and the area of ​​the conductive layer away from the base dielectric layer near the through groove is exposed.

[0023] In step S30, the portion of the capacitor body located in the connection area is removed, and the conductive layer forms conductive portions located in each of the conductive layer stack areas. The area of ​​each conductive portion near the through slot on the surface away from the base dielectric layer is exposed.

[0024] In step S40, a top dielectric layer is formed, wherein part of the top dielectric layer is located in the through slot and part is located on the side of the capacitor body away from the base dielectric layer.

[0025] In step S50, a first connection hole and a second connection hole located in the connection area, and a plurality of third connection holes and a plurality of fourth connection holes located in the conductive stack area are formed in each of the sub-functional areas; the first connection hole and the second connection hole penetrate the top dielectric layer, each third connection hole exposes a portion of the conductive part of an odd-numbered conductive layer, and each fourth connection hole exposes a portion of the conductive part of an even-numbered conductive layer.

[0026] In step S60, a conductive structure is formed, the conductive structure including a first connecting portion located in the first connecting hole, a second connecting portion located in the second connecting hole, a third connecting portion located in the third connecting hole, and a fourth connecting portion located in the fourth connecting hole; the first connecting portion is electrically connected to each of the third connecting portions, and the fourth connecting portion is electrically connected to each of the fourth connecting portions.

[0027] The stacked capacitor fabrication method provided in this application provides a method for forming stepped through-grooves, which exposes the areas of the conductive portions near the through-grooves on the surfaces of the conductive portions away from the base dielectric layer. The third connecting portion located in the third connecting hole contacts the exposed surfaces of the conductive portions of the odd-numbered conductive layers, and the fourth connecting portion located in the fourth connecting hole contacts the exposed surfaces of the conductive portions of the even-numbered conductive layers. Compared to a method where the connecting portions contact the sidewalls of the conductive layers, this method allows for a larger contact area between the third connecting portion and the conductive portions of the odd-numbered conductive layers, and a larger contact area between the fourth connecting portion and the conductive portions of the even-numbered conductive layers. This helps to reduce contact resistance and improve the stacked capacitor capacity. The performance of the stacked capacitor is improved by dividing the capacitor body into two parts during the formation of the through-slot, which saves the process steps of patterning the capacitor body and helps to reduce the complexity of the manufacturing process. Since the conductive layer is flat, there is no height difference between different areas of the same conductive layer, that is, no steps are formed. This avoids the problem of the conductive layer breaking due to the height difference between different areas of the conductive layer, thus improving the reliability of the stacked capacitor. Since the conductive layer is flat, the thickness of the spacer dielectric layer between adjacent conductive layers is uniform. This avoids the problem of electric field concentration caused by the thinner spacer dielectric layer at the step when there are steps in the conductive layer, thus effectively improving the breakdown characteristics of the stacked capacitor.

[0028] The stacked capacitors provided in this application embodiment can be capacitor structures formed inside the chip or on the chip surface.

[0029] The following will combine Figures 2 to 43The following provides a detailed description of steps S10 to S60. The accompanying drawings use a configuration of 4 conductive layers as an example. It is understood that the number of conductive layers can be different from 4, such as 3, 5, 6, 7, or 8 layers.

[0030] Prior to step S10, a base dielectric layer 10 is provided.

[0031] In one embodiment, the base dielectric layer 10 can be made of a low-k dielectric material (a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (a dielectric material with a relative permittivity less than 2.6), such as silicon nitride or silicon oxynitride, providing a platform for the subsequent fabrication of the capacitor body. The base dielectric layer 10 can be formed using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In embodiments where stacked capacitors are formed within or on the surface of a chip, the base dielectric layer 10 can also be used to isolate the preceding metal interconnect structure in the back-end ofline (BEOL) process, i.e., electrically isolating the stacked capacitors from the chip.

[0032] like Figure 2 and Figure 3 As shown, in step S10, a capacitor body 20 is formed; the capacitor body 20 includes multiple stacked conductive layers 21 and spacer dielectric layers 22 located between any two adjacent conductive layers 21; in a first direction X from the base dielectric layer 10 to the capacitor body 20, the multiple conductive layers 21 include alternating odd-numbered conductive layers and even-numbered conductive layers; each conductive layer 21 is flat; the capacitor body 20 includes opposing first side 201 and second side 202.

[0033] The direction from the first side 201 to the second side 202 is the second direction Y, which is perpendicular to the first direction X.

[0034] Combination Figure 2 and Figure 3 As shown, the conductive layer 21 of the capacitor body 20 includes a multi-layered stacked first conductive layer 211, a second conductive layer 212, a third conductive layer 213, and a fourth conductive layer 214. The spacer dielectric layer 22 includes a first spacer dielectric layer 221 located between the first conductive layer 211 and the second conductive layer 212, a first spacer dielectric layer 222 located between the second conductive layer 212 and the third conductive layer 213, and a third spacer dielectric layer 223 located between the third conductive layer 213 and the fourth conductive layer 214. The first conductive layer 211 and the third conductive layer 213 are odd-numbered conductive layers, while the second conductive layer 212 and the fourth conductive layer 214 are even-numbered conductive layers.

[0035] In one embodiment, each conductive layer 21 can be formed by depositing a conductive material layer, such as through chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The material of each conductive layer 21 can be a metallic material, such as aluminum. Of course, in other embodiments, the material of the conductive layer can also be, but is not limited to, etchable metals such as titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, citriium, molybdenum, and hafnium. The thickness of each conductive layer 21 can range from 10 nm to 100 nm, for example, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, and 100 nm. The thickness of each conductive layer 21 can be the same or different. The material of each conductive layer 21 can be the same or different.

[0036] In one embodiment, each spacer dielectric layer 22 can be formed by depositing a dielectric material, such as through chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. The thickness of the spacer dielectric layers 22 is uniform in all regions. The material of each spacer dielectric layer 22 can be any one or more mixtures of, but not limited to, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN. The thickness of each spacer dielectric layer 22 can range from 5nm to 50nm. For example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, etc. The thickness of each spacer dielectric layer 22 can be the same or different. The material of each spacer dielectric layer 22 can be the same or different.

[0037] Combination Figures 4 to 22 As shown, in step S20, a through groove 203 is formed, which penetrates the capacitor body 20 in the first direction X and the second direction Y, respectively, dividing the capacitor body 20 into two functional regions 204. Each functional region 204 includes at least one sub-functional region 2041, which includes a conductive stacked region 2042 and a connection region 2043. The through groove 203 is stepped, and the area of ​​the surface of each conductive layer 21 away from the base dielectric layer 10 and close to the through groove 203 is exposed.

[0038] In one embodiment, a dry etching process can be used to form the through-groove 203. The etching of adjacent conductive layers 21 and spacer dielectric layers 22 can be performed in different etching steps. When etching the spacer dielectric layer, the etching stops at the conductive layer located on the side of the spacer dielectric layer facing the base dielectric layer and in contact with the spacer dielectric layer. The formation process of the through-groove 203 is described below.

[0039] like Figure 4 and Figure 5 As shown, a mask layer 30 is formed on the side of the capacitor body 20 away from the base dielectric layer 10, and a first groove 31 penetrating the mask layer 30 in the second direction Y is formed on the mask layer 30. The first groove 31 can be created by etching, such as using oxygen etching, so as not to damage the capacitor body 20. The material of the mask layer 30 can be photoresist.

[0040] Next, as Figure 6 and Figure 7 As shown, the fourth conductive layer 214 and the third spacer dielectric layer 223 are etched through the first slot 31 of the mask layer 30 to form a first sub-channel 2031 that penetrates the fourth conductive layer 214 and the third spacer dielectric layer 223, and a portion of the surface of the third conductive layer 213 is exposed by the first sub-channel 2031.

[0041] The fourth conductive layer 214 can be etched first using a dry etching method, and then the third spacer dielectric layer 223 can be etched.

[0042] When etching each conductive layer 21, taking aluminum as an example, chlorine (Cl) gas can be used for etching. When chlorine gas is used to etch the conductive layer 21, AlCl3 will be generated; since AlCl3 has a low melting and boiling point, it can generate volatile products that can be etched away by Cl gas.

[0043] When etching each spacer dielectric layer 22, the conductive layer 21 located below and adjacent to the spacer layer 22 serves as an etching stop layer. A gas with good etching selectivity for the spacer dielectric layer 22 but poor etching selectivity for the conductive layer can be selected for etching. In some embodiments, when the conductive layer 21 is made of aluminum, a fluorine (F) gas can be selected for etching the spacer dielectric layer 22. Fluorine gases can etch the spacer dielectric layer 22, but they cause a dense AlF3 film to form on the aluminum surface. AlF3 has a melting and boiling point of over 1000 degrees Celsius, preventing the formation of volatile products and making it difficult to etch, thus preventing the underlying conductive layer 21 from being etched by the fluorine gas.

[0044] Next, as Figure 8 and Figure 9 As shown, the first groove 31 of the mask layer 30 is further etched to form the opposite two sides of the first groove 31 to form the second groove 32. The width of the second groove 32 is greater than the width of the first groove 31, and part of the surface of the fourth conductive layer 214 is exposed by the second groove 32.

[0045] Next, such as 10 and... Figure 11As shown, the fourth conductive layer 214, the third spacer dielectric layer 223, the third conductive layer 213, and the second spacer dielectric layer 222 are etched through the second slot 32 and the first sub-channel 2031 of the mask layer 30 to form a stepped second sub-channel 2032. The second sub-channel 2032 penetrates through the fourth conductive layer 214, the third spacer dielectric layer 223, the third conductive layer 213, and the second spacer dielectric layer 222. The entire surface of the fourth conductive layer 214 exposed by the second slot 32 is etched away, while parts of the surfaces of the third conductive layer 213 and the second conductive layer 212 are exposed. The width of the second sub-channel 2032 is the largest at the top and is the same as the width of the second slot 32. During the etching process, the fourth conductive layer 214 and the third conductive layer 213 are etched simultaneously, and the total area etched is equal to the cross-sectional area of ​​the second slot 32. That is, the part of the fourth conductive layer 214 exposed by the second slot 32 is completely etched away, and the part of the third conductive layer 213 etched away is the same as the cross-sectional area of ​​the first slot 31. The third spacer dielectric layer 223 and the second spacer dielectric layer 222 are etched simultaneously, and the total area etched is equal to the cross-sectional area of ​​the second slot 32. Finally, the side of the third spacer dielectric layer 223 exposed by the second sub-channel 2032 is flush with the side of the fourth conductive layer 214 exposed by the second sub-channel 2032, and is also flush with the side of the second slot 32. The side of the third conductive layer 213 exposed by the second sub-channel 2032 is flush with the side of the second spacer dielectric layer 222 exposed by the second sub-channel 2032. The second slot 32 and the second sub-slot 2032 are symmetrical about the same pair of surfaces perpendicular to the base dielectric layer 10.

[0046] Next, as Figure 12 and Figure 13 As shown, the second groove 32 of the mask layer 30 is etched to form the opposite sides of the second groove 32 to form the third groove 33. The width of the third groove 33 is greater than the width of the second groove 32, and part of the surface of the fourth conductive layer 214 is exposed by the third groove 33.

[0047] Next, as Figure 14 and Figure 15As shown, the fourth conductive layer 214, the third spacer dielectric layer 223, the third conductive layer 213, the second spacer dielectric layer 222, the second conductive layer 212, and the first spacer dielectric layer 221 are etched through the third slot 33 and the second sub-channel 2032 of the mask layer 30 to form a stepped third sub-channel 2033. The third sub-channel 2033 penetrates the fourth conductive layer 214, the third spacer dielectric layer 223, the third conductive layer 213, the second spacer dielectric layer 222, the second conductive layer 212, and the first spacer dielectric layer 221. The surface of the fourth conductive layer 214 exposed by the third slot 33 is completely etched away, and parts of the surfaces of the third conductive layer 213, the second conductive layer 212, and the first conductive layer 211 are exposed. During the etching process, the fourth conductive layer 214, the third conductive layer 213, and the second conductive layer 212 are etched simultaneously, and the total etched area is equal to the cross-sectional area of ​​the third trench 33. The portions of the fourth conductive layer 214, the third conductive layer 213, and the second conductive layer 212 exposed by the third trench 33 are completely etched away. The third spacer dielectric layer 223, the second spacer dielectric layer 222, and the first spacer dielectric layer 221 are also etched simultaneously, and the total etched area is equal to the cross-sectional area of ​​the third trench 33. Finally... The side of the third spacer dielectric layer 223 exposed by the third sub-channel 2033 is flush with the side of the fourth conductive layer 214 exposed by the third sub-channel 2033, and also flush with the side of the third slot 33; the side of the third conductive layer 213 exposed by the third sub-channel 2033 is flush with the side of the second spacer dielectric layer 222 exposed by the third sub-channel 2033; the side of the second conductive layer 212 exposed by the third sub-channel 2033 is flush with the side of the first spacer dielectric layer 221 exposed by the third sub-channel 2033. The third slot 33 and the third sub-channel 2033 are symmetrical about the same symmetrical surface perpendicular to the base dielectric layer.

[0048] Next, as Figure 16 and Figure 17 As shown, the third groove 33 of the mask layer 30 is etched to form the opposite two sides of the third groove 33 to form the fourth groove 34. The width of the fourth groove 34 is greater than the width of the third groove 33, and part of the surface of the fourth conductive layer 214 is exposed by the fourth groove 34.

[0049] Next, as Figure 18 and Figure 19As shown, the fourth conductive layer 214, the third spacer dielectric layer 223, the third conductive layer 213, the second spacer dielectric layer 222, the second conductive layer 212, the first spacer dielectric layer 221, and the first conductive layer 211 are etched through the fourth slot 34 and the third sub-channel 2033 of the mask layer 30 to form a stepped channel 203. The channel 203 penetrates the fourth conductive layer 214, the third spacer dielectric layer 223, the third conductive layer 213, the second spacer dielectric layer 222, the second conductive layer 212, the first spacer dielectric layer 221, and the first conductive layer 211. The surface of the fourth conductive layer 214 exposed by the fourth slot 34 is completely etched away, and part of the surfaces of the third conductive layer 213, the second conductive layer 212, the first conductive layer 211, and the substrate dielectric layer 10 are exposed. During the etching process, the fourth conductive layer 214, the third conductive layer 213, the second conductive layer 212, and the first conductive layer 211 are etched simultaneously, and the total etched area is equal to the cross-sectional area of ​​the fourth slot 34. The portions of the fourth conductive layer 214, the third conductive layer 213, the second conductive layer 212, and the first conductive layer 211 exposed by the fourth slot 34 are all etched away. The third spacer dielectric layer 223, the second spacer dielectric layer 222, and the first spacer dielectric layer 221 are etched simultaneously. Finally, the side of the third spacer dielectric layer 223 exposed by the through slot 203 is flush with the side of the fourth conductive layer 214 exposed by the through slot 203, and also flush with the side of the fourth slot 34. The side of the third conductive layer 213 exposed by the through slot 203 is flush with the side of the second spacer dielectric layer 222 exposed by the through slot 203, and the side of the second conductive layer 212 exposed by the through slot 203 is flush with the side of the first spacer dielectric layer 221 exposed by the through slot 203. The fourth slot 34 and the through slot 203 are symmetrical about the same pair of lining surfaces perpendicular to the base dielectric layer.

[0050] Next, as Figures 20 to 22 As shown, the mask layer 30 is removed. The through-slot 203 divides the capacitor body 20 into two functional areas 204. Figure 21 for Figure 20 The sectional view obtained by cutting along AA. Figure 22 for Figure 20 The sectional view obtained by cutting along BB.

[0051] In this embodiment, the through-groove 203 can be formed by etching the mask layer one after another, without having to perform photolithography on each conductive layer. When the number of capacitor bodies 20 is greater than four layers, the number of photolithography steps can be reduced, thus reducing the complexity of the process.

[0052] like Figures 23 to 25As shown, in step S30, the portion of the capacitor body 20 located in the connection area 2043 is removed; each of the conductive layers 21 forms a conductive portion 215 located in each of the conductive stacked areas 2042, and the area of ​​each conductive portion 215 away from the base dielectric layer 10 near the through groove 203 is exposed; each spacer dielectric layer 22 forms a dielectric portion 224 located in each of the conductive stacked areas 2042. Figure 24 for Figure 23 The sectional view obtained by cutting along CC. Figure 25 for Figure 23 The sectional view obtained by cutting along DD.

[0053] In this step, dry etching can be used to etch through all conductive layers 21 and spacer dielectric layers 22 in one step. Before etching, a mask layer can be formed on the side of the capacitor body 20 away from the base dielectric layer 10, covering the parts of the capacitor body 20 that do not need to be removed.

[0054] like Figure 23 As shown, each functional region 204 includes two sub-functional regions 2041, and the two sub-functional regions 2041 of the same functional region 204 are arranged along the second direction Y. In other embodiments, each functional region 204 may include two or more sub-functional regions 2041 arranged along the second direction Y. In the same sub-functional region 2041, the connection region 2043 surrounds the conductive stacked region 2042.

[0055] like Figures 26 to 28 As shown, in step S40, a top dielectric layer 40 is formed. Part of the top dielectric layer 40 is located within the through-slot 203, and part is located on the side of the capacitor body 20 facing away from the base dielectric layer 10. Furthermore, the top dielectric layer 40 partially fills each connection region 2043.

[0056] in, Figure 27 for Figure 26 The sectional view obtained by cutting along EE. Figure 28 for Figure 26 The sectional view obtained by cutting along FF.

[0057] The top dielectric layer 40 is made of a low-k dielectric material (a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride. The top dielectric layer 40 is relatively thick, at least greater than the thickness of the spacer dielectric layer 22. The thickness of the top dielectric layer 40 may be greater than the thickness of the conductive layer 21.

[0058] For the side of the stacked capacitor away from the base dielectric layer 10 (which can be understood as the top of the stacked capacitor), a conductive structure needs to be set later. The top dielectric layer 40 can be used to isolate different connection parts of the conductive structure.

[0059] like Figures 29 to 31 As shown, in step S50, a first connection hole 41 and a second connection hole 42 located in the connection area 2043, and a plurality of third connection holes 43 and a plurality of fourth connection holes 44 located in the conductive stack area 2042 are formed in each of the sub-functional areas 2041; the first connection hole 41 and the second connection hole 42 penetrate the top dielectric layer 40, each third connection hole 43 exposes a portion of the surface of the conductive portion 215 of an odd-numbered conductive layer, and each fourth connection hole 44 exposes a portion of the surface of the conductive portion 215 of an even-numbered conductive layer.

[0060] in, Figure 30 for Figure 29 The sectional view obtained by cutting along GG. Figure 31 for Figure 29 The sectional view obtained by cutting along HH.

[0061] The first connecting hole 41, the second connecting hole 42, the third connecting hole 43, and the fourth connecting hole 44 can be etched simultaneously. Before etching, a mask can be designed and a mask layer can be formed according to the width of each connecting hole. Fluorine gas can be used to etch the top dielectric layer 40, and the etching stops at the surface of each conductive layer 21.

[0062] like Figure 31 As shown, the conductive portions 215 of the first conductive layer 211 and the conductive portions 215 of the third conductive layer 213 that are not covered by the spacer dielectric layer 22 are respectively exposed by a third connection hole 43, and the conductive portions 215 of the second conductive layer 212 that are not covered by the spacer dielectric layer 22 and the conductive portions 215 of the fourth conductive layer 214 are respectively exposed by a fourth connection hole 44.

[0063] like Figure 29 As shown, within the same sub-functional area 2041, the first connecting hole 41 and the second connecting hole 42 are located on opposite sides of the conductive laminate area 2042. This arrangement facilitates the subsequent connection between the first connecting portion located in the first connecting hole 41 and the third connecting portion located in the third connecting hole 43, and facilitates the subsequent connection between the second connecting portion located in the second connecting hole 42 and the fourth connecting portion located in the fourth connecting hole 44.

[0064] like Figure 29 As shown, both the first connecting hole 41 and the second connecting hole 42 extend along the third direction Z, which is perpendicular to the first direction X and the second direction Y, respectively.

[0065] like Figure 29As shown, the third connecting hole 43 extends along the second direction Y, and its length is the same as the length of the corresponding conductive part 215. The two opposite edges of the third connecting hole 43 in the second direction Y coincide with the two opposite edges of the corresponding conductive part 215 in the second direction Y. Similarly, the fourth connecting hole 44 extends along the second direction Y, and its length is the same as the length of the corresponding conductive part 215. The two opposite edges of the fourth connecting hole 44 in the second direction Y coincide with the two opposite edges of the corresponding conductive part 215 in the second direction Y. This increases the contact area between the subsequently formed third connecting part and the corresponding conductive part 215, as well as the contact area between the subsequently formed fourth connecting part and the corresponding conductive part 215, which helps to reduce contact resistance.

[0066] In one embodiment, after step S50, the preparation method further includes the following steps: like Figures 32 to 34 As shown, a plurality of first grooves 45 and a plurality of second grooves 46 are formed on the surface of the top dielectric layer 40 away from the base dielectric layer 10. Each of the third connecting holes 43 communicates with the first connecting hole 41 through a first groove 45, and each of the fourth connecting holes 44 communicates with the second connecting hole 42 through a second groove 46.

[0067] in, Figure 33 for Figure 32 The sectional view obtained by cutting along section II. Figure 34 for Figure 32 The sectional view obtained by cutting along JJ.

[0068] The first groove 45 is located between the first connecting hole 41 and the third connecting hole 43, and the width of the first groove 45 in the third direction Z can be the same as the width of the third connecting hole 43 in the third direction Z; the second groove 46 is located between the second connecting hole 42 and the fourth connecting hole 44, and the width of the second groove 46 in the third direction Z can be the same as the width of the fourth connecting hole 44 in the third direction Z.

[0069] The first groove 45 and the second groove 46 can be formed by etching the top dielectric layer 40 with fluorine gas.

[0070] The depths of both the first groove 45 and the second groove 46 are less than the distance between the conductive layer 21, which is furthest from the base dielectric layer 10, and the top dielectric layer 40. This prevents the first groove 45 from being electrically connected to some conductive layers 21, thus avoiding short circuits.

[0071] like Figures 35 to 37As shown, in step S60, a conductive structure is formed, which includes a first connecting portion 51 located in the first connecting hole 41, a second connecting portion 52 located in the second connecting hole 42, a third connecting portion 53 located in the third connecting hole 43, and a fourth connecting portion 54 located in the fourth connecting hole 44; the first connecting portion 51 is electrically connected to each of the third connecting portions 53, and the second connecting portion 52 is electrically connected to each of the fourth connecting portions 54.

[0072] in, Figure 36 for Figure 35 The sectional view obtained by cutting along KK. Figure 37 for Figure 35 The sectional view obtained by cutting along LL.

[0073] Since the third connecting part 53 is located inside the third connecting hole 43, the third connecting part 53 contacts and is electrically connected to the corresponding odd-numbered conductive layer, thereby the third connecting part 53 electrically connects the odd-numbered conductive layer to the first connecting part 51, that is, the first connecting part 51 is electrically connected to all the odd-numbered conductive layers; since the fourth connecting part 54 is located inside the fourth connecting hole 44, the fourth connecting part 54 contacts and is electrically connected to the corresponding even-numbered conductive layer, thereby the fourth connecting part 54 electrically connects the even-numbered conductive layer to the second connecting part 52, that is, the second connecting part 52 is electrically connected to all the even-numbered conductive layers.

[0074] The conductive structure also includes a fifth connecting portion 55 located in each of the first grooves 45 and a sixth connecting portion 56 located in each of the second grooves 46. Each of the fifth connecting portions 55 is connected to the first connecting portion 51 and one of the third connecting portions 53, respectively. Each of the sixth connecting portions 56 is connected to the second connecting portion 52 and one of the fourth connecting portions 54, respectively. That is, each of the third connecting portions 53 is electrically connected to the first connecting portion 51 through the fifth connecting portion 55, and each of the fourth connecting portions 54 is electrically connected to the second connecting portion 52 through the sixth connecting portion 56.

[0075] In one embodiment, the various connections of the conductive structure can be formed simultaneously. The conductive structure can be formed using an electroplating process. Specifically, a seed layer can first be formed in each connection hole, the first groove 45, and the second groove 46. The seed layer can be formed using atomic layer deposition (ALD) to achieve good coverage. The material of the seed layer can be a material with good adhesion such as Ti, TiN, Ta, or TaN. Then, an electroplating process is performed to electroplat a metal material in each connection hole, the first groove 45, and the second groove 46. The metal material for electroplating can be copper (Cu), tungsten (W), or other metals. After electroplating the metal material on the seed layer, chemical mechanical polishing (CMP) can be performed to make the surface of each connection flush with the surface of the top dielectric layer 40.

[0076] Through the above process, a main layer is formed on the base dielectric layer 10.

[0077] In one embodiment, forming a main layer on the base dielectric layer includes: forming at least two stacked main layers on the base dielectric layer, with an isolation layer formed between adjacent main layers. In two adjacent main layers, a first connection portion that is further away from the base dielectric layer penetrates the isolation layer and is electrically connected to a first connection portion that is further away from the base dielectric layer; a second connection portion that is further away from the base dielectric layer penetrates the isolation layer and is electrically connected to a second connection portion that is further away from the base dielectric layer. This allows the capacitor structures of two adjacent main layers to be connected in parallel.

[0078] Figures 38 to 43 The example of forming two main layers on the base dielectric layer 10 will be introduced.

[0079] First, such as Figures 38 to 40 As shown, an isolation layer 60 is first formed on the side of the underlying main layer away from the base dielectric layer 10.

[0080] in, Figure 39 for Figure 38 The sectional view obtained by cutting along MM. Figure 40 for Figure 38 The cross-sectional view obtained by cutting along NN.

[0081] The material of the isolation layer 60 is a low-k dielectric material (a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride.

[0082] Subsequently, a main body layer is formed above the isolation layer 60. The formation process of this main body layer is similar to the detailed formation process of the main body layer described above, and will not be repeated here. Figures 41 to 43 As shown, the difference is that, during the formation of the upper main body layer, the first connecting hole 41' and the second connecting hole 42' simultaneously penetrate the isolation layer 60 and the top dielectric layer 40'.

[0083] in, Figure 42 for Figure 41 The sectional view obtained by cutting along XX. Figure 43 for Figure 41 The sectional view obtained by cutting along the YY direction.

[0084] in, Figures 38 to 43 The illustration uses a two-layer main body as an example. In other embodiments, the stacked capacitors may include three or more main body layers.

[0085] In one embodiment, the interconnects are formed simultaneously in the same etching process. When the capacitor body 20 includes a large number of conductive layers 21, to avoid etching through the conductive layers during the etching of the top dielectric layer 40' and the isolation layer 60 to form the interconnects, and to avoid etching the first connection portion 51 located in the first interconnect 41 and the second connection portion 52 located in the second interconnect 42, the thickness of each conductive layer 21 can be increased. Alternatively, an etching stop layer can be formed before forming the top dielectric layer 40'. The etching stop layer can cover the exposed surfaces of each conductive layer 21 in the upper capacitor body, and can also cover the surfaces of the first connection portion 51 and the second connection portion 52. After forming the interconnects, the etching stop layer is removed. Thus, when forming the interconnects, if the etching stops at the etching stop layer, the etching stop layer can protect the conductive layers, the first connection portion 51, and the second connection portion 52 from being etched. In some embodiments, when using fluorine gas to etch the top dielectric layer 40' and the isolation layer 60, the material of the etching stop layer can be molybdenum oxide.

[0086] This application also provides a stacked capacitor in its embodiments. For example... Figures 35 to 37 ,and Figures 41 to 43 As shown, the stacked capacitor includes a base dielectric layer 10 and a main layer located on the base dielectric layer 10.

[0087] The main body layer includes a capacitor body 20, a top dielectric layer 40, and a conductive structure 50. The capacitor body 20 includes multiple stacked conductive layers 21 and spacer dielectric layers 22 located between any two adjacent conductive layers 21. In a first direction X from the base dielectric layer 10 towards the capacitor body 20, the multiple conductive layers 21 include alternating odd-numbered and even-numbered conductive layers. The capacitor body 20 includes opposing first side 201 and second side 202. The capacitor body 20 is provided with a through slot 203, the through slot 203 being located in the first direction X and in a second direction X from the first side 201 towards the second side 202. The capacitor body 20 is divided into two functional regions 204 by passing through it in the Y direction. Each functional region 204 includes at least one sub-functional region 2041, which includes a conductive stacked region 2042 and a connection region 2043. The conductive layer 21 includes conductive portions 215 located only in each conductive stacked region 2042. Each conductive portion 215 is flat. The through-slot 203 is stepped, and the area of ​​each conductive portion 215 away from the base dielectric layer 10 and close to the through-slot 203 is exposed. The top dielectric layer 40 is partially located within the through-slot 203 and partially located on the side of the capacitor body 20 facing away from the base dielectric layer 10. The top dielectric layer 40 is provided with a first connection hole 41 and a second connection hole 42 located in the connection region 2043, and a plurality of third connection holes 43 and a plurality of fourth connection holes 44 located in the conductive stack region 2042. The first connection hole 41 and the second connection hole 42 penetrate the top dielectric layer 40. Each of the third connection holes 43 exposes a portion of the surface of an odd-numbered conductive layer, and each of the fourth connection holes 44 exposes a portion of the surface of an even-numbered conductive layer. The conductive structure 50 includes a first connection portion 51 located in the first connection hole 41, a second connection portion 52 located in the second connection hole 42, a third connection portion 53 located in the third connection hole 43, and a fourth connection portion 54 located in the fourth connection hole 44. The first connection portion 51 is electrically connected to each of the third connection portions 53, and the second connection portion 52 is electrically connected to each of the fourth connection portions 54.

[0088] In one embodiment, such as Figures 41 to 43 As shown, the stacked capacitor includes at least two stacked main layers and an isolation layer 60 located between any two adjacent main layers; in the two adjacent main layers, a first connection portion 51' that is farther away from the base dielectric layer 10 penetrates the isolation layer 60 and is electrically connected to a first connection portion 51 that is farther away from the base dielectric layer 10, and a second connection portion 52' that is farther away from the base dielectric layer 10 penetrates the isolation layer 60 and is electrically connected to a second connection portion 52 that is farther away from the base dielectric layer 10.

[0089] In one embodiment, the surface of the top dielectric layer 40 away from the base dielectric layer 10 is provided with a plurality of first grooves 45 and a plurality of second grooves 46. Each of the third connecting holes 43 communicates with the first connecting hole 41 through a first groove 45, and each of the fourth connecting holes 44 communicates with the second connecting hole 42 through a second groove 46. The conductive structure 50 further includes a fifth connecting portion 55 located in each of the first grooves 45 and a sixth connecting portion 56 located in each of the second grooves 46. Each of the fifth connecting portions 55 is connected to the first connecting portion 51 and a third connecting portion 53, respectively, and each of the sixth connecting portions 56 is connected to the second connecting portion 52 and a fourth connecting portion 54, respectively.

[0090] In one embodiment, such as Figure 35 As shown, each of the functional areas 204 includes at least two sub-functional areas 2041, and the at least two sub-functional areas 2041 of the same functional area 204 are arranged along the second direction Y.

[0091] In one embodiment, such as Figure 35 As shown, in the same sub-functional area 2041, the first connecting hole 41 and the second connecting hole 42 are located on opposite sides of the conductive stacked area 2042.

[0092] In one embodiment, such as Figure 35 As shown, the third connecting hole 43 extends along the second direction Y, and its length is the same as the length of the corresponding conductive part 215; the first connecting hole 41 extends along a third direction Z perpendicular to the first direction X and the second direction Y. The fourth connecting hole 44 extends along the second direction Y, and its length is the same as the length of the corresponding conductive part 215; the second connecting hole 42 extends along a third direction Z perpendicular to the first direction X and the second direction Y.

[0093] The embodiments of stacked capacitors provided in this application and the embodiments of the method for preparing stacked capacitors belong to the same inventive concept. The relevant details and beneficial effects can be referred to each other and will not be repeated here.

[0094] This application also provides a semiconductor device. The semiconductor device includes stacked capacitors as described above.

[0095] In some embodiments, the semiconductor device further includes a chip, and the stacked capacitors are disposed outside the surface of the chip or inside the chip.

[0096] The chips mentioned include, but are not limited to, high-performance chips such as CPU chips, GPU chips, FPGA chips, 5G modem chips, system-on-a-chip (SoC), power management chips (PMIC), and 2.5D / 3D chiplets.

[0097] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A stacked capacitor, characterized in that, include: A base dielectric layer and a host layer located on the base dielectric layer, the host layer comprising: A capacitor body includes multiple stacked conductive layers and spacer dielectric layers located between any two adjacent conductive layers; in a first direction from the base dielectric layer to the capacitor body, the multiple conductive layers include alternating odd-numbered and even-numbered conductive layers; the capacitor body includes opposing first and second sides; the capacitor body is provided with a through-slot, which penetrates the capacitor body in the first direction and in a second direction from the first side to the second side, dividing the capacitor body into two functional regions; each functional region includes at least one sub-functional region, the sub-functional region including a conductive layer stack region and a connection region, the conductive layer including conductive portions located only in each conductive layer stack region; each conductive portion is flat; the through-slot is stepped, and the surface of each conductive portion away from the base dielectric layer, near the through-slot, is exposed. The top dielectric layer is partially located within the through-slot and partially located on the side of the capacitor body away from the base dielectric layer. The top dielectric layer is provided with a first connection hole and a second connection hole located in the connection area, and a plurality of third connection holes and a plurality of fourth connection holes located in the conductive layer stack area. The first connection hole and the second connection hole penetrate the top dielectric layer. Each of the third connection holes exposes a portion of the surface of an odd-numbered conductive layer, and each of the fourth connection holes exposes a portion of the surface of an even-numbered conductive layer. A conductive structure includes a first connecting portion located in a first connecting hole, a second connecting portion located in a second connecting hole, a third connecting portion located in a third connecting hole, and a fourth connecting portion located in a fourth connecting hole; the first connecting portion is electrically connected to each of the third connecting portions, and the second connecting portion is electrically connected to each of the fourth connecting portions.

2. The stacked capacitor as described in claim 1, characterized in that, The stacked capacitor includes at least two stacked main layers and an isolation layer located between any two adjacent main layers; in the two adjacent main layers, a first connection portion that is further away from the base dielectric layer penetrates the isolation layer and is electrically connected to a first connection portion that is further away from the base dielectric layer, and a second connection portion that is further away from the base dielectric layer penetrates the isolation layer and is electrically connected to a second connection portion that is further away from the base dielectric layer.

3. The stacked capacitor according to claim 1, characterized in that, The surface of the top dielectric layer away from the base dielectric layer is provided with a plurality of first grooves and a plurality of second grooves. Each of the third connecting holes communicates with the first connecting hole through one of the first grooves, and each of the fourth connecting holes communicates with the second connecting hole through one of the second grooves. The conductive structure also includes a fifth connecting portion located in each of the first grooves and a sixth connecting portion located in each of the second grooves. Each of the fifth connecting portions is connected to the first connecting portion and one of the third connecting portions, and each of the sixth connecting portions is connected to the second connecting portion and one of the fourth connecting portions, respectively.

4. The stacked capacitor as described in claim 1, characterized in that, Each of the functional areas includes at least two sub-functional areas, and at least two sub-functional areas of the same functional area are arranged along the second direction.

5. The stacked capacitor as described in claim 1, characterized in that, Within the same sub-functional area, the first connecting hole and the second connecting hole are located on opposite sides of the conductive stacked area.

6. The stacked capacitor as described in claim 1, characterized in that, The third connecting hole extends along the second direction and its length is the same as the length of the corresponding conductive part; the first connecting hole extends along a third direction perpendicular to the first direction and the second direction; the fourth connecting hole extends along the second direction and its length is the same as the length of the corresponding conductive part; the second connecting hole extends along a third direction perpendicular to the first direction and the second direction.

7. The stacked capacitor as described in claim 3, characterized in that, The depth of the first groove and the depth of the second groove are both less than the distance between the conductive layer and the top dielectric layer that are furthest apart from the base dielectric layer.

8. The stacked capacitor as described in claim 1, characterized in that, The thickness of the conductive layer ranges from 10 nm to 100 nm; the thickness of the spacer dielectric layer ranges from 5 nm to 50 nm.

9. A semiconductor device, characterized in that, The semiconductor device includes a stacked capacitor as described in any one of claims 1 to 8.

10. The semiconductor device as claimed in claim 9, characterized in that, The semiconductor device further includes a chip, and the stacked capacitor is disposed outside the surface of the chip or inside the chip.

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