A transistor that increases the number of charge carriers in the base region

Abstract

A transistor that increases the number of charge carriers in the base region. This relates to the field of semiconductor technology. It includes a collector electrode, an epitaxial wafer, and a first isolation layer arranged sequentially from bottom to top. The epitaxial wafer has: a first heavily doped base region extending downwards from the top surface of the epitaxial wafer; several second heavily doped emitter regions extending downwards from the top surface of the first heavily doped base regions; multiple first heavily doped second base regions extending downwards from the top surface of the second heavily doped emitter regions; and several base electrodes extending downwards from the top surface of the first isolation layer and connected to the first heavily doped base regions. This invention has advantages such as reducing the base-emitter saturation voltage and dispersing current to avoid local current congestion.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a transistor that increases the number of charge carriers in the base region. Background Technology

[0002] In the field of power electronic device technology, transistors are a commonly used semiconductor device, often used in switching circuits and amplifier circuits. As the power density requirements of power electronic device applications become increasingly higher, the development of high current density transistors has always been an industry trend.

[0003] Existing technologies primarily address current density through process parameters, such as adjusting the emitter doping concentration. A higher emitter doping concentration can increase the carrier injection efficiency, thereby improving the overall device current density. However, after a long period of development, the device structure and process parameters of traditional transistors have become fixed, making it difficult to optimize them to increase current density. Therefore, finding other ways to improve transistor current density is a crucial technical problem that needs to be solved in this case. Utility Model Content

[0004] To address the above problems, this invention provides a transistor that increases the contact area between the emitter and base regions per unit area, thereby increasing the current density per unit area of ​​the transistor and thus increasing the number of charge carriers in the base region.

[0005] The technical solution of this utility model is: A transistor that increases the number of base carriers includes a collector electrode, an epitaxial wafer, and a first isolation layer arranged sequentially from bottom to top. The epitaxial wafer is provided with: The first doped base region extends downward from the top surface of the epitaxial wafer; The second doped emitter region is provided in several forms, each extending downward from the top surface of the first doped base region; The first doped base region is provided in multiple forms, which extend downward from the top surface of the second doped emitter region; The base electrode has several portions, each extending downward from the top surface of the first isolation layer and connected to the first heavily doped base region; The emitter electrode has several portions, each extending downward from the top surface of the first isolation layer, connecting with the second heavily doped emitter region, and forming a good ohmic contact with the second heavily doped emitter region; the longitudinal distance between the emitter electrodes is smaller than the longitudinal distance between the base electrodes.

[0006] Specifically, the thickness of the first heavily doped base region is less than the thickness of the second heavily doped emitter region, and the thickness of the second heavily doped emitter region is less than the thickness of the first heavily doped base region.

[0007] Specifically, the top surface of the second heavily doped emitter region is connected to the first heavily doped base region, the first isolation layer, and the emitter electrode, respectively.

[0008] Specifically, the first heavily doped base region is connected to the first heavily doped base region.

[0009] Specifically, the thickness of the epitaxial wafer is 100-2000 μm.

[0010] Specifically, the thickness of the first heavily doped base region is 1-50 μm.

[0011] Specifically, the thickness of the second heavily doped emitter region is 0.5-49 μm.

[0012] This invention addresses the issue of increasing the current density of transistors by providing a method for fabricating high current density transistors. This method increases the area of ​​the base and emitter junction through an innovative structure, thereby increasing the number of carriers injected from the emitter into the base region. This increases the current density per unit area under the same device area, while also reducing the base-emitter saturation voltage and dispersing the current to avoid local current congestion. Attached Figure Description

[0013] Figure 1 This is the process flow diagram; Figure 2 This is a top view schematic diagram of the fabrication of the first-doped base region; Figure 3 This is a top view schematic diagram of the fabrication of the second-doped emitter region; Figure 4 This is a top view schematic diagram of the fabrication of the first-doped dual-base region; Figure 5 This is a schematic diagram of the structure along the X1 section of the first heavily doped dual-base region; Figure 6 This is a schematic diagram of the structure along the X2 section of the first heavily doped dual-base region; Figure 7 This is a top view schematic diagram of the fabrication of the first isolation layer; Figure 8 This is a top view schematic diagram of the fabrication of the base electrode and emitter electrode; Figure 9 This is a schematic diagram of the fabrication of the base electrode and emitter electrode along the X1 cross section; Figure 10 This is a schematic diagram of the fabrication of the base electrode and emitter electrode along the X2 cross section; Figure 11 This is a schematic diagram of the cross-sectional structure of the current collector electrode; In the figure, 1 is the epitaxial wafer, 2 is the first heavily doped base region, 3 is the second heavily doped emitter region, 4 is the first isolation layer, 5 is the base electrode, 6 is the emitter electrode, 7 is the collector electrode, and 8 is the first heavily doped base region. Detailed Implementation

[0014] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0015] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0016] The following is for reference. Figure 1-11 Describe this utility model; A method for fabricating a transistor that increases the number of charge carriers in the base region includes the following steps: Step S100: A first heavily doped base region 2 is prepared within the epitaxial wafer 1, and several spaced second heavily doped emitter regions 3 are prepared within the first heavily doped base region 2, as shown in the figure. Figure 2-3 As shown; Step S110: Using photolithography, a mask is used to protect the outer region of the first heavily doped base region 2; the first heavily doped base region 2 is formed by diffusion or ion implantation. In step S120, a photolithography process is used to protect the outer region of the second heavily doped emission region 3 using a mask; and a number of spaced second heavily doped emission regions 3 are formed through a diffusion process or an ion implantation process.

[0017] Accordingly, the first and second doped regions are P-regions or N-regions with opposite doping charges. The thickness of epitaxial wafer 1 is 100-2000 μm, the thickness of the first heavily doped base region 2 is set to 1-50 μm, the thickness of the second heavily doped emitter region 3 is set to 0.5-49 μm, the width is set to 1-50 μm, the spacing is set to 1-50 μm, and the N-type doping concentration range is 1e. 14 .cm -3 -1e 20 .cm -3 The doping concentration range for P-type doping is 1e15 .cm -3 -1e 20 .cm -3 The relevant parameter settings are related to the electrical design of the device; In this embodiment, the first doped region is a P-region, the second doped region is an N-region, and the thickness of the epitaxial wafer 1 is 350 μm; the thickness of the first heavily doped base region 2 is 5 μm, and the doping concentration is 1e. 16 .cm -3 The second doped emitter region 3 has a thickness of 3 μm, a width of 20 μm, a spacing width of 10 μm, and a doping concentration of 1e. 19. cm -3 The first heavily doped base region 2 and the second heavily doped emitter region 3 were prepared using ion implantation.

[0018] Step S200: Prepare a first heavily doped dual-base region 8 within the second heavily doped emitter region 3, referring to... Figure 4-6 As shown; Step S210: Using photolithography, a mask is used to protect the outer region of the first heavily doped base region 8; the first heavily doped base region 8 is formed by diffusion or ion implantation.

[0019] Accordingly, the thickness of the first heavily doped base region 8 is set to 0.25-48 μm, a portion of the second heavily doped emitter region 3 extends downward from the top surface of the epitaxial wafer 1, and another portion of the second heavily doped emitter region 3 extends downward from the bottom surface of the first heavily doped base region 8. In this embodiment, the thickness of the first doped base region 8 is 1 μm.

[0020] Step S300: A first isolation layer 4 is prepared on the epitaxial wafer 1, and a window is opened at the first heavily doped base region 2 to prepare the base electrode 5, as shown in the figure. Figure 7-10 As shown; Step S310: Prepare the first isolation layer 4 by chemical vapor deposition, protect the external area of ​​the base electrode 5 by photolithography using a mask, and open the window by etching. Step S320: Use a stripping or etching process to prepare the base electrode 5 at the window opening.

[0021] Correspondingly, the first isolation layer 4 plays a protective role. It is made of SiO2 or Si3N4 and the thickness is set to 10-5000nm. It uses ICP dry etching to open the window. The window extends from the top surface of the first isolation layer 4 downward into the first heavily doped base region 2. The base electrode 5 contacts the first heavily doped base region 2 to form an ohmic contact. The relevant parameter settings are related to the electrical design of the device. In this embodiment, Si3N4 is used as the first isolation layer 4 with a thickness of 200nm. ICP dry etching is used to open the window with a depth of 200nm. A 200nm thick Ti / Al two-layer metal is prepared as the base electrode 5 using a local heavy doping remetallization process and a stripping process.

[0022] Step S400: A window is opened in the second heavily doped emitter region 3 to prepare the emitter electrode 6, as per [reference]. Figure 7-10 As shown; Step S410: Using photolithography, a mask is used to protect the external area of ​​the emitter electrode 6, and an etching process is used to open a window. Step S420: Use a stripping or etching process to prepare the emitter electrode 6 at the window opening; Accordingly, ICP dry etching is used to create a window that extends downward from the top of the first isolation layer 4 into the interior of the second heavily doped emitter region 3. The emitter electrode 6 contacts the second heavily doped emitter region 3 to form an ohmic contact. The relevant parameter settings are related to the electrical design of the device. In this embodiment, ICP dry etching is used to create a window with a depth of 200 nm. A 200 nm thick Ti / Al double metal layer is then prepared as the emitter electrode 6 using a lift-off process.

[0023] Step S500: Fabricate collector electrode 7 on the back side of the epitaxial wafer, referring to... Figure 11 As shown.

[0024] Correspondingly, the epitaxial wafer 1 is thinned to the corresponding thickness through a thinning process, and the collector electrode 7 is prepared on the back side of the epitaxial wafer using a deposition process or a sputtering process; In this embodiment, a thinning process is used to reduce the thickness of the 350µm epitaxial wafer 1 to 180µm, and a deposition process is used to prepare a 1µm thick Ti / Al as the collector electrode 7.

[0025] A transistor that increases the number of base carriers includes a collector electrode 7, an epitaxial wafer 1, and a first isolation layer 4 arranged sequentially from bottom to top. The epitaxial wafer 1 is provided with: The first doped base region 2 extends downward from the top surface of the epitaxial wafer 1; The second doped emitter region 3 is provided with several spaced-apart regions, each extending downward from the top surface of the first doped base region 2 and having a distance between it and the bottom surface of the first doped base region 2. The first doped base region 8 is provided in multiple forms, which extend downward from the top surface of the second doped emitter region 3 and are spaced apart from the bottom surface of the second doped emitter region 3. The first doped base region 8 has a thickness (z-direction) of 1 μm, the second doped emitter region 3 has a thickness of 3 μm, and the first doped base region 2 has a thickness of 5 μm. A portion of the second doped emitter region 3 extends downward from the top surface of the epitaxial wafer 1, and another portion of the second doped emitter region 3 extends downward from the bottom surface of the first doped base region 8. The first doped base region 8 and the first doped base region 2 are connected. The base electrode 5 is provided with several electrodes that extend downward from the top surface of the first isolation layer 4 and are connected to the first heavily doped base region 2, forming a good ohmic contact with the first heavily doped base region (2). The emitter electrode 6 is provided in several parts, which extend downward from the top surface of the first isolation layer 4 and are connected to the second heavily doped emitter region 3, forming a good ohmic contact with the second heavily doped emitter region 3; the longitudinal (y-axis direction) distance of the emitter electrode 6 is less than the longitudinal distance of the base electrode 5.

[0026] The thickness of the first heavily doped base region 8 is less than the thickness of the second heavily doped emitter region 3, and the thickness of the second heavily doped emitter region 3 is less than the thickness of the first heavily doped base region 2.

[0027] The top surface of the second heavily doped emitter region 3 is connected to the first heavily doped base region 8, the first isolation layer 4, and the emitter electrode 6, respectively.

[0028] The first heavily doped base region 8 is connected to the first heavily doped base region 2.

[0029] This innovative structure increases the contact area between the base and emitter junctions. Traditional transistor structures typically form the emitter region by injecting charge into the base region, with the upper surface of the emitter region and the upper surface of the base region on the same plane. Part of the emitter region acts as a buried layer, positioned below the base region, and the upper surface of the buried emitter region contacts the base region, increasing the contact area between the base and emitter junctions. Similarly, the upper surface of the non-buried emitter region is on the same plane as the upper surface of the base region. The height difference between the non-buried and buried emitter regions allows the side of the non-buried emitter region to contact the base region, further increasing the contact area between the base and emitter junctions. By increasing the contact area between the base and emitter junctions, the number of carriers injected from the emitter region into the base region is increased, resulting in a 10%-20% increase in current density per unit area for the same device area. It also offers advantages such as reducing the base-emitter saturation voltage and dispersing current to avoid localized current congestion.

[0030] Regarding the information disclosed in this case, the following points need to be clarified: The accompanying drawings of the embodiments disclosed in this case only relate to the structures involved in the embodiments disclosed in this case; other structures can be referred to with ordinary designs. Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A transistor that increases the number of charge carriers in the base region, characterized in that, It includes a collector electrode (7), an epitaxial wafer (1) and a first isolation layer (4) arranged sequentially from bottom to top; The epitaxial wafer (1) is provided with: The first doped base region (2) extends downward from the top surface of the epitaxial wafer (1); The second doped emitter region (3) is provided in several parts, which extend downward from the top surface of the first doped base region (2); The first doped base region (8) has multiple regions, which extend downward from the top surface of the second doped emitter region (3); The base electrode (5) is provided with several electrodes, which extend downward from the top surface of the first isolation layer (4) and are connected to the first heavily doped base region (2); The emitter electrode (6) is provided in several parts, which extend downward from the top surface of the first isolation layer (4) and are connected to the second heavily doped emitter region (3), forming a good ohmic contact with the second heavily doped emitter region (3); the longitudinal distance of the emitter electrode (6) is smaller than the longitudinal distance of the base electrode (5).

2. A transistor for increasing the number of charge carriers in the base region according to claim 1, characterized in that, The thickness of the first heavily doped base region (8) is less than the thickness of the second heavily doped emitter region (3), and the thickness of the second heavily doped emitter region (3) is less than the thickness of the first heavily doped base region (2).

3. A transistor for increasing the number of charge carriers in the base region according to claim 1, characterized in that, The top surface of the second heavily doped emitter region (3) is connected to the first heavily doped base region (8), the first isolation layer (4), and the emitter electrode (6), respectively.

4. A transistor for increasing the number of charge carriers in the base region according to claim 1, characterized in that, The side of the first heavily doped base region (8) is connected to the first heavily doped base region (2).

5. A transistor for increasing the number of charge carriers in the base region according to claim 1, characterized in that, The thickness of the epitaxial wafer (1) is 100-2000um.

6. A transistor for increasing the number of charge carriers in the base region according to claim 1, characterized in that, The thickness of the first heavily doped base region (2) is 1-50 μm.

7. A transistor for increasing the number of charge carriers in the base region according to claim 1, characterized in that, The thickness of the second heavily doped emission region (3) is 0.5-49 μm.

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