Thin-film transistors and electronic devices including such thin-film transistors

Abstract

A thin-film transistor (TFT) and an electronic device including the TFT are disclosed. The TFT includes a substrate, a barrier layer disposed on the substrate, and an active patterned layer disposed on the barrier layer and including a first region and a second region adjacent to the first region. The second region includes an opening. Therefore, characteristic changes caused by gas inflow into the upper and lower parts of the TFT can be eliminated.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0068537, filed on May 27, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosure relates to a thin-film transistor, a method for manufacturing the thin-film transistor, and an electronic device including the thin-film transistor. Background Technology

[0003] Transistors are widely used as switching or driving devices in the field of electronic devices. Specifically, because thin-film transistors are manufactured on glass or plastic substrates, they are useful in the field of display devices. Utility Model Content

[0004] The purpose of this invention is to provide a thin-film transistor capable of eliminating (or reducing) characteristic changes (or characteristic degradation) caused by external influences, a method for manufacturing the thin-film transistor, and an electronic device including the thin-film transistor.

[0005] However, the embodiments are not limited to those described herein. The above and other embodiments will become more apparent to those skilled in the art from the following detailed description of the disclosure.

[0006] According to an embodiment, a thin-film transistor may include: a substrate; a barrier layer disposed on the substrate; and an active patterned layer disposed on the barrier layer, including a first region and a second region adjacent to the first region, wherein the second region may include an opening.

[0007] The openings can be arranged in a regular pattern.

[0008] The openings can be arranged irregularly.

[0009] The opening can be circular or polygonal.

[0010] The size of the opening can vary depending on the width of the active patterned layer and the length of each in the second region.

[0011] The total size of the opening can be approximately 10% to approximately 80% of the total size of the second region.

[0012] The opening allows gas flowing into the second zone to be discharged.

[0013] The gas may include at least one of hydrogen, oxygen, moisture, and etching gas.

[0014] The active patterned layer may include oxide semiconductors.

[0015] The thin-film transistor may further include: a gate insulating pattern layer disposed on a first region; a gate electrode disposed on the gate insulating pattern layer; a passivation layer covering the barrier layer, the active pattern layer, the gate insulating pattern layer and the gate electrode; a source electrode penetrating the passivation layer and electrically connected to one of the second regions; and a drain electrode penetrating the passivation layer and electrically connected to the other of the second regions.

[0016] According to an embodiment, a method of manufacturing a thin-film transistor may include the following steps: forming an active layer on a barrier layer on a substrate; forming an active patterned layer by etching the active layer; forming a first region and a second region adjacent to the first region by partially doping the active patterned layer; and forming an opening in the second region.

[0017] The first region can be an undoped region, and the second region can be a doped region.

[0018] The opening allows hydrogen flowing from the barrier layer into the second region to be discharged.

[0019] The method may further include: forming a gate insulating layer covering the barrier layer and the active patterned layer; and etching the gate insulating layer to form a gate insulating patterned layer on the first region.

[0020] The opening allows etching gases flowing into the second region to escape during the etching process of the gate insulating layer.

[0021] The method may further include: forming a gate electrode on a gate insulating pattern layer; and forming a passivation layer to cover the barrier layer, the active pattern layer, the gate insulating pattern layer, and the gate electrode.

[0022] The opening allows hydrogen flowing from the passivation layer into the second region to be discharged.

[0023] The method may also include forming a first contact hole and a second contact hole by etching a passivation layer.

[0024] The opening allows etching gases flowing into the second region to escape during the etching process of the passivation layer.

[0025] The method may further include: forming a source electrode electrically connected to one of the second regions through a first contact hole; and forming a drain electrode electrically connected to another of the second regions through a second contact hole.

[0026] According to an embodiment, the electronic device may include: a processor for providing input image data; and a display device for displaying an image based on the input image data, the display device including a thin-film transistor. The thin-film transistor may include: a substrate; a barrier layer disposed on the substrate; and an active patterned layer disposed on the barrier layer, including a first region and a second region adjacent to the first region, the second region including an opening. Attached Figure Description

[0027] The above and other features will become more apparent from the description of the disclosed embodiments with reference to the accompanying drawings.

[0028] Figure 1 This is a schematic cross-sectional view showing a thin-film transistor according to an embodiment.

[0029] Figure 2 It is shown Figure 1 A schematic cross-sectional view of the variation in channel length in a thin-film transistor.

[0030] Figure 3 This is a schematic cross-sectional view showing a thin-film transistor according to an embodiment.

[0031] Figure 4 This illustrates an embodiment. Figure 3 A schematic plan view of the active patterned layer.

[0032] Figure 5 This illustrates an embodiment. Figure 3 A schematic plan view of the active patterned layer.

[0033] Figures 6 to 15 This is a schematic cross-sectional view illustrating a method for manufacturing a thin-film transistor according to an embodiment.

[0034] Figure 16 This is a block diagram of an electronic device according to an embodiment.

[0035] Figure 17 Schematic diagrams of various embodiments of the electronic device are shown. Detailed Implementation

[0036] In the following, preferred embodiments according to the disclosure are described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the parts necessary for understanding the operation according to the disclosure are described, and descriptions of other parts are omitted so as not to obscure the subject matter of the disclosure. Furthermore, the disclosure may be implemented in other forms and is not limited to the embodiments described herein. However, the embodiments described herein are provided in sufficient detail to allow those skilled in the art to readily implement the technical spirit of the disclosure.

[0037] Throughout this specification, the phrase "connected to" another part includes not only cases where the part is "directly connected" to the other part, but also cases where the part is "indirectly connected" to the other part with another element placed therebetween. The terminology used herein is for describing particular embodiments and is not intended to limit the disclosure. Throughout this specification, the phrase "comprising" means, unless otherwise stated, that the part may further include another component without excluding it. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ). Here, "and / or" includes all combinations of one or more of the corresponding constructions.

[0038] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Therefore, without departing from the scope disclosed herein, within a certain range, "first component" may refer to "second component".

[0039] Spatial relative terms such as “below” and “above” can be used for descriptive purposes to describe the relationship between one element or feature and another element(s) as shown in the accompanying drawings. In addition to the directions depicted in the drawings, spatial relative terms are intended to include other orientations in use, operation, and / or manufacture. For example, when the device shown in the drawings is inverted, the element depicted as positioned “below” other elements or features is positioned in an orientation “above” said other elements or features. Therefore, in embodiments, the term “below” can include both above and below orientations. Additionally, the device may face other orientations (e.g., rotated 90 degrees or in other orientations), and thus the spatial relative terms used herein should be interpreted accordingly.

[0040] Various embodiments are described with reference to the accompanying drawings, which schematically illustrate preferred embodiments. Therefore, the intended shape may vary, for example, depending on tolerances and / or manufacturing techniques. Consequently, the embodiments disclosed herein should not be construed as limited to the specific shapes shown and should be interpreted as including shape variations, for example, that occur due to manufacturing processes. As noted above, the shapes shown in the drawings may not represent the actual shape of areas of the device, and the embodiments are not limited thereto.

[0041] The disclosed embodiments are described in detail below with reference to the accompanying drawings.

[0042] Figure 1 This is a schematic cross-sectional view showing a thin-film transistor according to an embodiment. Figure 2It is shown Figure 1 A schematic cross-sectional view of the variation in channel length in a thin-film transistor.

[0043] Reference Figure 1 and Figure 2 The barrier layer BRL can be disposed on the substrate SUB. The substrate SUB can be a glass substrate, but the embodiments are not limited thereto. For example, the substrate SUB can be any of a variety of substrates used in semiconductor device manufacturing processes (such as a plastic substrate or a silicon substrate). The barrier layer BRL can provide a smooth interface for depositing the active patterned layer AP. For example, the barrier layer BRL can improve the crystal quality of the active patterned layer AP or reduce defects. The barrier layer BRL can include silicon dioxide (SiO2) and silicon nitride (SiN). x At least one of the following, but the embodiments are not limited thereto.

[0044] An active patterned layer (AP) can be disposed on a barrier layer (BRL). In embodiments, the active patterned layer (AP) may include an oxide semiconductor. For example, the active patterned layer (AP) may include indium gallium zinc oxide (IGZO) or indium tin gallium zinc oxide (ITGZO), but embodiments are not limited thereto. In embodiments, the active patterned layer (AP) may include an amorphous oxide semiconductor. For example, the active patterned layer (AP) may include amorphous indium gallium zinc oxide (a-IGZO) or amorphous indium tin gallium zinc oxide (a-ITGZO), but embodiments are not limited thereto.

[0045] The active patterned layer AP may include a first region A1 and a second region A2 adjacent to the first region A1. The first region A1 may be an undoped region and may have a lower conductivity than the second region A2. The first region A1 may be a region through which charge carriers (e.g., holes or electrons) flow and may also be referred to as a channel region. The second region A2 may be a doped region and may have a higher conductivity than the first region A1. For example, the second region A2 may be doped with an n-type dopant (e.g., ...). Figure 8 (NP in the second region A2), but the embodiments are not limited to this. One of the second regions A2 can be a region supplying charge carriers, and can also be referred to as a source region. For example, one of the second regions A2 can refer to a region set in the second region A2. Figure 1 The second region A2 on the left side of the diagram. Another region in the second region A2 can be the area where carriers supplied from the source region are discharged after passing through the channel region, and can also be referred to as the drain region. For example, another region in the second region A2 can refer to the area set in... Figure 1 The second region A2 on the right side of the image.

[0046] A gate insulating pattern layer (GIP) may be disposed on the first region A1. The gate insulating pattern layer (GIP) can serve to separate the gate electrode GE from the first region A1. The gate insulating pattern layer (GIP) may include an insulator. For example, the gate insulating pattern layer (GIP) may include silicon dioxide (SiO2), but the embodiments are not limited thereto.

[0047] The gate electrode GE can be disposed on the gate insulating pattern layer GIP. The gate electrode GE can control the flow of charge carriers. The gate electrode GE can include metal. For example, the gate electrode GE can have a single-layer structure or a multi-layer structure including at least one of molybdenum (Mo), aluminum (Al), copper (Cu) and titanium (Ti).

[0048] The passivation layer PVL can be deposited on the barrier layer BRL, active patterned layer AP, and gate electrode GE. The passivation layer PVL can surround (or cover) the barrier layer BRL, active patterned layer AP, gate insulating patterned layer GIP, and gate electrode GE. The passivation layer PVL serves to prevent external damage caused by scratches, moisture, etc. The passivation layer PVL can include silicon dioxide (SiO2) and silicon nitride (SiN). x The passive layer PVL may include at least one of the following, but the embodiments are not limited thereto. The passive layer PVL may include a first contact hole CH1 and a second contact hole CH2 for the electrical connection structure.

[0049] The source electrode SE can be disposed on the passivation layer PVL. The source electrode SE can penetrate the passivation layer PVL and be electrically connected to one of the second regions A2. For example, the source electrode SE can be electrically connected to the source region through the first contact hole CH1. The source electrode SE can include a metal. For example, the source electrode SE can have a single-layer structure or a multi-layer structure including at least one of aluminum (Al), copper (Cu), and titanium (Ti).

[0050] The drain electrode DE can be disposed on the passivation layer PVL. The drain electrode DE can penetrate the passivation layer PVL and be electrically connected to another region A2. For example, the drain electrode DE can be electrically connected to the drain region through the second contact hole CH2. The drain electrode DE can include a metal. For example, the drain electrode DE can have a single-layer structure or a multi-layer structure including at least one of aluminum (Al), copper (Cu), and titanium (Ti).

[0051] The characteristics of a thin-film transistor (TFT) may be affected by the length L1 of the first region A1 (or channel region). (Refer to...) Figure 2The active patterned layer AP, including the oxide semiconductor, can have the characteristic of absorbing gases flowing in from the outside. Therefore, the length L1 of the first region A1 may be changed by the gases flowing into the upper and lower parts of the active patterned layer AP. For example, if the carrier concentration in the second region A2 is changed by the gas and the length L2 of the second region A2 increases, the length L1 of the first region A1 may decrease. When the length L1 of the first region A1 decreases, the characteristics of the thin-film transistor (TFT) may change. For example, as the length L1 of the first region A1 decreases, a negative offset may occur, in which the threshold voltage of the thin-film transistor (TFT) shifts in the negative direction.

[0052] Figure 3 This is a schematic cross-sectional view showing a thin-film transistor according to an embodiment. Regarding Figure 3 Brief description or omission of [something] Figure 1 and Figure 2 Duplicate content.

[0053] Reference Figure 3 The second region A2 may include an opening OP. For example, the source and drain regions may include openings OP. An opening OP may refer to a hole, wire, etc., penetrating the second region A2. The opening OP can eliminate (or reduce) the influence of gas flowing into the second region A2. For example, the opening OP can discharge gas flowing into the upper part of the second region A2 to the lower part. For example, the opening OP can discharge gas flowing into the lower part of the second region A2 to the upper part. For example, the opening OP can allow gas flowing into the second region A2 to be discharged to the outside instead of remaining in the second region A2. Therefore, even when gas flows into the second region A2, since the length L1 of the first region A1 and the length L2 of the second region A2 remain unchanged, the characteristic changes of the thin-film transistor TFT', such as negative offset, can not occur. For example, the influence of gas on the thin-film transistor TFT' can be eliminated (or reduced) by the opening OP.

[0054] Figure 4 This illustrates an embodiment. Figure 3 A schematic plan view of the active patterned layer. Figure 5 This illustrates an embodiment. Figure 3 A schematic plan view of the active patterned layer.

[0055] Reference Figure 4 The opening OP of the active patterned layer AP can be circular. However, the embodiments are not limited to this. For example, the opening OP can be one of various polygonal shapes, such as triangular or quadrilateral shapes. In the following, for ease of description, it is assumed that the opening OP is circular.

[0056] The size (or area) of each of the openings OP can vary depending on the size (or area) of each of the second regions A2. For example, the size of the opening OP can vary depending on the width W and length L2 of the second region A2. For example, the total size (or area) occupied by the openings OP within the second region A2 can be from about 10% to about 80% of the total size (or area) of the second region A2. However, the embodiments are not limited thereto. As an example, the size (or area) of each of the openings OP applied to a large panel in which the width W of the second region A2 is in the range of about 38 μm to about 60 μm and the length L2 of the second region A2 is about 10 μm can be in the range of about 1 μm to about 2 μm.

[0057] The openings (OPs) can be arranged regularly within the second region A2. For example, the openings (OPs) can be arranged in a 6×6 matrix within the second region A2. However, the embodiment is not limited to this. For example, as long as the openings (OPs) are arranged regularly, their shape or number is not limited to this. See also Figure 5 The opening OP of the active pattern layer AP' can be irregularly arranged in the second region A2.

[0058] Figures 6 to 15 This is a schematic cross-sectional view illustrating a method for manufacturing a thin-film transistor according to an embodiment.

[0059] Reference Figure 6 After forming a barrier layer (BRL) on the substrate (SUB), an active layer (AL) can be formed on the barrier layer (BRL). The active layer (AL) may include an oxide semiconductor such as indium gallium zinc oxide (IGZO) or indium tin gallium zinc oxide (ITGZO), but the embodiments are not limited thereto. The active layer (AL) can be deposited by thin film deposition methods such as sputtering, pulsed laser deposition, or electron beam deposition, but the embodiments are not limited thereto.

[0060] Reference Figure 7 This can be achieved by modifying the active layer AL (see...) Figure 6 The active patterned layer AP is formed by patterning. The active patterned layer AP can be formed by photolithography, but the embodiments are not limited to this.

[0061] Reference Figure 8 The active patterned layer AP can be partially doped. For example, a first region A1 and a second region A2 adjacent to the first region A1 can be formed by an ion doping process. The first region A1 can be an undoped region, and the second region A2 can be a doped region. The second region A2 can be doped with an n-type dopant NP, but the embodiments are not limited to this.

[0062] Reference Figure 9An opening OP can be formed in the second region A2. For example, an opening OP penetrating the second region A2 can be formed by methods such as punching or etching. When an opening OP is formed in the second region A2, gas flowing into the lower part of the active patterned layer AP can be discharged to the outside. For example, hydrogen flowing into the second region A2 from the barrier layer BRL can be discharged to the outside through the opening OP. For example, oxygen, moisture, etc. introduced from the outside can also be discharged to the outside through the opening OP. Therefore, since the influence of gas originating from the barrier layer BRL is eliminated (or reduced), the length L1 of the first region A1 (or channel region) and the length L2 of the second region A2 (or source and drain regions) can remain unchanged.

[0063] Reference Figure 10 A gate insulating layer (GIL) can be formed on the barrier layer (BRL) and the active patterned layer (AP). (See reference...) Figure 11 This can be achieved by modifying the gate insulating layer GIL (see Figure 10 The gate insulating pattern layer (GIP) is formed by patterning. For example, the GIP can be formed by an etching process. When an opening (OP) is formed in the second region A2, the gas flowing into the upper part of the active pattern layer AP can be exhausted to the outside. For example, the etching gas EG used in the etching process can be exhausted to the outside through the opening OP. For example, oxygen, moisture, etc. introduced from the outside can also be exhausted to the outside through the opening OP. Therefore, since the influence of the gas caused by the etching process is eliminated, the length L1 of the first region A1 and the length L2 of the second region A2 can remain unchanged.

[0064] Reference Figure 12 The gate electrode GE can be formed on the gate insulating pattern layer GIP. (See reference...) Figure 13 The passivation layer PVL can be formed as a cover barrier layer BRL, an active patterned layer AP, a gate insulating patterned layer GIP, and a gate electrode GE. When an opening OP is formed in the second region A2, the gas flowing into the upper part of the active patterned layer AP can be exhausted to the outside. Examples include materials such as silicon dioxide (SiO2) or silicon nitride (SiN). x The passivation layer PVL of the inorganic material can block gases such as oxygen and moisture, but may have high hydrogen release characteristics. Hydrogen flowing from the passivation layer PVL into the second region A2 can be discharged to the outside through the opening OP. At the same time, oxygen, moisture, etc. introduced (or permeated) from the outside can also be discharged to the outside through the opening OP. Therefore, since the influence of gases introduced (or permeated) from the passivation layer PVL is eliminated, the length L1 of the first region A1 and the length L2 of the second region A2 can remain unchanged.

[0065] Reference Figure 14A first contact hole CH1 and a second contact hole CH2 can be formed to penetrate the passivation layer PVL. The first contact hole CH1 and the second contact hole CH2 can be formed through an etching process. When an opening OP is formed in the second region A2, the gas flowing into the upper part of the active patterned layer AP can be discharged to the outside. For example, the etching gas EG used in the etching process can be discharged to the outside through the opening OP. For example, oxygen, moisture, etc., introduced from the outside can also be discharged to the outside through the opening OP. Therefore, since the influence of gas caused by the etching process is eliminated, the length L1 of the first region A1 and the length L2 of the second region A2 can remain unchanged.

[0066] Reference Figure 15 This allows the formation of a source electrode SE and a drain electrode DE. The source electrode SE can be electrically connected to one of the second regions A2 (or the source region) through the first contact hole CH1. The drain electrode DE can be electrically connected to the other of the second regions A2 (or the drain region) through the second contact hole CH2.

[0067] According to embodiments, a thin-film transistor capable of eliminating characteristic changes caused by gas flowing into the upper and lower parts of the thin-film transistor, and a method for manufacturing the thin-film transistor, can be provided.

[0068] However, the effects of disclosure are not limited to those described above, and can be extended in various ways without departing from the spirit and scope of disclosure.

[0069] The display device according to the embodiments is applicable to various types of electronic devices. In the embodiments, the electronic device includes a display device, and may also include other modules or devices with additional functions in addition to the display device.

[0070] Figure 16 This is a block diagram of an electronic device according to an embodiment. (Refer to...) Figure 16 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0071] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0072] The memory 13 can store data and / or information used to operate the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11. The display module 11 can process the provided signals and output image information on the display screen.

[0073] The power module 14 may include a power supply module (such as a power adapter or battery device) and a power conversion module. The power conversion module converts the power supplied by the power supply module and generates power to operate the electronic device 10.

[0074] At least one of the aforementioned components of the electronic device 10 may be included in the display device according to the embodiment described above. Additionally, in terms of function, some of the modules included in a single module may be included in the display device, while other modules may be disposed separately from the display device. For example, the display module 11 may be included in the display device, while the processor 12, memory 13, and power module 14 may not be included in the display device but may be disposed separately in the electronic device 10.

[0075] Figure 17 Schematic diagrams of various embodiments of the electronic device are shown.

[0076] Reference Figure 17 Various types of electronic devices in embodiments of the application display device may include electronic devices for displaying images (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, and desktop monitors 10_1e), wearable electronic devices including display modules (such as smart glasses 10_2a, head-mounted displays (HMDs) 10_2b, and smartwatches 10_2c), and automotive electronic devices 10_3 including display modules (such as central information displays (CIDs) and interior mirror displays disposed in the instrument cluster, center dashboard, and dashboard of a vehicle).

[0077] Although the disclosure has been described with reference to the above embodiments, it should be noted that the above embodiments are for illustrative purposes and not for limiting the scope of the disclosure. Those skilled in the art will understand that various modifications are possible within the scope of the disclosed technical spirit.

[0078] The scope of disclosure is not limited to the details described in the detailed description of the specification, but should also be defined by the claims. It will be understood that all changes or modifications derived from the meaning and scope of the claims and their equivalents are included within the scope of disclosure.

Claims

1. A thin-film transistor, characterized in that, The thin-film transistor includes: Base; A barrier layer is disposed on the substrate; and An active patterned layer is disposed on the barrier layer and includes a first region and a second region adjacent to the first region. The second region includes an opening.

2. The thin-film transistor according to claim 1, characterized in that, The openings are arranged regularly.

3. The thin-film transistor according to claim 1, characterized in that, The opening has a circular or polygonal shape.

4. The thin-film transistor according to claim 1, characterized in that, The size of each of the openings varies according to the width of the active patterned layer and the length of each of the openings in the second region.

5. The thin-film transistor according to claim 4, characterized in that, The total size of the opening is 10% to 80% of the total size of the second region.

6. The thin-film transistor according to claim 1, characterized in that, The opening discharges gas that flows into the second region.

7. The thin-film transistor according to claim 1, characterized in that, The thin-film transistor further includes: A gate insulating pattern layer is disposed on the first region; The gate electrode is disposed on the gate insulating pattern layer; A passivation layer covers the barrier layer, the active pattern layer, the gate insulating pattern layer, and the gate electrode; The source electrode penetrates the passivation layer and is electrically connected to one of the second regions; and The drain electrode penetrates the passivation layer and is electrically connected to another electrode in the second region.

8. An electronic device, characterized in that, The electronic device includes: A processor for providing input image data; and A display device for displaying an image based on the input image data, the display device including a thin-film transistor. The thin-film transistor includes: a substrate; a barrier layer disposed on the substrate; and an active patterned layer disposed on the barrier layer, including a first region and a second region adjacent to the first region. The second region includes an opening.

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