Array substrate and electronic paper

Abstract

This utility model discloses an array substrate and electronic paper. The array substrate includes a substrate and a thin film stack layer stacked on one side of the substrate. The thin film stack layer includes a first metal layer, a first metal insulating layer, a second metal layer, and a third metal layer stacked sequentially on one side of the substrate. The thin film stack layer forms multiple pixel regions arranged in an array and multiple scan lines extending along a first direction. Each pixel region includes a thin film transistor. The gate of the thin film transistor is located on the first metal layer, and the gates of thin film transistors in the same row are connected. The scan lines are located on the second metal layer. Each scan line is connected to the gate of a row of thin film transistors through a transfer via. The transfer via is located in the transfer region of the first metal insulating layer, and the vertical projection of the transfer region on the substrate coincides with the vertical projection of the overlapping area of ​​the first, second, and third metal layers on the substrate. Therefore, this invention can avoid the influence of the transfer via of the scan lines on the display image.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and in particular to an array substrate and electronic paper. Background Technology

[0002] Currently, the scan lines pass through vias in the display area for layer transfer. However, the vias for layer transfer in existing electronic paper occupy a large space, and there is no signal shielding layer at the position close to the display electronic paper film. As a result, when the scan lines transmit signals through the vias, there will be physical visual differences in the display position corresponding to the position of the via. The display position corresponding to the position of the via will be affected by electric field coupling, resulting in poor display effect.

[0003] Figure 1 A structural layout of an array substrate provided for the prior art. Figure 2 A cross-sectional view of an array substrate at the location of a transfer via, provided in the prior art. Figure 3 An application provided by existing technology Figure 1 An illustration of the display effect of electronic paper. (For example...) Figures 1-3 As shown, due to the large space occupied by the transfer via 01 in the electronic paper, a physical visual difference occurs in the display image corresponding to the location of the transfer via 01. Furthermore, the location of the transfer via 01 near the electronic paper film lacks a signal shielding layer. When the scan line 02 connects to the gate connection line 04 of a row of thin-film transistors through the transfer via 01 to transmit the scan signal, the electronic ink on the electronic paper film corresponding to the location of the transfer via 01 is affected by electric field coupling, resulting in poor display quality. Figure 3 As shown, the transfer via 01 of the array substrate is set along the diagonal, and an abnormal dark line appears along the diagonal on the corresponding electronic paper display. Utility Model Content

[0004] This invention provides an array substrate and electronic paper to avoid the influence of the scan line transfer vias on the display screen, thereby improving the display effect.

[0005] In a first aspect, the present invention provides an array substrate, which includes a substrate and a thin film stack layer stacked on one side of the substrate. The thin film stack layer includes a first metal layer, a first metal insulating layer, a second metal layer and a third metal layer stacked sequentially on one side of the substrate.

[0006] The thin film stack layer forms multiple pixel regions arranged in an array and multiple scan lines extending along a first direction, each pixel region including a thin film transistor; the first direction is the column direction of the pixel regions;

[0007] The gate of the thin-film transistor is located in the first metal layer, and the gates of the thin-film transistors in the same row are connected; the scan line is located in the second metal layer;

[0008] Each scan line is connected to the gate of a row of thin-film transistors through a transfer via. The transfer via is disposed in the transfer region of the first metal insulating layer. The vertical projection of the transfer region on the substrate coincides with the vertical projection of the overlapping region of the first metal layer, the second metal layer and the third metal layer on the substrate.

[0009] Optionally, each pixel region further includes a pixel electrode;

[0010] The pixel electrode is located in the third metal layer.

[0011] Optionally, each of the scan lines is disposed on one side of a column of thin-film transistors.

[0012] Optionally, the thin film stack layer may also form a plurality of data lines extending along the first direction;

[0013] Each of the data lines is disposed on one side of a column of thin-film transistors, and each of the data lines is connected to the first electrode of a column of thin-film transistors; both the data lines and the first electrode of the thin-film transistors are located in the second metal layer.

[0014] Optionally, the thin film stack layer further includes a planarization layer disposed between the second metal layer and the third metal layer.

[0015] Optionally, the thin film stack layer further includes a transparent conductive layer disposed on the side of the third metal layer away from the second metal layer.

[0016] Optionally, the array substrate further includes a scanning circuit; the scanning circuit is located in the border area on both sides of the display area along a first direction; the scanning circuit is connected to each of the scanning lines.

[0017] Optionally, the thin film stack layer further includes a scan signal repair layer stacked on the side of the third metal layer away from the second metal layer;

[0018] The scan signal repair layer is located in the border area and surrounds the display area;

[0019] Each of the scan lines extends into the border area;

[0020] The vertical projection of the scan signal repair layer on the substrate overlaps with the vertical projection of the portion of the scan line extending to the border area on the substrate.

[0021] Optionally, the scan signal repair layer includes a plurality of first laser repair points;

[0022] The vertical projection of each of the first laser repair points on the substrate coincides with the vertical projection of the portion of the scan line extending to the border area on the substrate;

[0023] Each of the scan lines includes a second laser repair point;

[0024] The vertical projection of the second laser repair point on the substrate coincides with the vertical projection of the first metal layer corresponding to the gate connection of the thin-film transistor on the substrate.

[0025] Secondly, this utility model embodiment also provides an electronic paper, which includes the array substrate provided in this utility model embodiment.

[0026] This embodiment of the invention places the transfer via in the transfer region of the first metal insulating layer, and the vertical projection of the transfer region onto the substrate coincides with the vertical projection of the overlapping region of the first, second, and third metal layers onto the substrate. Therefore, the third metal layer can shield the transfer via and the portion of each scan line that connects to the gate of a row of thin-film transistors through the transfer via, ensuring no physical visual difference in the display image corresponding to the transfer via position. The third metal layer can also shield the electric field generated by the scan signal transmitted by the scan line, thereby preventing the electronic ink on the electronic paper film from being affected by electric field coupling and improving the display effect of the electronic paper film. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A structural layout of an array substrate provided for the prior art;

[0029] Figure 2 A cross-sectional view of an array substrate at the location of a transfer via, provided in the prior art;

[0030] Figure 3 An application provided by existing technology Figure 1 A diagram illustrating the display effect of electronic paper;

[0031] Figure 4 A structural layout of an array substrate provided for an embodiment of this utility model;

[0032] Figure 5 A cross-sectional view of an array substrate at the location of a transfer via, provided for an embodiment of this utility model;

[0033] Figure 6 A cross-sectional view of another array substrate at the location of the transfer via provided in an embodiment of this utility model;

[0034] Figure 7 A schematic diagram of the positional structure of the scan line and the scan signal repair layer provided in an embodiment of this utility model;

[0035] Figure 8 for Figure 7 A sectional view along line A-A';

[0036] Figure 9 This is a structural layout of another array substrate provided in an embodiment of the present invention. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0038] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0039] This solution proposes an array substrate to reduce the impact of the scan line transfer vias on the display image, thereby improving the display effect. Figure 4 This invention provides a structural layout of an array substrate according to an embodiment of the present invention. Figure 5 This is a cross-sectional view of an array substrate at the location of a transfer via, provided as an embodiment of the present invention. Figure 4 and Figure 5As shown, the array substrate includes a substrate 10 and a thin film stack layer 20 stacked on one side of the substrate 10. The thin film stack layer 20 includes a first metal layer 210, a first metal insulating layer 220, a second metal layer 230 and a third metal layer 240 stacked sequentially on one side of the substrate 10.

[0040] The thin film stack layer 20 forms a plurality of pixel regions 21 arranged in an array and a plurality of scan lines 22 extending along a first direction Y. Each pixel region 21 includes a thin film transistor; the first direction Y is the column direction of the pixel regions 21.

[0041] The gate of the thin-film transistor is located on the first metal layer 210, and the gates of the thin-film transistors in the same row are connected; the scan line 22 is located on the second metal layer 230;

[0042] Each scan line 22 is connected to the gate of a row of thin film transistors through a transfer via. The transfer via is located in the transfer region of the first metal insulating layer 220. The vertical projection of the transfer region on the substrate 10 coincides with the vertical projection of the overlapping region of the first metal layer 210, the second metal layer 230 and the third metal layer 240 on the substrate 10.

[0043] Each through-hole is used to assist a second metal layer 230, which is configured as a scan line 22, in connecting with a first metal layer 210, which is configured as a row of thin-film transistor gates, so that a scan line 22 provides a scan signal to a row of thin-film transistor gates.

[0044] Furthermore, the vertical projection of each transfer via on the substrate 10 coincides with the vertical projection of the overlapping area of ​​the first metal layer 210, the second metal layer 230, and the third metal layer 240 on the substrate 10. Clearly, the transfer via is located below the third metal layer 240. That is, each scan line 22 connects to the gate of a row of thin-film transistors through a transfer via below the third metal layer 240. Therefore, the transfer via and the connection of each scan line 22 to the gate of a row of thin-film transistors through a transfer via are blocked by the third metal layer 240 located above them, thus preventing any physical visual difference in the display image corresponding to the position of the transfer via.

[0045] The third metal layer 240, which shields the transfer via and the portion of each scan line 22 that is connected to the gate of a row of thin-film transistors through a transfer via, can also shield the electric field generated by the scan signal transmitted by the scan line 22. This prevents the electronic ink on the electronic paper film disposed on the side of the third metal layer 240 away from the substrate 10 from being affected by electric field coupling, thereby improving the display effect of the electronic paper film display.

[0046] It should be noted that the illustration is only illustrative of the positional relationship between the second metal layer 230 and the third metal layer 240. There is an electrical isolation layer (not shown) between them, and they are not electrically connected. The first metal layer 210 and the second metal layer 230 can be electrically connected through a transfer via. In addition, a first metal insulating layer 220 is provided between the first metal layer 210 and the second metal layer 230 to isolate them from electrical connection.

[0047] In this embodiment of the invention, the transfer via is disposed in the transfer region of the first metal insulating layer 220, and the vertical projection of the transfer region on the substrate 10 coincides with the vertical projection of the overlapping region of the first metal layer 210, the second metal layer 230, and the third metal layer 240 on the substrate 10. Therefore, the third metal layer 240 can shield the transfer via and the portion of each scan line 22 connected to the gate of a row of thin-film transistors through a transfer via, ensuring that there is no physical visual difference in the display image corresponding to the position of the transfer via; the third metal layer 240 can also shield the electric field generated by the scan line 22 transmitting the scan signal, thereby preventing the electronic ink of the electronic paper film from being affected by electric field coupling and improving the display effect of the electronic paper film.

[0048] Based on the above embodiments, alternatively, refer to the following: Figure 4 Each pixel region 21 also includes a pixel electrode 241; the pixel electrode 241 is located in the third metal layer 240. Each scan line 22 is disposed on one side of a column of thin-film transistors.

[0049] The pixel electrode 241 covers each pixel area 21, meaning that the vertical projection of the pixel electrode 241 onto the substrate 10 covers the vertical projection of the thin film transistor onto the substrate 10 and the partial vertical projection of the scan line 22 adjacent to the thin film transistor onto the substrate 10.

[0050] Based on the above embodiments, alternatively, refer to the following: Figure 4 The thin film stacked layer 20 also forms a plurality of data lines 23 extending along the first direction Y; each data line 23 is disposed on one side of a column of thin film transistors, and each data line 23 is connected to the first electrode of a column of thin film transistors; the data lines 23 and the first electrodes of the thin film transistors are both located in the second metal layer 230.

[0051] In this configuration, the second electrode of each thin-film transistor is connected to the pixel electrode 241 of the same pixel region 21. The data line 23 is used to provide a data voltage to the thin-film transistor. When the gate of the thin-film transistor controls its conduction, the data voltage provided by the data line 23 to the thin-film transistor can be written to the pixel electrode 241.

[0052] Based on the above embodiments, optionally, Figure 6A cross-sectional view of another array substrate provided in an embodiment of this utility model at the location of the transfer via. (See figure) Figure 6 As shown, the thin film stack 20 further includes a planarization layer 250, which is disposed between the second metal layer 230 and the third metal layer 240. The thin film stack 20 also includes a transparent conductive layer 260, which is disposed on the side of the third metal layer 240 away from the second metal layer 230.

[0053] The planarization layer 250 protects the underlying structure, optimizes the flatness of the surface of the second metal layer 230, and prevents unnecessary conductivity between the second metal layer 230 and the third metal layer 240. The transparent conductive layer 260 has strong water vapor permeability and can effectively prevent water vapor from penetrating the underlying metal layer.

[0054] Optionally, based on the above embodiments, the array substrate further includes a scanning circuit; the scanning circuit is disposed in the border area located on both sides of the display area along the first direction Y; the scanning circuit is connected to each scanning line 22.

[0055] The scanning circuit is located on the border area on both sides of the display area along the first direction Y, and the scanning line 22 extends along the first direction Y. By setting the scanning circuit in the extension direction of the scanning line 22, the length and complexity of the scanning line 22 can be simplified, and the width of the border area on both sides of the display area along the vertical first direction Y (along the row direction of the pixel area 21) can be reduced, thereby achieving a narrow border design.

[0056] Based on the above embodiments, optionally, Figure 7 This is a schematic diagram illustrating the positional structure of the scan line and scan signal repair layer, provided as an embodiment of the present invention. Figure 8 for Figure 7 A sectional view along line A-A' Figure 9 Another structural layout of the array substrate provided in this embodiment of the present invention is shown below. Figures 7-9 As shown, the thin film stacked layer 20 also includes a scan signal repair layer 270 stacked on the side of the third metal layer 240 away from the second metal layer 230; the scan signal repair layer 270 is located in the border area and surrounds the display area; each scan line 22 extends to the border area; the vertical projection of the scan signal repair layer 270 on the substrate 10 overlaps with the vertical projection of the portion of the scan line 22 extending to the border area on the substrate 10.

[0057] Specifically, the scan signal repair layer 270 includes a plurality of first laser repair points 271; the vertical projection of each first laser repair point 271 on the substrate 10 coincides with the vertical projection of the portion of a scan line 22 extending to the border area on the substrate 10. Each scan line 22 includes a second laser repair point 221; the vertical projection of the second laser repair point 221 on the substrate 10 coincides with the vertical projection of the first metal layer 210 corresponding to the gate connection of a row of thin-film transistors on the substrate 10.

[0058] Laser repair at the first laser repair point 271 connects the scan signal repair layer 270 to the scan line 22 directly below it. Laser repair at the second laser repair point 221 connects the scan line 22 to the gate connection line of the row of thin-film transistors directly below it. Therefore, when the scan line 22 is open-circuited and the gate connection line of the corresponding row of thin-film transistors cannot receive the scan signal, laser repair can be performed at the two first laser repair points 271 directly above the scan line 22 to repair the connection between the scan signal repair layer 270 and the scan line 22 directly below it. Then, laser repair can be performed at the second laser repair point 221 of the scan line 22 to repair the connection between the scan line 22 and the gate connection line of the row of thin-film transistors directly below it.

[0059] This utility model embodiment also provides an electronic paper, which includes the array substrate provided in any embodiment of this utility model.

[0060] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0061] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. An array substrate, characterized in that, The material includes a substrate and a thin film stack layer stacked on one side of the substrate. The thin film stack layer includes a first metal layer, a first metal insulating layer, a second metal layer, and a third metal layer stacked sequentially on one side of the substrate. The thin film stack layer forms multiple pixel regions arranged in an array and multiple scan lines extending along a first direction, each pixel region including a thin film transistor; the first direction is the column direction of the pixel regions; The gate of the thin-film transistor is located in the first metal layer, and the gates of the thin-film transistors in the same row are connected; the scan line is located in the second metal layer; Each scan line is connected to the gate of a row of thin-film transistors through a transfer via. The transfer via is disposed in the transfer region of the first metal insulating layer. The vertical projection of the transfer region on the substrate coincides with the vertical projection of the overlapping region of the first metal layer, the second metal layer and the third metal layer on the substrate.

2. The array substrate according to claim 1, characterized in that, Each of the pixel regions further includes a pixel electrode; The pixel electrode is located in the third metal layer.

3. The array substrate according to claim 1, characterized in that, Each of the scan lines is disposed on one side of a column of thin-film transistors.

4. The array substrate according to claim 1, characterized in that, The thin film stack layer also forms multiple data lines extending along the first direction; Each of the data lines is disposed on one side of a column of thin-film transistors, and each of the data lines is connected to the first electrode of a column of thin-film transistors; both the data lines and the first electrode of the thin-film transistors are located in the second metal layer.

5. The array substrate according to claim 1, characterized in that, The thin film stack layer further includes a planarization layer disposed between the second metal layer and the third metal layer.

6. The array substrate according to claim 1, characterized in that, The thin film stack layer further includes a transparent conductive layer disposed on the side of the third metal layer away from the second metal layer.

7. The array substrate according to claim 1, characterized in that, It also includes a scanning circuit; the scanning circuit is located in the border area on both sides of the display area along the first direction; the scanning circuit is connected to each of the scanning lines.

8. The array substrate according to claim 7, characterized in that, The thin film stack layer further includes a scan signal repair layer stacked on the side of the third metal layer away from the second metal layer; The scan signal repair layer is located in the border area and surrounds the display area; Each of the scan lines extends into the border area; The vertical projection of the scan signal repair layer on the substrate overlaps with the vertical projection of the portion of the scan line extending to the border area on the substrate.

9. The array substrate according to claim 8, characterized in that, The scan signal repair layer includes multiple first laser repair points; The vertical projection of each of the first laser repair points on the substrate coincides with the vertical projection of the portion of the scan line extending to the border area on the substrate; Each of the scan lines includes a second laser repair point; The vertical projection of the second laser repair point on the substrate coincides with the vertical projection of the first metal layer corresponding to the gate connection of the thin-film transistor on the substrate.

10. An electronic paper, characterized in that, Includes the array substrate as described in any one of claims 1-9.

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