Solar cells and photovoltaic modules

Abstract

A solar cell includes a silicon substrate, a first doped layer, a second doped layer, and a conductive layer. The silicon substrate includes a first surface and a second surface facing each other. A through-hole is formed in the silicon substrate, penetrating both the first and second surfaces. The first doped layer is located on the side of the silicon substrate containing the first surface. The second doped layer is located on the side of the silicon substrate containing the second surface. The second doped layer and the first doped layer have opposite doping types. The conductive layer is located on the wall of the through-hole. The conductive layer contacts and connects the first and second doped layers. A plurality of first metal grid lines are located on the side of the silicon substrate containing the first surface, and the through-hole is located between two adjacent first metal grid lines. A plurality of second metal grid lines are located on the side of the silicon substrate containing the second surface, and the through-hole is located between two adjacent second metal grid lines. This application also provides a photovoltaic module. This solar cell can effectively solve the risks of hot spots and the effects of shading.

Description

Technical Field

[0001] This application relates to the field of photovoltaic material manufacturing and processing, and more specifically, to a solar cell and a photovoltaic module. Background Technology

[0002] In back-contact solar cells, such as heterojunction back-contact (HBC) cells, both the P-region and N-region metal electrodes are located on the back side of the cell, with no metal electrodes on the front side. This results in numerous contact interfaces between the P-region and N-region metal electrodes. Existing technologies typically prevent leakage breakdown under high negative voltage conditions by creating uniform and dense PN leakage contact channels on the back side, thereby reducing the risk of hot spots and mitigating the impact of shading, effectively solving the high-temperature problem of the cell when hot spots occur. However, in mainstream front-back contact solar cells, such as passivated emitter and rear cell (PERC), tunnel oxide passivated contact (TOPCon) cells, and heterojunction (HJT) solar cells, the P-region and N-region metal electrodes are located on the front and back sides of the cell, respectively. The PN leakage contact channels are only located at the edges of the silicon wafer, making it impossible to create an effective and sufficient number of PN leakage contact channels. Therefore, there is a serious risk of hot spots and the impact of shading. Utility Model Content

[0003] Therefore, embodiments of this application provide a solar cell that can effectively solve the risks of hot spots and the effects of shading.

[0004] A solar cell, comprising: A silicon substrate includes opposing first and second surfaces, wherein the silicon substrate has through holes penetrating the first and second surfaces; The first doped layer is located on the side of the first surface of the silicon substrate; The second doped layer is located on the side of the second surface of the silicon substrate, and the doping types of the first doped layer and the second doped layer are opposite. A conductive layer is located on the wall of the through hole, and the conductive layer contacts and connects the first doped layer and the second doped layer; A first transparent conductive film is located on the side of the first doped layer away from the silicon substrate; The second transparent conductive film is located on the side of the second doped layer away from the silicon substrate; A plurality of first metal gate lines are located on the side of the silicon substrate containing the first surface, and the through-hole is located between two adjacent first metal gate lines; and Multiple second metal gate lines are located on the side of the second surface of the silicon substrate, and the through-hole is located between two adjacent second metal gate lines.

[0005] The solar cell in this application embodiment is an HJT solar cell. By opening a through hole at a specific location on the silicon substrate, and setting a conductive layer on the hole wall to connect the first doped layer and the second doped layer on both sides of the silicon substrate, a reverse leakage channel is formed, which improves the reverse conduction capability of the cell and can greatly reduce the reverse voltage of the solar cell, thereby improving the hot spot risk and the impact of shading in the actual operation of the photovoltaic module.

[0006] In some embodiments, the conductive layer is a transparent conductive layer and is made of the same material as the first transparent conductive film or the second transparent conductive film.

[0007] In some embodiments, the materials of the first doped layer and the second doped layer are each one of doped amorphous silicon, doped nanocrystalline silicon, doped silicon oxide, high work function material, or low work function material.

[0008] In some embodiments, the conductive layer is in direct contact with the wall of the through hole.

[0009] In some embodiments, at least one of the following is further disposed between the conductive layer and the hole wall of the through hole: a silicon oxide layer, an intrinsic amorphous silicon layer, a phosphorus-doped amorphous silicon layer, a boron-doped amorphous silicon layer, a doped nanocrystalline silicon layer, a doped silicon oxide layer, a high work function material layer, or a low work function material layer.

[0010] In some embodiments, a first passivation layer is disposed between the silicon substrate and the first doped layer, and a second passivation layer is disposed between the silicon substrate and the second doped layer.

[0011] In some embodiments, the materials of the first passivation layer and the second passivation layer are silicon oxide or intrinsic amorphous silicon, respectively.

[0012] In some embodiments, a first passivation layer, a first doped layer, a second passivation layer, and a second doped layer are sequentially disposed between the conductive layer and the wall of the through hole, wherein the first passivation layer is in direct contact with the wall of the through hole.

[0013] In some embodiments, a second passivation layer, a second doped layer, a first passivation layer, and a first doped layer are sequentially disposed between the conductive layer and the wall of the through hole, wherein the second passivation layer is in direct contact with the wall of the through hole.

[0014] In some embodiments, the conductive layer is a doped silicon layer with the same doping type as the first doped layer or the second doped layer.

[0015] In some embodiments, the diameter of the through hole is 50 μm to 2000 μm.

[0016] In some embodiments, the ratio of the total opening area of ​​all through holes on the first surface to the area of ​​the first surface is less than 2%.

[0017] This application also provides a photovoltaic module, including the solar cell described above and a solder strip connecting the solar cell. The solder strip includes a first solder strip and a second solder strip, wherein the first solder strip is located on the side of the first surface of the silicon substrate and is electrically connected to the first metal grid line, and the second solder strip is located on the side of the second surface of the silicon substrate and is electrically connected to the second metal grid line. Along the thickness direction of the silicon substrate, the position of the through hole is directly opposite the first solder strip and the second solder strip.

[0018] In some embodiments, insulating adhesive is provided at the opening position of the through hole on the side where the first surface is located, or insulating adhesive is provided at the opening position of the through hole on the side where the second surface is located, so that the first solder strip and the second solder strip are electrically insulated by the insulating adhesive. Attached Figure Description

[0019] Figure 1 This is a cross-sectional schematic diagram of a solar cell according to an embodiment of this application.

[0020] Figure 2 This is a top view schematic diagram of a solar cell according to an embodiment of this application.

[0021] Figure 3 This is a top view schematic diagram of a photovoltaic module according to an embodiment of this application.

[0022] Figure 4 This is a cross-sectional schematic diagram of a photovoltaic module according to an embodiment of this application.

[0023] Explanation of key component symbols: Substrate 10, first doped layer 20, second doped layer 30, conductive layer 40, first surface 101, second surface 102. Through-hole 103, first passivation layer 51, second passivation layer 52, first metal gate line 61, second metal gate line 62. Insulating adhesive 80, first direction D1, second direction D2, first solder strip 71, second solder strip 72. First transparent conductive film 91, second transparent conductive film 92. Detailed Implementation

[0024] The embodiments of this application are described below with reference to the accompanying drawings. Unless otherwise specified, the data range values ​​described in this application shall include the end values.

[0025] The terminology used in the implementation section of this application is only for explaining specific embodiments of this application and is not intended to limit this application. The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0026] This application provides an HJT solar cell, which improves the reverse conduction capability of the cell by introducing a reverse leakage channel in the cell, thereby greatly reducing the reverse voltage of the cell and improving the hot spot risk of the photovoltaic module in actual operation.

[0027] Please see Figure 1 The solar cell of this application embodiment includes a silicon substrate 10 and a first doped layer 20, a second doped layer 30, and a conductive layer 40 disposed on the silicon substrate 10. The silicon substrate 10 includes a first surface 101 and a second surface 102 opposite to each other. The first surface 101 and the second surface 102 are the front and back surfaces of the silicon substrate 10, respectively. The first doped layer 20 is located on the side where the first surface 101 of the silicon substrate 10 is located, and the second doped layer 30 is located on the side where the second surface 102 of the silicon substrate 10 is located, and the doping types of the first doped layer 20 and the second doped layer 30 are opposite. (See also...) Figure 3 A plurality of through holes 103 are spaced apart on the silicon substrate 10. Each through hole 103 penetrates the first surface 101 and the second surface 102. A conductive layer 40 is disposed on the hole wall of the through hole 103. The conductive layer 40 contacts and connects the first doped layer 20 and the second doped layer 30. In this way, electrical contact is achieved between the front and back sides of the solar cell. In this embodiment, the solar cell is an HJT solar cell.

[0028] In some embodiments, a first transparent conductive film 91 is disposed on the side of the first doped layer 20 away from the silicon substrate 10, and a second transparent conductive film 92 is disposed on the side of the second doped layer 30 away from the silicon substrate 10. The first transparent conductive film 91 and the second transparent conductive film 92 are selected from one of indium tin oxide (ITO) layer, tin oxide (SnO) layer, and aluminum-doped zinc oxide (AZO) layer.

[0029] In some embodiments, the conductive layer 40 is a transparent conductive layer, for example, selected from one of an indium tin oxide (ITO) layer, a tin oxide (SnO) layer, and an aluminum-doped zinc oxide (AZO) layer.

[0030] The materials of the first doped layer 20 and the second doped layer 30 are each selected from doped amorphous silicon, doped nanocrystalline silicon, doped silicon oxide, high work function materials, or low work function materials. If the first doped layer 20 is a p-type doped layer, then the second doped layer 30 can be an n-type doped layer. If the first doped layer 20 is an n-type doped layer, then the second doped layer 30 can be a p-type doped layer. In some embodiments, the conductive layer 40 is a doped crystalline silicon layer with the same doping type as the first doped layer 20 or the second doped layer 30. If the first doped layer 20 is a high work function material, then the second doped layer 30 is a low work function material. If the first doped layer 20 is a low work function material, then the second doped layer 30 is a high work function material. A high work function material can be, for example, MoO. x Low work function materials could be, for example, LiF. x wait.

[0031] It should be noted that high work function materials and low work function materials achieve p-type and n-type contacts through band structure without doping. High work function materials refer to materials with relatively large work function values, requiring higher energy for electrons to escape from their surface. Low work function materials refer to materials with relatively small work function values, requiring lower energy for electrons to escape from their surface. In silicon-based heterojunction solar cells, high work function materials are used to match the valence band of silicon to collect holes, forming p-type contacts; while low work function materials are used to match the conduction band of silicon to collect electrons, forming n-type contacts.

[0032] Typically, the conduction band bottom (Ec) of crystalline silicon is approximately 4.05 eV relative to the vacuum level. Broadband materials with a work function lower than Ec or a small conduction band level in contact with silicon can serve as electron-selective contacts. Furthermore, the valence band top (Ev) of crystalline silicon is approximately 5.17 eV relative to the vacuum level. Materials with a work function higher than Ev or a small valence band level in contact with silicon can serve as hole-selective contacts.

[0033] In the embodiments of this application, a low work function material refers to a material whose work function value is less than the conduction band bottom of crystalline silicon. In some embodiments, the work function value of the low work function material is less than 4.05 eV, such as less than 4.0 eV, but is not limited thereto.

[0034] In the embodiments of this application, a high work function material refers to a material with a work function value less than the valence band top of crystalline silicon. In some embodiments, a high work function material refers to a material with a work function value greater than 5.17 eV, but is not limited thereto.

[0035] In some embodiments, a first passivation layer 51 is disposed between the silicon substrate 10 and the first doped layer 20, and an interface second passivation layer 52 is disposed between the silicon substrate 10 and the second doped layer 30. The materials of the first passivation layer 51 and the second passivation layer 52 are silicon oxide or intrinsic amorphous silicon.

[0036] In some embodiments, at least one of an intrinsic amorphous silicon layer, a phosphorus-doped amorphous silicon layer, a boron-doped amorphous silicon layer, a high work function material layer, or a low work function material layer is further disposed between the conductive layer 40 and the hole wall of the through hole 103.

[0037] The through hole 103 can be created using methods such as mechanical drilling, laser drilling, photolithographic grinding, or printing and grinding. For example... Figure 2 As shown, the through holes 103 are arranged in a matrix on the silicon substrate 10, but this is not a limitation.

[0038] In some embodiments, the through hole 103 is a circular hole, and the diameter of the through hole 103 can be 50μm to 2000μm, for example 50μm, 100μm, 100μm, 200μm, 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, 1000μm, 1100μm, 1200μm, 1300μm, 1400μm, 1500μm, 1600μm, 1700μm, 1800μm, 1900μm, or 2000μm.

[0039] In some embodiments, the ratio of the total opening area of ​​all through holes 103 to the area of ​​the first surface 101 is less than 2%, for example, 0.5%, 0.7%, 1%, 1.2%, 1.5%, 1.8% or 1.9%, in order to reduce the area occupied by the through holes 103.

[0040] Combination Figure 2 and Figure 3 As shown, the solar cell also includes a plurality of first metal grid lines 61 and a plurality of second metal grid lines 62. The first metal grid lines 61 are located on the side where the first surface 101 of the silicon substrate 10 is located, specifically on the side of the first transparent conductive film 91 facing away from the silicon substrate 10. The second metal grid lines 62 are located on the side where the second surface 102 of the silicon substrate 10 is located, specifically on the side of the first transparent conductive film 91 facing away from the silicon substrate 10. The first metal grid lines 61 and the second metal grid lines 62 are used to collect the current generated by the cell after being exposed to light. In this embodiment, each first metal grid line 61 extends into a strip along a first direction D1, and the plurality of first metal grid lines 61 are arranged at intervals along a second direction D2, the second direction D2 intersecting the first direction D1.

[0041] In this embodiment, the second direction D2 is perpendicular to the first direction D1. Each second metal gate line 62 extends into a strip shape along the first direction D1, and multiple second metal gate lines 62 are arranged at intervals along the second direction D2. Figure 2 As shown, the through hole 103 is located between two adjacent first metal grid lines 61, as... Figure 3As shown, the through hole 103 is located between two adjacent second metal grid lines 62 to avoid occupying the space of the first metal grid line 61 and the second metal grid line 62.

[0042] This application also includes a photovoltaic module, comprising multiple solar cells as described above, and solder ribbons connecting adjacent solar cells. Solder ribbons (also called interconnects or busbars) play a crucial role in photovoltaic modules, connecting multiple cells to form a complete circuit and efficiently discharging current. While the current generated by the solar cells themselves is direct current, the output voltage of a single solar cell is very low (approximately 0.5-0.6V). Solder ribbons securely connect the front (usually the negative electrode) and back (usually the positive electrode) of adjacent cells by welding. Through this series connection, the voltages of dozens or even hundreds of cells are superimposed to achieve the required output voltage of the module (e.g., 30V, 60V, etc.). The solder ribbons constitute the "wires" between the solar cells, allowing current to flow smoothly throughout the entire photovoltaic module.

[0043] See also Figure 3 and Figure 4 The solder strips include multiple first solder strips 71 and multiple second solder strips 72. Taking a solar cell of a photovoltaic module as an example, the first solder strips 71 are located on the side of the first surface 101 of the silicon substrate 10 and are electrically connected to the first metal grid line 61 to collect the current of the first metal grid line 61. The second solder strips 72 are located on the side of the second surface 102 of the silicon substrate 10 and are electrically connected to the second metal grid line 62 to collect the current of the second metal grid line 62. In the embodiments of this application, each first solder strip 71 extends into a strip shape along the second direction D2, and multiple first solder strips 71 are arranged at intervals along the first direction D1. Each second solder strip 72 extends into a strip shape along the second direction D2, and multiple second solder strips 72 are arranged at intervals along the first direction D1.

[0044] In addition, such as Figure 4 As shown, along the thickness direction of the silicon substrate 10, the through-hole 103 is positioned directly opposite the first solder strip 71 and the second solder strip 72. The first solder strip 71 covers the opening of the through-hole 103 on the first surface 101 side, and the second solder strip 72 covers the opening of the through-hole 103 on the second surface 102 side. Thus, with the through-hole 103 directly opposite the first solder strip 71 and the second solder strip 72, it does not require additional space in the light-receiving area of ​​the solar cell, and therefore does not affect the light conversion efficiency.

[0045] like Figure 4As shown, to prevent electrical conductivity between the first solder strip 71 and the second solder strip 72, an insulating adhesive 80 is provided at the opening position of the through hole 103 on the first surface 101 side or the second surface 102 side. The insulating adhesive 80 provides electrical insulation between the first solder strip 71 and the second solder strip 72. In this embodiment, the insulating adhesive 80 is provided at the opening position of the through hole 103 on the second surface 102 side, and connects the conductive layer 40, the second doped layer 30, and the second solder strip 72 on the hole wall of the through hole 103. It can be understood that when the insulating adhesive 80 is provided at the opening position of the through hole 103 on the first surface 101 side, the insulating adhesive 80 connects the conductive layer 40, the first doped layer 20, and the first solder strip 71 on the hole wall of the through hole 103.

[0046] Taking a heterojunction solar cell as an example, the silicon substrate 10 is an N-type silicon substrate (e.g., a phosphorus-doped silicon substrate). A first passivation layer 51 (e.g., an intrinsic amorphous silicon layer), a first doped layer 20 (e.g., an N-type doped, phosphorus-doped amorphous silicon layer), and a first transparent conductive film 91 are sequentially formed on the first surface 101 of the silicon substrate 10. A second passivation layer 52 (e.g., an intrinsic amorphous silicon layer), a second doped layer 30 (P-type doped, e.g., a boron-doped amorphous silicon layer), and a second transparent conductive film 92 are sequentially formed on the second surface 102 of the silicon substrate 10. The first passivation layer 51 and the second passivation layer 52 serve a passivation function, reducing surface recombination. One of the first doped layer 20 and the second doped layer 30 is used to form a PN junction, and the other is used to collect electrons. The first transparent conductive film 91 and the second transparent conductive film 92 serve to conduct electricity and transmit light. Furthermore, a plurality of first metal grid lines 61 are formed on the first transparent conductive film 91, and a plurality of second metal grid lines 62 are formed on the second transparent conductive film 92. Along the thickness direction of the silicon substrate 10, the through hole 103 not only penetrates the silicon substrate 10, but also penetrates each layer on both sides of the silicon substrate 10, such as penetrating the first passivation layer 51, the first doped layer 20, the first transparent conductive film 91, and penetrating the second passivation layer 52, the second doped layer 30, and the second transparent conductive film 92.

[0047] In some embodiments, the solar cell may be without a main grid, that is, no metal main grid is provided on the side where the first surface 101 and the second surface 102 are located, only the first metal grid line 61 is provided on the side where the first surface 101 is located, and only the second metal grid line 62 is provided on the side where the second surface 102 is located.

[0048] The through-hole 103 is located between two adjacent first metal grid lines 61 and between two adjacent second metal grid lines 62 to avoid occupying the space of the first metal grid lines 61 and the second metal grid lines 62. Along the thickness direction of the silicon substrate 10, the position of the through-hole 103 is directly opposite the first solder strip 71 and the second solder strip 72. The through-hole 103 does not need to occupy the light-receiving area of ​​the solar cell and therefore will not affect the light energy conversion efficiency.

[0049] The fabrication method of heterojunction solar cells will be described below.

[0050] Step S1: Provide a silicon substrate and clean and texturize the silicon substrate.

[0051] Texturing is a process that creates an uneven, textured surface on a silicon substrate. Its purpose is to remove organic dirt and impurities from the surface of the silicon substrate and to increase the absorption of sunlight by the silicon substrate by utilizing the light-trapping effect, thereby reducing reflectivity.

[0052] Step S2: Form a first passivation layer and a first doped layer (phosphorus-doped amorphous silicon layer) on the side where the first surface of the silicon substrate is located.

[0053] This step S2 can be performed using plasma-enhanced chemical vapor deposition (PECVD) technology.

[0054] Step S3: Form a second passivation layer and a second doped layer (boron-doped amorphous silicon layer) on one side of the second surface of the silicon substrate.

[0055] Step S3 can be performed using PECVD technology.

[0056] Step S4: Deposit transparent conductive films on both the first and second surfaces of the silicon substrate.

[0057] Step S5: Form a first metal gate line on the side where the first surface of the silicon substrate is located, and form a second metal gate line on the side where the second surface is located.

[0058] Understandably, there are multiple opportunities to create the through-hole 103. In some embodiments, the through-hole 103 is created on the silicon substrate 10 before the cleaning and texturing process in step S1, and the method of creating the hole can be laser drilling. In some embodiments, the through-hole 103 is created on the silicon substrate 10 after the deposition and formation of the first passivation layer 51, the first doped layer 20, the second passivation layer 52, and the second doped layer 30, and the method of creating the hole can be laser drilling. In some embodiments, after step S5, when the positive solar cell is sliced ​​into half-wafers, laser drilling is performed on the silicon substrate 10 to create the through-hole 103.

[0059] In the process of manufacturing photovoltaic modules, insulating adhesive 80 is printed on the opening on the side of the second surface 102 of the through hole 103, and then the first solder strip 71 is welded on the side of the first surface 101, and the second solder strip 72 is welded on the side of the second surface 102.

[0060] Depending on when the through hole 103 is opened, there are various types and timings of the film layer formed on the hole wall of the through hole 103.

[0061] In one embodiment, before cleaning and texturing the silicon substrate 10, a through hole 103 is formed in the silicon substrate 10. The method for preparing the solar cell specifically includes the following steps S11 to S16.

[0062] Step S11: Laser drilling is performed on the silicon substrate 10 to form a through hole 103.

[0063] Step S12: Clean and texturize the silicon substrate 10 after drilling. The texturizing process can etch away the laser damage formed on the silicon substrate 10 when the laser opens the through hole 103.

[0064] Step S13: Deposit a first passivation layer 51 and a first doped layer 20 (e.g., a phosphorus-doped amorphous silicon layer) on the side of the silicon substrate 10 where the first surface 101 is located. This step S13 can be performed using PECVD technology.

[0065] Step S14: A second passivation layer 52 and a second doped layer 30 (e.g., a boron-doped amorphous silicon layer) are formed on one side of the second surface 102 of the silicon substrate 10. This step S14 can be performed using PECVD technology. The order in which steps S13 and S14 are performed is not required.

[0066] Therefore, after completing steps S13 and S14, a corresponding film layer will also be attached to the wall of the through hole 103, such as the first passivation layer 51, the first doped layer 20, the second passivation layer 52, and the second doped layer 30 attached in sequence, or the second passivation layer 52, the second doped layer 30, the first passivation layer 51, and the first doped layer 20 attached in sequence.

[0067] Step S15: A transparent conductive film is deposited on both the first surface 101 and the second surface 102 of the silicon substrate 10. After step S15, a transparent conductive film, i.e., a transparent conductive layer 40, is also attached to the wall of the through hole 103.

[0068] Step S16: A first metal gate line 61 is formed on the side of the first surface 101 of the silicon substrate 10, and a second metal gate line 62 is formed on the side of the second surface 102.

[0069] In this case, the conductive layer 40 on the wall of the through hole 103 is a transparent conductive film formed concurrently during the deposition of the transparent conductive film in step S15. Additionally, a first passivation layer 51, a first doped layer 20, a second passivation layer 52, and a second doped layer 30 are sequentially formed between the conductive layer 40 and the hole wall of the silicon substrate 10, with the first passivation layer 51 in direct contact with the hole wall of the silicon substrate 10; or, a second passivation layer 52, a second doped layer 30, a first passivation layer 51, and a first doped layer 20 are sequentially formed between the conductive layer 40 and the hole wall of the silicon substrate 10, with the second passivation layer 52 in direct contact with the hole wall of the silicon substrate 10.

[0070] In another embodiment, the method for preparing a solar cell specifically includes the following steps S21 to S26.

[0071] Step S21: Clean and texturize the silicon substrate 10.

[0072] Step S22: Deposit a first passivation layer 51 and a first doped layer 20 (e.g., a phosphorus-doped amorphous silicon layer) on the side of the silicon substrate 10 where the first surface 101 is located. This step S22 can be performed using PECVD technology.

[0073] Step S23: A second passivation layer 52 and a second doped layer 30 (e.g., a boron-doped amorphous silicon layer) are formed on one side of the second surface 102 of the silicon substrate 10. This step S23 can be performed using PECVD technology. The order in which steps S22 and S23 are performed is not required.

[0074] Step S24: Laser drilling is performed on the silicon substrate 10 to form a through hole 103.

[0075] Step S25: A transparent conductive film is deposited on both the first surface 101 and the second surface 102 of the silicon substrate 10. After step S25, a transparent conductive film, i.e., a transparent conductive layer 40, is also attached to the wall of the through hole 103.

[0076] Step S26: A first metal gate line 61 is formed on the side of the first surface 101 of the silicon substrate 10, and a second metal gate line 62 is formed on the side of the second surface 102.

[0077] In this case, the conductive layer 40 on the hole wall of the through hole 103 is a transparent conductive film formed together with the transparent conductive film during step S25. In addition, the conductive layer 40 is directly attached to the hole wall of the silicon substrate 10, that is, the conductive layer 40 is in direct contact with the hole wall of the silicon substrate 10.

[0078] In some embodiments, after the solar cell is fabricated, laser drilling is performed simultaneously on the solar cell to form through-holes 103 while laser-cutting the entire solar cell into half-cells. In this case, during the laser drilling process to form the through-hole 103, the laser needs to pass through the silicon substrate 10 and the first transparent conductive film 91, the first doped layer 20, the first passivation layer 51, the second transparent conductive film 92, the second doped layer 30, and the second passivation layer 52 attached to the silicon substrate 10. When laser drilling forms the through-hole 103, if the drilling starts from the first surface 101 side, the laser will dope the doping elements on the first surface 101 side onto the hole wall. Therefore, the conductive layer 40 formed on the hole wall of the through-hole 103 is a doped crystalline silicon layer with the same doping type as the first doped layer 20. When laser drilling forms a through hole 103, the drilling starts from the side of the second surface 102. Due to the effect of the laser, the doping elements on the side of the second surface 102 will be doped onto the hole wall of the through hole. The conductive layer 40 formed on the hole wall of the through hole 103 is a doped silicon layer with the same doping type as the second doped layer 30.

[0079] The solar cell of this application forms a reverse leakage channel by forming a through hole 103 at a specific position on the silicon substrate 10. A conductive layer 40 is disposed on the hole wall of the through hole 103 to electrically connect the first doped layer 20 and the second doped layer 30 on both sides of the silicon substrate 10. This enhances the reverse conduction capability of the cell and can greatly reduce the reverse voltage of the solar cell, thereby improving the hot spot risk of the photovoltaic module in actual operation.

[0080] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A solar cell, characterized in that, include: A silicon substrate includes opposing first and second surfaces, wherein the silicon substrate has through holes penetrating the first and second surfaces; The first doped layer is located on the side of the first surface of the silicon substrate; The second doped layer is located on the side of the second surface of the silicon substrate, and the doping types of the first doped layer and the second doped layer are opposite. A conductive layer is located on the wall of the through hole, and the conductive layer contacts and connects the first doped layer and the second doped layer; A first transparent conductive film is located on the side of the first doped layer away from the silicon substrate; The second transparent conductive film is located on the side of the second doped layer away from the silicon substrate; A plurality of first metal gate lines are located on the side of the silicon substrate containing the first surface, and the through-hole is located between two adjacent first metal gate lines; and Multiple second metal gate lines are located on the side of the second surface of the silicon substrate, and the through-hole is located between two adjacent second metal gate lines.

2. The solar cell according to claim 1, characterized in that, The conductive layer is a transparent conductive layer and is made of the same material as the first transparent conductive film or the second transparent conductive film.

3. The solar cell according to claim 1 or 2, characterized in that, The conductive layer is in direct contact with the wall of the through hole.

4. The solar cell according to claim 1, characterized in that, Between the conductive layer and the hole wall of the through hole, at least one of the following is provided: silicon oxide layer, intrinsic amorphous silicon layer, phosphorus-doped amorphous silicon layer, boron-doped amorphous silicon layer, doped nanocrystalline silicon layer, doped silicon oxide layer, high work function material layer, or low work function material layer.

5. The solar cell according to claim 1, characterized in that, A first passivation layer is disposed between the silicon substrate and the first doped layer, and a second passivation layer is disposed between the silicon substrate and the second doped layer; The conductive layer and the wall of the through hole are further provided with a first passivation layer, a first doped layer, a second passivation layer and a second doped layer in sequence, and the first passivation layer is in direct contact with the wall of the through hole; Alternatively, a second passivation layer, a second doped layer, a first passivation layer, and a first doped layer may be sequentially disposed between the conductive layer and the wall of the through hole, with the second passivation layer in direct contact with the wall of the through hole.

6. The solar cell according to claim 1, 4, or 5, characterized in that, The conductive layer is a doped silicon layer with the same doping type as the first doped layer or the second doped layer.

7. The solar cell according to claim 1, characterized in that, The diameter of the through hole is 50μm~2000μm.

8. The solar cell according to claim 1 or 7, characterized in that, The ratio of the total opening area of ​​all the through holes on the first surface to the area of ​​the first surface is less than 2%.

9. A photovoltaic module, characterized in that, The invention includes a solar cell according to any one of claims 1 to 8 and a solder strip connecting the solar cell, the solder strip comprising a first solder strip and a second solder strip, wherein the first solder strip is located on the side of the first surface of the silicon substrate and is electrically connected to the first metal grid line, the second solder strip is located on the side of the second surface of the silicon substrate and is electrically connected to the second metal grid line, and the through hole is positioned opposite the first solder strip and the second solder strip along the thickness direction of the silicon substrate.

10. The photovoltaic module according to claim 9, characterized in that, Insulating adhesive is provided at the opening position of the through hole on the side where the first surface is located, or at the opening position of the through hole on the side where the second surface is located, so that the first welding strip and the second welding strip are electrically insulated by the insulating adhesive.

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