Display panel and display device

Abstract

This disclosure provides a display panel and display device, relating to the field of display technology, for improving the display effect of the display panel. The display panel includes a substrate, a driving layer, and a light-emitting device layer, which are sequentially stacked along a first direction. The driving layer includes a first conductive layer and a second conductive layer. The first conductive layer includes data signal lines. The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes a conductive pattern. The light-emitting device layer includes a first electrode layer and a pixel definition layer. The first electrode layer includes a first electrode. The pixel definition layer is located on the side of the first electrode layer away from the substrate. The pixel definition layer includes a first pixel opening, a second pixel opening, and a third pixel opening. At least one of the first pixel opening, the second pixel opening, and the third pixel opening, when projected onto the substrate, is located within the boundary range of the projected projection of the conductive pattern onto the substrate. The above-described display panel is used to display images.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the continuous development of display technology, display devices have gradually become ubiquitous in people's lives. Among them, organic light-emitting diode (OLED) display panels are widely used in display devices such as mobile phones, televisions, and laptops due to their advantages such as self-illumination, low power consumption, wide viewing angle, fast response speed, and high contrast. Utility Model Content

[0003] The purpose of the embodiments of this disclosure is to provide a display panel and a display device for improving the display effect of the display panel.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, a display panel is provided. The display panel includes a substrate, a driving layer, and a light-emitting device layer. The substrate, the driving layer, and the light-emitting device layer are stacked sequentially along a first direction, which is the thickness direction of the substrate.

[0006] The driving layer includes a first conductive layer and a second conductive layer. The first conductive layer includes data signal lines. The data signal lines extend along a second direction, which is perpendicular to the first direction. The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes conductive patterns.

[0007] The light-emitting device layer includes multiple light-emitting devices, each including a first electrode. The multiple light-emitting devices include a first-color light-emitting device, a second-color light-emitting device, and a third-color light-emitting device. The light-emitting device layer also includes a first electrode layer and a pixel definition layer. The first electrode layer is formed by the first electrodes within the light-emitting devices. The pixel definition layer is located on the side of the first electrode layer away from the substrate. The pixel definition layer includes a first pixel opening, a second pixel opening, and a third pixel opening.

[0008] The orthographic projection of at least one of the first pixel opening, the second pixel opening, and the third pixel opening onto the substrate is located within the boundary range of the orthographic projection of the conductive pattern onto the substrate.

[0009] In the aforementioned display panel, the orthographic projection of at least one of the first pixel opening, the second pixel opening, and the third pixel opening within the pixel definition layer onto the substrate lies within the boundary range of the orthographic projection of the conductive pattern onto the substrate. Since the orthographic projection of the first pixel opening onto the substrate at least partially overlaps with the orthographic projection of the first electrode within the first color light-emitting device onto the substrate, when the orthographic projection of the first pixel opening onto the substrate lies within the boundary range of the orthographic projection of the conductive pattern onto the substrate, the portion of the first electrode overlapping with the first pixel opening (i.e., the actual effective area of ​​the first electrode within the first color light-emitting device) in the orthographic projection onto the substrate lies within the boundary range of the orthographic projection of the conductive pattern onto the substrate. This allows the conductive pattern to support the actual effective area of ​​the first electrode within the first color light-emitting device and provide comprehensive support, which helps improve the flatness of the actual effective area of ​​the first electrode within the first color light-emitting device, thereby improving the luminous uniformity of the first color light-emitting device and ultimately enhancing the display effect of the display panel.

[0010] Since the orthographic projection of the second pixel opening onto the substrate and the orthographic projection of the first electrode in the second color light-emitting device onto the substrate at least partially overlap, when the orthographic projection of the second pixel opening onto the substrate is within the boundary range of the orthographic projection of the conductive pattern onto the substrate, the portion of the first electrode that overlaps with the second pixel opening (i.e., the actual effective area of ​​the first electrode in the second color light-emitting device) in the orthographic projection onto the substrate is within the boundary range of the orthographic projection of the conductive pattern onto the substrate. This allows the conductive pattern to support the actual effective area of ​​the first electrode in the second color light-emitting device and provide full support for it. This is beneficial to improving the flatness of the actual effective area of ​​the first electrode in the second color light-emitting device, thereby improving the luminous uniformity of the second color light-emitting device and thus improving the display effect of the display panel.

[0011] Since the orthographic projection of the third pixel opening onto the substrate and the orthographic projection of the first electrode in the third color light-emitting device onto the substrate at least partially overlap, when the orthographic projection of the third pixel opening onto the substrate is within the boundary range of the orthographic projection of the conductive pattern onto the substrate, the portion of the first electrode that overlaps with the third pixel opening in the orthographic projection onto the substrate (i.e., the actual effective area of ​​the first electrode in the third color light-emitting device) is within the boundary range of the orthographic projection of the conductive pattern onto the substrate. This allows the conductive pattern to support the actual effective area of ​​the first electrode in the third color light-emitting device and provide full support for it. This is beneficial to improving the flatness of the actual effective area of ​​the first electrode in the third color light-emitting device, thereby improving the luminous uniformity of the third color light-emitting device and thus improving the display effect of the display panel.

[0012] In some embodiments, the conductive pattern includes a first conductive pattern. The orthographic projection of the first pixel opening onto the substrate is located within the boundary of the orthographic projection of the first conductive pattern onto the substrate.

[0013] In some embodiments, the second conductive layer further includes a first voltage signal line. The first voltage signal line extends along a third direction, which is perpendicular to the first direction and intersects with the second direction. A first conductive pattern is connected to the first voltage signal line.

[0014] In some embodiments, the second conductive layer includes a plurality of first conductive patterns. A first voltage signal line is connected to the plurality of first conductive patterns, and the plurality of first conductive patterns connected to the same first voltage signal line are located on the same side of the first voltage signal line along a second direction.

[0015] In some embodiments, the conductive pattern includes a second conductive pattern. The orthogonal projection of the second pixel opening onto the substrate lies within the boundary range of the orthogonal projection of the second conductive pattern onto the substrate. And / or, the orthogonal projection of the third pixel opening onto the substrate lies within the boundary range of the orthogonal projection of the second conductive pattern onto the substrate.

[0016] In some embodiments, the second conductive layer further includes a first voltage signal line. The first voltage signal line extends along a third direction, which is perpendicular to the first direction and intersects with the second direction. The second conductive pattern is connected to the first voltage signal line.

[0017] In some embodiments, the second conductive layer includes a plurality of second conductive patterns. A first voltage signal line is connected to the plurality of second conductive patterns, and the plurality of second conductive patterns connected to the same first voltage signal line are located on the same side of the first voltage signal line along a second direction.

[0018] In some embodiments, the conductive pattern further includes a first conductive pattern. The orthographic projection of the first pixel opening onto the substrate is located within the boundary range of the orthographic projection of the first conductive pattern onto the substrate. The first conductive pattern is connected to a first voltage signal line. The first conductive pattern and the second conductive pattern, connected to the same first voltage signal line, are located on opposite sides of the first voltage signal line along a second direction.

[0019] In some embodiments, the second conductive layer includes a plurality of first conductive patterns and a plurality of second conductive patterns. The plurality of first conductive patterns are spaced apart along a third direction. The plurality of second conductive patterns are spaced apart along a third direction. Along a second direction, a first conductive pattern corresponds to a gap region between two adjacent second conductive patterns, and a second conductive pattern corresponds to a gap region between two adjacent first conductive patterns.

[0020] In some embodiments, the distance between the boundary of the orthographic projection of at least one of the first pixel opening, the second pixel opening, and the third pixel opening onto the substrate, and the boundary of the orthographic projection of the conductive pattern onto the substrate is less than or equal to 9 μm.

[0021] In some embodiments, the driving layer further includes a first insulating layer located between the first conductive layer and the second conductive layer. The dimension of the first insulating layer along the first direction is greater than or equal to 2 μm.

[0022] In some embodiments, the first conductive layer further includes a third conductive pattern. The orthographic projection of the first pixel opening onto the substrate lies within the boundary range of the orthographic projection of the third conductive pattern onto the substrate.

[0023] In some embodiments, the first conductive layer further includes a second voltage signal line extending along a second direction. A third conductive pattern is located on one side of the second voltage signal line along the third direction and is connected to the second voltage signal line to form an integral structure. The third direction is perpendicular to the first direction and intersects the second direction.

[0024] In some embodiments, the first conductive layer includes a plurality of second voltage signal lines, which are spaced apart along a third direction. A third conductive pattern is located between two adjacent second voltage signal lines and is connected to each of the two second voltage signal lines to form an integral structure.

[0025] In some embodiments, the first conductive layer further includes a first fan-out line and a second voltage signal line. The first fan-out line extends along a second direction. The orthographic projection of the first fan-out line onto the substrate and the orthographic projection of the first pixel opening onto the substrate at least partially overlap. The second voltage signal line extends along the second direction. The first fan-out line is located on one side of the second voltage signal line along a third direction, which is perpendicular to the first direction and intersects the second direction. The orthographic projection of the first pixel opening onto the substrate and the orthographic projection of the second voltage signal line onto the substrate at least partially overlap.

[0026] In some embodiments, the second voltage signal line includes a main body and a first extension. The main body extends along a second direction. The first extension is connected to the main body. Along a third direction, the first extension is located between the main body and the first fan-out line.

[0027] The first extension includes a first sub-part extending along a second direction. Alternatively, the first extension includes multiple first sub-parts extending along the second direction, and the multiple first sub-parts are spaced apart along a third direction and connected sequentially.

[0028] The orthographic projection of the first pixel opening onto the substrate overlaps with the orthographic projection of the first sub-part onto the substrate.

[0029] In some embodiments, the dimension of the first fan-out line along a third direction is equal to the dimension of the first sub-section along a third direction. And / or, when the first extension includes a plurality of first sub-sections, the spacing between the first fan-out line and the first extension along a third direction is equal to the spacing between two adjacent first sub-sections along a third direction.

[0030] In some embodiments, the dimension of the first fan-out line along a third direction is greater than or equal to 1.9 μm and less than or equal to 2.8 μm. And / or, the dimension of the first extension along a third direction is greater than or equal to 1.9 μm and less than or equal to 2.8 μm.

[0031] The distance between the first fan-out line and the first extension in a third direction is greater than or equal to 2 μm and less than or equal to 2.9 μm. And / or, in the case where the first extension includes a plurality of first sub-sections, the distance between two adjacent first sub-sections in a third direction is greater than or equal to 2 μm and less than or equal to 2.9 μm.

[0032] In some embodiments, the first conductive layer includes a plurality of second voltage signal lines, which are spaced apart along a third direction. A first fan-out line is located between two adjacent second voltage signal lines, and a first extension within the two adjacent second voltage signal lines is symmetrically arranged with respect to the first fan-out line.

[0033] In some embodiments, the first pixel opening is symmetrically arranged with respect to the first virtual line extending along the second direction. The orthographic projection of the first virtual line onto the substrate is located within the boundary range of the orthographic projection of the first fan-out line onto the substrate.

[0034] In some embodiments, the orthographic projection of the second pixel opening onto the substrate and the orthographic projection of the data signal line onto the substrate at least partially overlap. The first conductive layer further includes a second voltage signal line. The data signal line is located on one side of the second voltage signal line along a third direction, which is perpendicular to the first direction and intersects the second direction. The orthographic projection of the second pixel opening onto the substrate and the orthographic projection of the second voltage signal line onto the substrate at least partially overlap.

[0035] In some embodiments, the second voltage signal line includes a main body and a second extension. The main body extends along a second direction. The second extension is connected to the main body. Along a third direction, the second extension is located between the main body and the data signal line.

[0036] The second extension includes a second sub-part extending along a second direction. Alternatively, the second extension includes multiple second sub-parts extending along the second direction, and the multiple second sub-parts are spaced apart along a third direction and connected sequentially.

[0037] The orthographic projection of the second pixel opening onto the substrate overlaps with the orthographic projection of the second sub-part onto the substrate.

[0038] In some embodiments, the dimensions of the data signal line along a third direction are equal to the dimensions of the second sub-part along a third direction. And / or, in the case where the second extension includes a plurality of second sub-parts, the spacing between the data signal line and the second extension along a third direction is equal to the spacing between two adjacent second sub-parts along a third direction.

[0039] In some embodiments, the dimension of the data signal line along a third direction is greater than or equal to 1.9 μm and less than or equal to 2.8 μm. And / or, the dimension of the second sub-part along a third direction is greater than or equal to 1.9 μm and less than or equal to 2.8 μm.

[0040] The spacing between the data signal line and the second extension in a third direction is greater than or equal to 2 μm and less than or equal to 2.9 μm. And / or, in the case where the second extension includes a plurality of second sub-sections, the spacing between two adjacent second sub-sections in a third direction is greater than or equal to 2 μm and less than or equal to 2.9 μm.

[0041] In some embodiments, the first conductive layer includes a plurality of second voltage signal lines, which are spaced apart along a third direction. Data signal lines are located between two adjacent second voltage signal lines.

[0042] In some embodiments, two data signal lines are provided between two adjacent second voltage signal lines. A second virtual line extends along a second direction and is located between the two data signal lines. Second extensions within the two adjacent second voltage signal lines are symmetrically arranged with respect to the second virtual line.

[0043] In some embodiments, the second pixel opening is symmetrically arranged with respect to the second virtual line.

[0044] In some embodiments, in the orthographic projection onto the substrate, there are at least two second pixel openings that have the same shape and area, and that have a different total overlap area with the data signal line and the second voltage signal line.

[0045] In some embodiments, the orthographic projection of the second pixel opening onto the substrate and the orthographic projection of the data signal line onto the substrate at least partially overlap. The first conductive layer further includes a first fan-out line. The first fan-out line is located on one side of the data signal line along a third direction, which is perpendicular to the first direction and intersects the second direction. The orthographic projection of the first fan-out line onto the substrate and the orthographic projection of the second pixel opening onto the substrate at least partially overlap.

[0046] In some embodiments, the first conductive layer includes a plurality of data signal lines, which are spaced apart along a third direction. A first fan-out line is located between two adjacent data signal lines.

[0047] In some embodiments, the second pixel opening is symmetrically arranged with respect to the second virtual line extending along the second direction. The orthographic projection of the second virtual line onto the substrate lies within the boundary range of the orthographic projection of the first fan-out line onto the substrate.

[0048] In some embodiments, the first conductive layer further includes a second voltage signal line. The second voltage signal line extends along a second direction. The second conductive layer also includes a first voltage signal line. The first voltage signal line extends along a third direction, which is perpendicular to the first direction and intersects the second direction. The first voltage signal line is connected to the second voltage signal line.

[0049] In some embodiments, the first conductive layer further includes a first fan-out line. The first fan-out line extends along a second direction. The second conductive layer further includes a second fan-out line. The second fan-out line extends along a third direction, which is perpendicular to the first direction and intersects the second direction.

[0050] The second fan-out line is connected to both the first fan-out line and the data signal line. Alternatively, the light-emitting device layer further includes a second electrode layer located on the side of the pixel definition layer away from the substrate. The second electrode layer includes a third voltage signal line. The second fan-out line is then connected to both the first fan-out line and the third voltage signal line.

[0051] On the other hand, a display panel is provided. The display panel includes a substrate, a driving layer, and a light-emitting device layer. The substrate, the driving layer, and the light-emitting device layer are sequentially stacked along a first direction, which is the thickness direction of the substrate.

[0052] The light-emitting device layer includes multiple light-emitting devices, each including a first electrode. The multiple light-emitting devices include a first-color light-emitting device, a second-color light-emitting device, and a third-color light-emitting device. The light-emitting device layer also includes a first electrode layer and a pixel definition layer. The first electrode layer is formed by the first electrodes within the light-emitting devices. The pixel definition layer is located on the side of the first electrode layer away from the substrate. The pixel definition layer includes a first pixel opening, a second pixel opening, and a third pixel opening.

[0053] The driving layer includes a first conductive layer. The first conductive layer includes a first signal line and a second voltage signal line. The first signal line extends along a second direction, which is perpendicular to the first direction. The second voltage signal line extends along the second direction. The second voltage signal line is located on one side of the first signal line along a third direction, which is perpendicular to the first direction and intersects with the second direction.

[0054] The orthographic projection of at least one of the first pixel opening, the second pixel opening, and the third pixel opening onto the substrate overlaps at least partially with the orthographic projection of the first signal line onto the substrate, and also overlaps at least partially with the orthographic projection of the second voltage signal line onto the substrate.

[0055] In the aforementioned display panel, the orthographic projection of at least one of the first pixel opening, the second pixel opening, and the third pixel opening onto the substrate overlaps with both the orthographic projection of the first signal line onto the substrate and the orthographic projection of the second voltage signal line onto the substrate. Since the orthographic projection of the first pixel opening onto the substrate at least partially coincides with the orthographic projection of the first electrode within the first color light-emitting device onto the substrate, the orthographic projection of the second pixel opening onto the substrate at least partially coincides with the orthographic projection of the first electrode within the second color light-emitting device onto the substrate, and the orthographic projection of the third pixel opening onto the substrate at least partially coincides with the orthographic projection of the first electrode within the third color light-emitting device onto the substrate, when the orthographic projection of at least one of the first pixel opening, the second pixel opening, and the third pixel opening onto the substrate overlaps with both the orthographic projection of the first signal line onto the substrate and the orthographic projection of the second voltage signal line onto the substrate, the portion of the first electrode (i.e., the first electrode within the first color light-emitting device) that overlaps with the first pixel opening in the orthographic projection onto the substrate... At least one of the following: the actual effective area of ​​the electrode, the portion of the first electrode overlapping with the second pixel opening (i.e., the actual effective area of ​​the first electrode in the second color light-emitting device), and the portion of the first electrode overlapping with the third pixel opening (i.e., the actual effective area of ​​the first electrode in the third color light-emitting device), overlaps with both the first signal line and the second voltage signal line. This allows the first signal line and the second voltage signal line to support the actual effective area of ​​the first electrode from different positions, which helps to improve the flatness of the actual effective area of ​​the first electrode. This, in turn, helps to improve the light emission uniformity of at least one of the first color light-emitting device, the second color light-emitting device, and the third color light-emitting device, thereby improving the display effect of the display panel.

[0056] In some embodiments, the first signal line is a first fan-out line.

[0057] In some embodiments, the first conductive layer includes a plurality of second voltage signal lines, which are spaced apart along a third direction. A first fan-out line is located between two adjacent second voltage signal lines.

[0058] In some embodiments, the orthographic projection of the first pixel opening onto the substrate overlaps with both the orthographic projection of the first fan-out line onto the substrate and the orthographic projection of the second voltage signal line onto the substrate.

[0059] The second voltage signal line includes a main body and a first extension. The main body extends along a second direction. The first extension is connected to the main body. Along a third direction, the first extension is located between the main body and the first fan-out line.

[0060] The first extension includes a first sub-part extending along a second direction. Alternatively, the first extension includes multiple first sub-parts extending along the second direction, and the multiple first sub-parts are spaced apart along a third direction and connected sequentially.

[0061] The orthographic projection of the first pixel opening onto the substrate overlaps with the orthographic projection of the first sub-part onto the substrate.

[0062] In some embodiments, the first fan-out line is located between two adjacent second voltage signal lines, and the first extensions within the two adjacent second voltage signal lines are symmetrically arranged relative to the first fan-out line.

[0063] In some embodiments, the first conductive layer further includes data signal lines extending along a second direction. The second voltage signal lines, data signal lines, and first fan-out lines are spaced apart along a third direction. The orthographic projections of the second voltage signal lines, data signal lines, and first fan-out lines onto the substrate all at least partially overlap with the orthographic projections of the second pixel opening onto the substrate.

[0064] In some embodiments, the first conductive layer includes a plurality of data signal lines, which are spaced apart along a third direction. A first fan-out line is located between two adjacent data signal lines, and the two adjacent data signal lines are symmetrically arranged with respect to the first fan-out line.

[0065] In some embodiments, the second pixel opening is symmetrically arranged with respect to the second virtual line extending along the second direction. The orthographic projection of the second virtual line onto the substrate lies within the boundary range of the orthographic projection of the first fan-out line onto the substrate.

[0066] In some embodiments, the first signal line is a data signal line. The orthographic projection of the second pixel opening onto the substrate overlaps with both the orthographic projection of the data signal line onto the substrate and the orthographic projection of the second voltage signal line onto the substrate.

[0067] The second voltage signal line includes a main body and a second extension. The main body extends along a second direction. The second extension is connected to the main body. Along a third direction, the second extension is located between the main body and the data signal line.

[0068] The second extension includes a second sub-part extending along a second direction. Alternatively, the second extension includes multiple second sub-parts extending along the second direction, and the multiple second sub-parts are spaced apart along a third direction and connected sequentially.

[0069] The orthographic projection of the second pixel opening onto the substrate overlaps with the orthographic projection of the second sub-part onto the substrate.

[0070] In some embodiments, the first conductive layer includes a plurality of second voltage signal lines, which are spaced apart along a third direction. Data signal lines are located between two adjacent second voltage signal lines.

[0071] In some embodiments, two data signal lines are provided between two adjacent second voltage signal lines. A second virtual line extends along a second direction and is located between the two data signal lines.

[0072] Two data signal lines are symmetrically arranged with respect to the second virtual line. And / or, the second extensions within two adjacent second voltage signal lines are symmetrically arranged with respect to the second virtual line.

[0073] In some embodiments, the display panel includes a display area and a peripheral area located on at least one side of the display area. A first pixel aperture, a second pixel aperture, and a third pixel aperture are located in the display area. The driving layer further includes a second conductive layer located on the side of the first conductive layer away from the substrate. The orthographic projection of at least one of the first pixel aperture, the second pixel aperture, and the third pixel aperture onto the substrate does not overlap with the orthographic projection of the conductive structure within the second conductive layer onto the substrate.

[0074] In some embodiments, the orthographic projections of the first pixel opening, the second pixel opening, and the third pixel opening onto the substrate, and the orthographic projections of the conductive structure in the second conductive layer onto the substrate do not overlap.

[0075] In some embodiments, the driving layer further includes a second conductive layer. The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes a conductive pattern. The orthographic projection of at least one of the first pixel opening, the second pixel opening, and the third pixel opening onto the substrate is located within the boundary of the orthographic projection of the conductive pattern onto the substrate.

[0076] In some embodiments, the driving layer further includes a second conductive layer. The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes a first voltage signal line extending in a third direction. The first voltage signal line is connected to the second voltage signal line.

[0077] In another aspect, a display device is provided. The display device includes a display panel and a driver chip as described in any of the above embodiments. The driver chip is connected to the display panel.

[0078] The above-described display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0079] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0080] Figure 1 This is a plan view of a display device according to some embodiments;

[0081] Figure 2 For a display panel according to some embodiments Figure 1 ;

[0082] Figure 3 Structure of light-emitting devices within sub-pixels according to some embodiments Figure 1 ;

[0083] Figure 4 Structure of light-emitting devices within sub-pixels according to some embodiments Figure 2 ;

[0084] Figure 5 This is a plan view of a partial region of the first electrode layer within the light-emitting device layer according to some embodiments;

[0085] Figure 6 This is an equivalent circuit diagram of the pixel circuit within a sub-pixel according to some embodiments;

[0086] Figure 7 This is a cross-sectional view of a partial area of ​​a display panel according to some embodiments;

[0087] Figure 8 This is a plan view of a partial region of the first electrode layer and the pixel definition layer within the light-emitting device layer according to some embodiments;

[0088] Figure 9 A plane of a local region of the second conductive layer within the driving layer according to some embodiments Figure 1 ;

[0089] Figure 10 A plane of a local region of the second conductive layer within the driving layer according to some embodiments Figure 2 ;

[0090] Figure 11 A plane of a local region of the second conductive layer within the driving layer according to some embodiments Figure 3 ;

[0091] Figure 12A plane of a local region of the second conductive layer within the driving layer according to some embodiments Figure 4 ;

[0092] Figure 13 A plane representing a local region of the second conductive layer within the driving layer and the pixel definition layer within the light-emitting device layer according to some embodiments. Figure 1 ;

[0093] Figure 14 A plane representing a local region of the second conductive layer within the driving layer and the pixel definition layer within the light-emitting device layer according to some embodiments. Figure 2 ;

[0094] Figure 15 A plane representing a local region of the second conductive layer within the driving layer and the pixel definition layer within the light-emitting device layer according to some embodiments. Figure 3 ;

[0095] Figure 16 A plane representing a local region of the second conductive layer within the driving layer and the pixel definition layer within the light-emitting device layer according to some embodiments. Figure 4 ;

[0096] Figure 17 This is a cross-sectional view of a partial region of the second conductive layer and the second insulating layer within the driving layer, and the first electrode layer within the light-emitting device layer, according to some embodiments.

[0097] Figure 18 A plane of a local region of the first conductive layer within the driving layer according to some embodiments Figure 1 ;

[0098] Figure 19 A plane of a local region of the first conductive layer within the driving layer according to some embodiments Figure 2 ;

[0099] Figure 20 A plane of a local region of the first conductive layer within the driving layer according to some embodiments Figure 3 ;

[0100] Figure 21 A plane of a local region of the first conductive layer within the driving layer according to some embodiments Figure 4 ;

[0101] Figure 22 A plane of a local region of the first conductive layer within the driving layer according to some embodiments Figure 5 ;

[0102] Figure 23 A plane of a local region of the first conductive layer within the driving layer according to some embodiments Figure 6 ;

[0103] Figure 24 A plane of a local region of the first conductive layer within the driving layer according to some embodiments Figure 7 ;

[0104] Figure 25 Plane of a local region of the first and second conductive layers within the driving layer according to some embodiments Figure 1 ;

[0105] Figure 26 Plane of a local region of the first and second conductive layers within the driving layer according to some embodiments Figure 2 ;

[0106] Figure 27 For a display panel according to some embodiments Figure 2 ;

[0107] Figure 28 A plane representing a local region of the first conductive layer within the driving layer and the pixel definition layer within the light-emitting device layer according to some embodiments. Figure 1 ;

[0108] Figure 29 A plane representing a local region of the first conductive layer within the driving layer and the pixel definition layer within the light-emitting device layer according to some embodiments. Figure 2 ;

[0109] Figure 30 A plane representing a local region of the first conductive layer within the driving layer and the pixel definition layer within the light-emitting device layer according to some embodiments. Figure 3 ;

[0110] Figure 31 A plane representing a local region of the first conductive layer within the driving layer and the pixel definition layer within the light-emitting device layer according to some embodiments. Figure 4 ;

[0111] Figure 32 A plane representing a local region of the first conductive layer within the driving layer and the pixel definition layer within the light-emitting device layer according to some embodiments. Figure 5 ;

[0112] Figure 33 A plane representing a local region of the first conductive layer within the driving layer and the pixel definition layer within the light-emitting device layer according to some embodiments. Figure 6 ;

[0113] Figure 34 A plane representing a local region of the first conductive layer within the driving layer and the pixel definition layer within the light-emitting device layer according to some embodiments. Figure 7 ;

[0114] Figure 35For a planar region of a first conductive layer and a second conductive layer within a driving layer according to some embodiments, and a pixel definition layer within a light-emitting device layer. Figure 1 ;

[0115] Figure 36 For a planar region of a first conductive layer and a second conductive layer within a driving layer according to some embodiments, and a pixel definition layer within a light-emitting device layer. Figure 2 ;

[0116] Figure 37 For a planar region of a first conductive layer and a second conductive layer within a driving layer according to some embodiments, and a pixel definition layer within a light-emitting device layer. Figure 3 ;

[0117] Figure 38 For a planar region of a first conductive layer and a second conductive layer within a driving layer according to some embodiments, and a pixel definition layer within a light-emitting device layer. Figure 4 ;

[0118] Figure 39 For a planar region of a first conductive layer and a second conductive layer within a driving layer according to some embodiments, and a pixel definition layer within a light-emitting device layer. Figure 5 ;

[0119] Figure 40 For a planar region of a first conductive layer and a second conductive layer within a driving layer according to some embodiments, and a pixel definition layer within a light-emitting device layer. Figure 6 ;

[0120] Figure 41 For a planar region of a first conductive layer and a second conductive layer within a driving layer according to some embodiments, and a pixel definition layer within a light-emitting device layer. Figure 7 ;

[0121] Figure 42 For a planar region of a first conductive layer and a second conductive layer within a driving layer according to some embodiments, and a pixel definition layer within a light-emitting device layer. Figure 8 ;

[0122] Figure 43 For a planar region of a first conductive layer and a second conductive layer within a driving layer according to some embodiments, and a pixel definition layer within a light-emitting device layer. Figure 9 ;

[0123] Figure 44 For a planar region of a first conductive layer and a second conductive layer within a driving layer according to some embodiments, and a pixel definition layer within a light-emitting device layer. Figure 10 ;

[0124] Figure 45 For a planar region of a first conductive layer and a second conductive layer within a driving layer according to some embodiments, and a pixel definition layer within a light-emitting device layer. Figure 10 one;

[0125] Figure 46 For a planar region of a first conductive layer and a second conductive layer within a driving layer according to some embodiments, and a pixel definition layer within a light-emitting device layer. Figure 10 two;

[0126] Figure 47 This is a cross-sectional view of a partial region of the first conductive layer, the first insulating layer, and the second conductive layer within the driving layer according to some embodiments.

[0127] Figure 48 This is a cross-sectional view of a portion of a first conductive layer, a first insulating layer, and a second insulating layer within a driving layer, and a first electrode layer within a light-emitting device layer, according to some embodiments.

[0128] Figure 49 This is a plan view of a partial area of ​​the driving layer within a display panel according to some embodiments;

[0129] Figure 50 This is a plan view of a partial region of the light-shielding layer and the first active layer within the driving layer according to some embodiments;

[0130] Figure 51 This is a plan view of a partial region of the first active layer and the first gate layer within the driving layer according to some embodiments;

[0131] Figure 52 This is a plan view of a partial region of the first gate layer and the second gate layer within the driving layer according to some embodiments;

[0132] Figure 53 A plan view of a partial region of the second gate layer, the second active layer, and the third gate layer within the driving layer according to some embodiments;

[0133] Figure 54 This is a plan view of a partial region of the third gate layer and the first source / drain conductive layer within the driving layer according to some embodiments. Detailed Implementation

[0134] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0135] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0136] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0137] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0138] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0139] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0140] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0141] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0142] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0143] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0144] For ease of description below, an XYZ coordinate system is established. The first direction Z is the thickness direction of the substrate, and the second direction Y and the third direction X are both perpendicular to the first direction Z, and the second direction Y and the third direction X intersect. For example, the second direction Y can be perpendicular to the third direction X.

[0145] It should be noted that, for example, 3 (100) in the accompanying drawings of this disclosure indicates that component 3 belongs to component 100, and 2211 / 221 indicates that the component can be either 221 or 2211. Other similar reference numerals in the accompanying drawings also follow the above description.

[0146] like Figure 1 As shown, some embodiments of this disclosure provide a display device 1000.

[0147] Exemplarily, the display device 1000 can be any device that displays images, whether moving (e.g., video) or stationary (e.g., still images), and whether text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, Global Positioning System (GPS) receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 The following is an illustration using a mobile phone as an example, with display device 1000 as an example.

[0148] For example, the display device 1000 may be an electroluminescent display device or a photoluminescent display device.

[0149] When the display device 1000 is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) display device or a quantum dot light-emitting diode (QLED) display device.

[0150] When the display device 1000 is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0151] The following describes some embodiments of this disclosure using an organic light-emitting diode display device or a quantum dot light-emitting diode display device as examples.

[0152] In some embodiments, please continue reading Figure 1The display device 1000 may include a display panel 100 and a driver chip (not shown in the figure). The driver chip is connected to the display panel 100 and can be configured to drive the display panel 100 to display images.

[0153] It should be noted that, from the perspective of connection medium and signal transmission principle, the above-mentioned "connection" can be electrical connection, etc.

[0154] For example, the connection between the driver chip and the display panel 100 can be an electrical connection.

[0155] When the connection between the driver chip and the display panel 100 is an electrical connection, an electrical path can be established between the driver chip and the display panel 100 through a conductive material, so that electrical signals can be effectively transmitted between the driver chip and the display panel 100.

[0156] From the perspective of the connection path, the above "connection" can be a direct connection or an indirect connection, etc.

[0157] For example, the connection between the driver chip and the display panel 100 can be a direct connection.

[0158] When the connection between the driver chip and the display panel 100 is a direct connection, the driver chip and the display panel 100 can communicate directly through a dedicated channel to achieve fast data signal transmission.

[0159] For example, the connection between the driver chip and the display panel 100 can be an indirect connection.

[0160] When the connection between the driver chip and the display panel 100 is indirect, the driver chip and the display panel 100 can transfer data signals through an intermediate component to enhance the flexibility of the display device 1000.

[0161] The following description of "connection" will follow this explanation and will not be repeated.

[0162] For example, the driver chip within the display device 1000 may include a source driver IC.

[0163] For example, the driver chip in the display device 1000 can be encapsulated by means of chip on film (COF), chip on glass (COG), or chip on flexible material (COP) and bonded to the display panel 100.

[0164] For example, when the display device 1000 is an organic light-emitting diode (OLED) display device, the display panel 100 within the display device 1000 can be an OLED display panel.

[0165] When the display device 1000 is a quantum dot electroluminescent diode display device, the display panel 100 within the display device 1000 can be a quantum dot electroluminescent diode display panel.

[0166] In some embodiments, please continue reading Figure 1 The display device 1000 may include optical components 200.

[0167] For example, the optical device 200 may include a camera, enabling the display device 1000 to perform various functions such as taking pictures, recording videos, or facial recognition.

[0168] The optical device 200 may also include sensors, etc. For example, the optical device 200 may include a fingerprint recognition sensor, enabling the display device 1000 to perform functions such as fingerprint recognition.

[0169] The structure of the above-mentioned display panel 100 will be described in detail below.

[0170] In some embodiments, such as Figure 2 As shown, Figure 2 This is a plan view of a display panel 100 according to some embodiments. The display panel 100 may be a rectangular structure.

[0171] It should be noted that the aforementioned "rectangular structure" refers to the fact that the overall shape of the boundary of the display panel 100 is rectangular, but it is not limited to a standard rectangle. That is, "rectangle" here includes not only the shape of a standard rectangle, but also, considering manufacturing conditions, shapes similar to rectangles. For example, please continue reading... Figure 2 The long and short sides of the rectangle can be curved at each intersection (i.e., at the corner G), that is, the corner G is smooth, so that the boundary of the display panel 100 is a rounded rectangle in the plan view.

[0172] In other embodiments, the display panel 100 may be a circular structure or other shapes with corners.

[0173] The following uses a rectangular structure for the display panel 100 as an example to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the shape of the display panel 100 can also be any other shape.

[0174] In some embodiments, please continue reading Figure 2The display panel 100 has a display area AA for displaying images and a peripheral area AN located on at least one side of the display area AA.

[0175] For example, the peripheral area AN can be located on one side of the display area AA.

[0176] Alternatively, the peripheral area AN can be located on opposite sides of the display area AA.

[0177] Alternatively, please continue reading Figure 2 The surrounding area AN can surround the display area AA.

[0178] For example, please continue reading Figure 2 The peripheral area AN of the display panel 100 may contain a gate driver on array (GOA) and control signal lines (e.g., clock signal lines, power supply voltage signal lines, etc.). However, the functions of the peripheral area AN of the display panel 100 include, but are not limited to, these.

[0179] In some embodiments, please continue reading Figure 2 The display panel 100 may include multiple sub-pixels S.

[0180] For example, please continue reading Figure 2 When the display panel 10 has a display area AA, multiple sub-pixels S can be disposed within the display area AA of the display panel 100. The sub-pixel S is the smallest light-emitting unit within the display area AA.

[0181] For example, please continue reading Figure 2 Multiple sub-pixels S within the display panel 100 can be arranged in an array.

[0182] For example, please continue reading Figure 2 Multiple sub-pixels S can be arranged at intervals along the second direction Y and the third direction X, respectively.

[0183] For example, multiple sub-pixels S within the display panel 100 can emit light of the same color.

[0184] When multiple sub-pixels S within the display panel 100 emit light of the same color, the display panel 100 may further include a color filter layer (not shown) disposed on the light-emitting side of the multiple sub-pixels S. For example, the multiple sub-pixels S within the display panel 100 may all emit light of colors such as white, red, green, or blue. In this case, the colored light emitted by the sub-pixels S is emitted as the same color after passing through the color filter layer, or is converted into other colors of light and emitted. Thus, when multiple sub-pixels S emit light of the same color, the display panel 100 can achieve multi-color light emission.

[0185] Alternatively, multiple sub-pixels S within the display panel 100 can emit light of different colors.

[0186] For example, the multiple sub-pixels S in the display panel 100 may include a first color sub-pixel that emits a first color light, a second color sub-pixel that emits a second color light, and a third color sub-pixel that emits a third color light, thereby realizing multi-color light emission of the display panel 100.

[0187] It should be noted that the "light-emitting side of sub-pixel S" mentioned above refers to the side of sub-pixel S that emits light.

[0188] In some embodiments, please continue reading Figure 2 In the case where the display panel 100 includes a plurality of sub-pixels S, the plurality of sub-pixels S in the display panel 100 may include a plurality of light-emitting devices S1.

[0189] For example, such as Figure 3 and Figure 4 As shown, and in combination Figure 2 , Figure 3 and Figure 4 These are structural diagrams of light-emitting devices S1 within sub-pixels S according to some embodiments. Multiple light-emitting devices S1 may include a first color light-emitting device S11.

[0190] In the case where the display panel 100 includes a first color sub-pixel that emits a first color light, the first color sub-pixel may include a first color light-emitting device S11.

[0191] For example, the first color sub-pixel can be a green sub-pixel, and the first color light-emitting device S11 can be a green light-emitting device.

[0192] For example, please continue reading Figure 3 and Figure 4 The multiple light-emitting devices S1 may include a second color light-emitting device S12.

[0193] In the case where the display panel 100 includes a second color sub-pixel that emits a second color light, the second color sub-pixel may include a second color light-emitting device S12.

[0194] For example, the second color sub-pixel can be a red sub-pixel, and the second color light-emitting device S12 can be a red light-emitting device.

[0195] For example, please continue reading Figure 3 and Figure 4 The multiple light-emitting devices S1 may include a third color light-emitting device S13.

[0196] In the case where the display panel 100 includes a third color sub-pixel that emits a third color light, the third color sub-pixel may include a third color light-emitting device S13.

[0197] For example, the third color sub-pixel can be a blue sub-pixel, and the third color light-emitting device S13 can be a blue light-emitting device.

[0198] For example, such as Figure 5 As shown, Figure 5 This is a plan view of a partial region of the first electrode layer 31 within the light-emitting device layer 3 according to some embodiments. When the plurality of light-emitting devices S1 include a first color light-emitting device S11, a second color light-emitting device S12, and a third color light-emitting device S13, the plurality of first color light-emitting devices S11 can be arranged at intervals along the third direction X, and the plurality of second color light-emitting devices S12 and the plurality of third color light-emitting devices S13 can be arranged alternately along the third direction X.

[0199] Please continue reading. Figure 5 Along the second direction Y, the first color light-emitting device S11 can correspond to the gap area between the adjacent second color light-emitting device S12 and the third color light-emitting device S13, the second color light-emitting device S12 can correspond to the gap area between two adjacent first color light-emitting devices S11, and the third color light-emitting device S13 can correspond to the gap area between two adjacent first color light-emitting devices S11.

[0200] For example, please continue reading Figure 3 and Figure 4 The light-emitting device S1 may include a first electrode 311.

[0201] For example, the material of the first electrode 311 in the light-emitting device S1 may include a metallic material. Specifically, the material of the first electrode 311 may include one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo).

[0202] The material of the first electrode 311 within the light-emitting device S1 may also include an alloy material. Specifically, the material of the first electrode 311 may include one or more of aluminum-neodymium alloy (AlNd) and molybdenum-niobium alloy (MoNb).

[0203] The material of the first electrode 311 within the light-emitting device S1 may also include a transparent conductive material. Specifically, the material of the first electrode 311 may include one or more of indium tin oxide (ITO) and indium zinc oxide (IZO).

[0204] For example, the first electrode 311 in the light-emitting device S1 can be a single-layer structure.

[0205] Alternatively, the first electrode 311 within the light-emitting device S1 can be a multilayer composite structure. Specifically, the first electrode 311 can be a titanium / aluminum / titanium (Ti / Al / Ti) structure, an indium tin oxide / silver / indium tin oxide (ITO / Ag / ITO) structure, or a molybdenum / aluminum-neodymium alloy / indium tin oxide (Mo / AlNd / ITO) structure, etc.

[0206] For example, please continue reading Figure 3 and Figure 4 The light-emitting device S1 may include a light-emitting part 321.

[0207] The light-emitting part 321 may include a light-emitting layer 3211.

[0208] For example, please continue reading Figure 3 When the display panel 100 is an organic light-emitting diode (OLED) display panel, the light-emitting layer 3211 within the light-emitting portion 321 may include an organic light-emitting layer (EML). The organic light-emitting layer (EML) may include a light-emitting layer host material and a light-emitting layer guest material, and the light-emitting layer guest material may be a fluorescent dopant or a phosphorescent dopant, etc.

[0209] For example, please continue reading Figure 4 In the case where the display panel 100 is a quantum dot electroluminescent diode display panel, the light-emitting layer 3211 within the light-emitting part 321 may include a quantum dot layer (QDL). The quantum dot layer (QDL) may have quantum dot particles, and the quantum dot particles may be interconnected by surface modification groups.

[0210] Please continue reading. Figure 3 and Figure 4 The light-emitting part 321 may also include one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0211] For example, please continue reading Figure 3 and Figure 4 The light-emitting device S1 may include a second electrode 331.

[0212] For example, the material of the second electrode 331 within the light-emitting device S1 may include a metallic material. Specifically, the material of the second electrode 331 may include one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo).

[0213] The material of the second electrode 331 within the light-emitting device S1 may also include an alloy material. Specifically, the material of the second electrode 331 may include one or more of aluminum-neodymium alloy (AlNd) and molybdenum-niobium alloy (MoNb).

[0214] The material of the second electrode 331 within the light-emitting device S1 may also include a transparent conductive material. Specifically, the material of the second electrode 331 may include one or more of indium tin oxide (ITO) and indium zinc oxide (IZO).

[0215] For example, please continue reading Figure 3 and Figure 4 When the light-emitting device S1 includes a first electrode 311, a light-emitting part 321, and a second electrode 331, the first electrode 311, the light-emitting part 321, and the second electrode 331 can be stacked sequentially along the first direction Z. The first electrode 311 and the second electrode 331 can provide charge carriers such as electrons and holes to the light-emitting part 321 so that the light-emitting part 321 emits light.

[0216] Please continue reading. Figure 3 and Figure 4 One of the first electrode 311 and the second electrode 331 can be used as the anode of the light-emitting device S1, and the other can be used as the cathode of the light-emitting device S1.

[0217] For example, please continue reading Figure 3 and Figure 4 The first electrode 311 can be used as the anode of the light-emitting device S1, and the second electrode 331 can be used as the cathode of the light-emitting device S1.

[0218] When the first electrode 311 serves as the anode of the light-emitting device S1 and the second electrode 331 serves as the cathode of the light-emitting device S1, when a voltage is applied between the first electrode 311 and the second electrode 331, holes injected from the first electrode 311 can be transported to the light-emitting part 321 in the light-emitting device S1, and electrons injected from the second electrode 331 can also be transported to the light-emitting part 321 in the light-emitting device S1. Electrons and holes, as charge carriers, recombine in the light-emitting part 321 to generate excitons. When the excitons transition from the excited state to the ground state, they emit light, thereby causing the light-emitting part 321 to emit light, and thus causing the light-emitting device S1 to emit light.

[0219] In some embodiments, please continue reading Figure 2 In the case where the display panel 100 includes a plurality of sub-pixels S, and each sub-pixel S includes a light-emitting device S1, the sub-pixel S may also include a pixel circuit S2. The pixel circuit S2 is connected to the light-emitting device S1 and can be used to drive the light-emitting device S1 to emit light.

[0220] For example, please continue reading Figure 2 The pixel circuit S2 and the light-emitting device S1 can have a one-to-one driving relationship. That is, one light-emitting device S1 can be connected to a corresponding pixel circuit S2.

[0221] Alternatively, the pixel circuit S2 and the light-emitting device S1 can have a one-to-many driving relationship. That is, one pixel circuit S2 can be connected to multiple light-emitting devices S1 and configured to drive multiple light-emitting devices S1 to emit light.

[0222] For example, such as Figure 6 As shown, Figure 6 This is an equivalent circuit diagram of the pixel circuit S2 within a sub-pixel S according to some embodiments. The pixel circuit S2 can be an 8T1C structure, where T represents a transistor, the number preceding T indicates the number of transistors, and C represents a capacitor, the number preceding C indicates the number of capacitors. That is, the pixel circuit S2 can include 8 transistors and 1 capacitor.

[0223] Alternatively, the pixel circuit S2 can be a structure such as 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 6T2C, or 7T1C.

[0224] The following uses an 8T1C structure for the pixel circuit S2 within sub-pixel S as an example to illustrate some embodiments of this disclosure.

[0225] In some embodiments, please continue reading Figure 6 When the pixel circuit S2 within the sub-pixel S has an 8T1C structure, the pixel circuit S2 may include a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, a third reset transistor T8, and a storage capacitor C1.

[0226] For example, please continue reading Figure 6 At least one of the first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7 and third reset transistor T8 in the pixel circuit S2 can be a P-type transistor.

[0227] The turn-on voltage of a P-type transistor can be a low-level voltage (e.g., the turn-on voltage of a P-type transistor can be 0V, -5V, or -10V, etc.), and the turn-off voltage of a P-type transistor can be a high-level voltage (e.g., the turn-off voltage of a P-type transistor can be 5V or 10V, etc.).

[0228] Alternatively, please continue reading Figure 6 At least one of the first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7 and third reset transistor T8 in the pixel circuit S2 can be an N-type transistor.

[0229] The turn-on voltage of an N-type transistor can be a high-level voltage (e.g., the turn-on voltage of an N-type transistor can be 5V or 10V, etc.), and the turn-off voltage of an N-type transistor can be a low-level voltage (e.g., the turn-off voltage of an N-type transistor can be 0V, -5V, or -10V, etc.).

[0230] For example, the first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8 in the pixel circuit S2 can all be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit S2 can simplify the process flow, reduce the process difficulty when manufacturing the display panel 100, and thus improve the yield of the display panel 100.

[0231] For example, please continue reading Figure 6 In the pixel circuit S2, some of the transistors among the first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8 can be P-type transistors, and the other part of the transistors can be N-type transistors.

[0232] It should be noted that, Figure 6 In the embodiments shown, only the threshold compensation transistor T2 is an N-type transistor, and the first reset transistor T1, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7 and third reset transistor T8 are P-type transistors, to illustrate some embodiments of this disclosure.

[0233] For example, at least one of the first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8 in the pixel circuit S2 can be a low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT). LTPS-TFTs have advantages such as high mobility and fast charging.

[0234] Alternatively, at least one of the first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8 in the pixel circuit S2 can be an oxide thin film transistor (Oxide-TFT). Oxide thin film transistors have advantages such as low leakage current.

[0235] When a portion of the transistors in the pixel circuit S2—the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8—are low-temperature polycrystalline silicon thin-film transistors (LTPO), and the remaining portion are oxide thin-film transistors (OPT). Therefore, the display panel 100 including the pixel circuit S2 can be a low-temperature polycrystalline oxide (LTPO) display panel. LTPO display panels enable low-frequency driving, which helps reduce the power consumption of the display panel 100 and improves its display performance.

[0236] For example, the first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light emission control transistor T5, second light emission control transistor T6, second reset transistor T7 and third reset transistor T8 in the pixel circuit S2 can be top gate transistors, bottom gate transistors or dual gate transistors.

[0237] For example, please continue reading Figure 6 The pixel circuit S2 may also include a first node N1, a second node N2, a third node N3, and a fourth node N4.

[0238] It should be noted that in the pixel circuit S2 provided in the embodiments of this disclosure, the first node N1, the second node N2, the third node N3, and the fourth node N4 do not represent actual existing components, but rather represent the junction points of related connections in the equivalent circuit diagram of the pixel circuit S2. That is to say, the first node N1, the second node N2, the third node N3, and the fourth node N4 are nodes equivalent to the junction points of related connections in the equivalent circuit diagram of the pixel circuit S2.

[0239] Please continue reading. Figure 6 The first node N1 can be connected to the control terminal of the driving transistor T3, the first plate of the storage capacitor C1, and the second terminal of the threshold compensation transistor T2. The second node N2 can be connected to the first terminal of the driving transistor T3, the second terminal of the first light-emitting control transistor T5, the second terminal of the data writing transistor T4, and the second terminal of the third reset transistor T8. The third node N3 can be connected to the second terminal of the first reset transistor T1, the first terminal of the threshold compensation transistor T2, the first terminal of the second light-emitting control transistor T6, and the second terminal of the driving transistor T3. The fourth node N4 can be connected to the second terminal of the second light-emitting control transistor T6, the second terminal of the second reset transistor T7, and the light-emitting device S1.

[0240] The first plate of the storage capacitor C1 can be connected to the first node N1, and the second plate of the storage capacitor C1 can be connected to the first voltage signal line V1.

[0241] The first terminal of the first reset transistor T1 can be connected to the first initialization signal line Vinit1, the second terminal of the first reset transistor T1 can be connected to the second terminal of the driving transistor T3, and the gate of the first reset transistor T1 can be connected to the first reset control signal line Reset1.

[0242] The first terminal of the threshold compensation transistor T2 can be connected to the second terminal of the driving transistor T3, the second terminal of the threshold compensation transistor T2 can be connected to the gate of the driving transistor T3, and the gate of the threshold compensation transistor T2 can be connected to the first scan signal line Ngate.

[0243] The gate of the driving transistor T3 can be connected to the first plate of the storage capacitor C1, the first terminal of the driving transistor T3 can be connected to the second node N2, and the second terminal of the driving transistor T3 can be connected to the third node N3.

[0244] The second terminal of the data writing transistor T4 can be connected to the first terminal of the driving transistor T3, the first terminal of the data writing transistor T4 can be connected to the data signal line D1, and the gate of the data writing transistor T4 can be connected to the second scan signal line Pgate.

[0245] The first terminal of the first light-emitting control transistor T5 can be connected to the first voltage signal line V1, the second terminal of the first light-emitting control transistor T5 can be connected to the first terminal of the driving transistor T3, and the gate of the first light-emitting control transistor T5 can be connected to the light-emitting control signal line EM.

[0246] The first electrode of the second light-emitting control transistor T6 can be connected to the second electrode of the driving transistor T3, the second electrode of the second light-emitting control transistor T6 can be connected to the first electrode in the light-emitting device S1, and the gate of the second light-emitting control transistor T6 can be connected to the light-emitting control signal line EM.

[0247] The first electrode of the second reset transistor T7 can be connected to the second initialization signal line Vinit2, the second electrode of the second reset transistor T7 can be connected to the first electrode in the light-emitting device S1, and the gate of the second reset transistor T7 can be connected to the second reset control signal line Reset2.

[0248] The first terminal of the third reset transistor T8 can be connected to the third initialization signal line Vinit3, the second terminal of the third reset transistor T8 can be connected to the first terminal of the driving transistor T3, and the gate of the third reset transistor T8 can be connected to the second reset control signal line Reset2.

[0249] The second electrode inside the light-emitting device S1 can be connected to the third voltage signal line V3.

[0250] The light-emitting devices S1 (e.g., first-color light-emitting device S11, second-color light-emitting device S12 and third-color light-emitting device S13), pixel circuits S2 and signal lines in the display panel 100 can be disposed within the film layer structure of the display panel 100. The film layer structure of the display panel 100 will be described in detail below.

[0251] In some embodiments, such as Figure 7 As shown, Figure 7 This is a cross-sectional view of a partial area of ​​a display panel 100 according to some embodiments. The display panel 100 may include a substrate 1, a driving layer 2, and a light-emitting device layer 3. The substrate 1, the driving layer 2, and the light-emitting device layer 3 are sequentially stacked along a first direction Z, where the first direction Z is the thickness direction of the substrate 1.

[0252] For example, substrate 1 can be a rigid substrate.

[0253] For example, the material of substrate 1 may include one of glass and polymethyl methacrylate (PMMA).

[0254] For example, the material of substrate 1 may include multiple (two or more) materials such as glass and polymethyl methacrylate.

[0255] Alternatively, substrate 1 can be a flexible substrate.

[0256] For example, the material of substrate 1 may include one of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyimide (PI).

[0257] For example, the material of substrate 1 may include a variety of materials such as polyethylene terephthalate, polyethylene thiocyanate, and polyimide.

[0258] For example, please continue reading Figure 7 The multiple light-emitting devices S1 within the display panel 100 can be located within the light-emitting device layer 3. That is, the light-emitting device layer 3 can include multiple light-emitting devices S1.

[0259] For example, please continue reading Figure 7 and combined Figure 2 Multiple pixel circuits S2 within the display panel 100 can be located within the driving layer 2.

[0260] For example, please continue reading Figure 7 The display panel 100 may also include an encapsulation layer 4. The encapsulation layer 4 is located on the side of the light-emitting device layer 3 away from the substrate 1. The encapsulation layer 4 can be used to encapsulate the light-emitting device layer 3, thereby protecting the light-emitting device layer 3 from corrosion caused by external water and oxygen.

[0261] For example, encapsulation layer 4 may include an inorganic encapsulation layer and an organic encapsulation layer. The inorganic encapsulation layer is made of inorganic materials and can be used to block water and oxygen. The organic encapsulation layer is made of organic materials and can serve to flatten interfaces, cover defects, and relieve stress.

[0262] The structure of the light-emitting device layer 3 described above will be explained in detail below.

[0263] In some embodiments, please continue reading Figure 7 and combined Figure 8 , Figure 8 This is a plan view of a partial region of the first electrode layer 31 and the pixel definition layer PDL within the light-emitting device layer 3 according to some embodiments. The light-emitting device layer 3 may include the first electrode layer 31 and the pixel definition layer PDL. The pixel definition layer PDL is located on the side of the first electrode layer 31 away from the substrate 1. The first electrode layer 31 may be formed by the first electrode 311 within the light-emitting device S1.

[0264] Please continue reading. Figure 8 and combined Figure 7 In the case where the plurality of light-emitting devices S1 within the display panel 100 include a first color light-emitting device S11, the first electrode layer 31 may include a first electrode 311 within the first color light-emitting device S11, and the pixel definition layer PDL may include a first pixel opening K1. The orthographic projection of the first pixel opening K1 onto the substrate 1 and the orthographic projection of the first electrode 311 within the first color light-emitting device S11 onto the substrate 1 at least partially overlap.

[0265] Please continue reading. Figure 8 and combined Figure 7 In the case where the plurality of light-emitting devices S1 within the display panel 100 includes a second color light-emitting device S12, the first electrode layer 31 may include a first electrode 311 within the second color light-emitting device S12, and the pixel definition layer PDL may include a second pixel opening K2. The orthographic projection of the second pixel opening K2 onto the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 311 within the second color light-emitting device S12 onto the substrate 1.

[0266] Please continue reading. Figure 8 and combined Figure 7 In the case where the plurality of light-emitting devices S1 within the display panel 100 includes a third color light-emitting device S13, the first electrode layer 31 may include a first electrode 311 within the third color light-emitting device S13, and the pixel definition layer PDL may include a third pixel opening K3. The orthographic projection of the third pixel opening K3 onto the substrate 1 and the orthographic projection of the first electrode 311 within the third color light-emitting device S13 onto the substrate 1 at least partially overlap.

[0267] For example, please continue reading Figure 8 and combined Figure 2 When the display panel 100 has a display area AA, the first pixel opening K1, the second pixel opening K2 and the third pixel opening K3 in the pixel definition layer PDL can be located in the display area AA of the display panel 100.

[0268] In some embodiments, please continue reading Figure 7 and Figure 8In the case where the light-emitting device layer 3 includes a first electrode layer 31 and a pixel definition layer PDL, and the first electrode layer 31 includes a first electrode 311 in the first color light-emitting device S11, a first electrode 311 in the second color light-emitting device S12, and a first electrode 311 in the third color light-emitting device S13, and the pixel definition layer PDL includes a first pixel opening K1, a second pixel opening K2, and a third pixel opening K3, the light-emitting device layer 3 may further include a light-emitting functional layer 32 and a second electrode layer 33. The second electrode layer 33 is located on the side of the pixel definition layer PDL away from the substrate 1, and is also located on the side of the light-emitting functional layer 32 away from the substrate 1.

[0269] The second electrode layer 33 may include the second electrode 331 in the first color light-emitting device S11, the second electrode 331 in the second color light-emitting device S12, and the second electrode 331 in the third color light-emitting device S13.

[0270] The light-emitting functional layer 32 may include a light-emitting portion 321 in the first color light-emitting device S11, a light-emitting portion 321 in the second color light-emitting device S12, and a light-emitting portion 321 in the third color light-emitting device S13. The light-emitting portion 321 in the first color light-emitting device S11 may be located within the first pixel opening K1 and connected to the first electrode 311 and the second electrode 331 within the first color light-emitting device S11, respectively. The light-emitting portion 321 in the second color light-emitting device S12 may be located within the second pixel opening K2 and connected to the first electrode 311 and the second electrode 331 within the second color light-emitting device S12, respectively. The light-emitting portion 321 in the third color light-emitting device S13 may be located within the third pixel opening K3 and connected to the first electrode 311 and the second electrode 331 within the third color light-emitting device S13, respectively.

[0271] Please continue reading. Figure 8 and combined Figure 7 Since the orthographic projection of the first pixel opening K1 in the pixel definition layer PDL onto the substrate 1 and the orthographic projection of the first electrode 311 in the first color light-emitting device S11 onto the substrate 1 at least partially overlap, the pixel definition layer PDL can define the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11 (i.e., the area where the first electrode 311 in the first color light-emitting device S11 is directly connected to the light-emitting part 321 in the first color light-emitting device S11), thereby enabling the pixel definition layer PDL to define the light-emitting area and light-emitting area of ​​the first color light-emitting device S11.

[0272] Since the orthographic projection of the second pixel opening K2 in the pixel definition layer PDL onto the substrate 1 and the orthographic projection of the first electrode 311 in the second color light-emitting device S12 onto the substrate 1 are at least partially overlapped, the pixel definition layer PDL can define the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12 (i.e., the area where the first electrode 311 in the second color light-emitting device S12 is directly connected to the light-emitting part 321 in the second color light-emitting device S12), thereby enabling the pixel definition layer PDL to define the light-emitting area and light-emitting area of ​​the second color light-emitting device S12.

[0273] Since the orthographic projection of the third pixel opening K3 in the pixel definition layer PDL onto the substrate 1 and the orthographic projection of the first electrode 311 in the third color light-emitting device S13 onto the substrate 1 at least partially overlap, the pixel definition layer PDL can define the actual effective area of ​​the first electrode 311 in the third color light-emitting device S13 (i.e., the area where the first electrode 311 in the third color light-emitting device S13 is directly connected to the light-emitting part 321 in the third color light-emitting device S13), thereby enabling the pixel definition layer PDL to define the light-emitting area and light-emitting area of ​​the third color light-emitting device S13.

[0274] For example, please continue reading Figure 7 The third voltage signal line V3 within the display panel 100 can be located within the second electrode layer 33. That is, the second electrode layer 33 may include the third voltage signal line V3.

[0275] Please continue reading. Figure 7 The third voltage signal line V3 can be connected to the second electrode 331 in the light-emitting device S1 (e.g., the first color light-emitting device S11, the second color light-emitting device S12, and the third color light-emitting device S13).

[0276] For example, please continue reading Figure 7 The second electrode 331 within the light-emitting device S1 can be considered as part of the third voltage signal line V3. Alternatively, the third voltage signal line V3 can be considered as an extension of the second electrode 331 within the light-emitting device S1.

[0277] The structure of the aforementioned driving layer 2 will be described in detail below.

[0278] In some embodiments, such as Figure 9 , Figure 10 , Figure 11 and Figure 12 As shown, Figure 9 , Figure 10 , Figure 11 and Figure 12 These are all plan views of a partial region of the second conductive layer 22 within the driving layer 2 according to some embodiments. The driving layer 2 may include the second conductive layer 22.

[0279] For example, please continue reading Figure 9 , Figure 10 , Figure 11 and Figure 12 The first voltage signal line V1 within the display panel 100 can be located within the second conductive layer 22. That is, the second conductive layer 22 can include the first voltage signal line V1. The first voltage signal line V1 can extend along a third direction X, which is perpendicular to the first direction Z and intersects with the second direction Y.

[0280] For example, please continue reading Figure 9 , Figure 10 , Figure 11 and Figure 12 The second conductive layer 22 may include a second fan-out line F2. The second fan-out line F2 may extend along a third direction X.

[0281] Please continue reading. Figure 9 , Figure 10 , Figure 11 and Figure 12 In the case that the second conductive layer 22 also includes a first voltage signal line V1, and the first voltage signal line V1 extends along the third direction X, the second fan-out line F2 and the first voltage signal line V1 can be arranged at intervals along the second direction Y, or the second fan-out line F2 and the first voltage signal line V1 can be arranged alternately along the second direction Y.

[0282] In some embodiments, such as Figure 13 , Figure 14 and Figure 15 As shown, and in combination Figure 7 , Figure 13 , Figure 14 and Figure 15 These are partial plan views of the second conductive layer 22 in the driving layer 2 and the pixel definition layer PDL in the light-emitting device layer 3, according to some embodiments. When the driving layer 2 includes the second conductive layer 22, the light-emitting device layer 3 includes the pixel definition layer PDL, and the pixel definition layer PDL includes a first pixel opening K1, a second pixel opening K2, and a third pixel opening K3, the orthogonal projection of at least one of the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3 onto the substrate 1 can be non-overlapping with the orthogonal projection of the conductive structure in the second conductive layer 22 onto the substrate 1.

[0283] In the aforementioned display panel 100, the orthographic projection of at least one of the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3 onto the substrate 1 does not overlap with the orthographic projection of the conductive structure within the second conductive layer 22 onto the substrate 1. Please continue reading. Figure 13 and Figure 15 and combined Figure 7 and Figure 8 Since the orthographic projection of the first pixel opening K1 onto the substrate 1 and the orthographic projection of the first electrode 311 in the first color light-emitting device S11 onto the substrate 1 are at least partially overlapped, when the orthographic projection of the first pixel opening K1 onto the substrate 1 and the orthographic projection of the conductive structure in the second conductive layer 22 onto the substrate 1 do not overlap, in the orthographic projection onto the substrate 1, the portion of the first electrode 311 that overlaps with the first pixel opening K1 (i.e., the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11) does not overlap with the conductive structure in the second conductive layer 22. This avoids the influence of the conductive structure in the second conductive layer 22 on the flatness of the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11, which is beneficial to improving the flatness of the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11, and thus beneficial to improving the light emission uniformity of the first color light-emitting device S11, thereby improving the display effect of the display panel 100.

[0284] Please continue reading. Figure 13 and Figure 14 and combined Figure 7 and Figure 8 Since the orthographic projection of the second pixel opening K2 onto the substrate 1 and the orthographic projection of the first electrode 311 in the second color light-emitting device S12 onto the substrate 1 are at least partially overlapped, when the orthographic projection of the second pixel opening K2 onto the substrate 1 and the orthographic projection of the conductive structure in the second conductive layer 22 onto the substrate 1 do not overlap, in the orthographic projection onto the substrate 1, the portion of the first electrode 311 that overlaps with the second pixel opening K2 (i.e., the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12) does not overlap with the conductive structure in the second conductive layer 22. This avoids the influence of the conductive structure in the second conductive layer 22 on the flatness of the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12, which is beneficial to improving the flatness of the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12, and thus beneficial to improving the light emission uniformity of the second color light-emitting device S12, thereby improving the display effect of the display panel 100.

[0285] Please continue reading. Figure 13 and Figure 14 and combined Figure 7 and Figure 8Since the orthographic projection of the third pixel opening K3 onto the substrate 1 and the orthographic projection of the first electrode 311 in the third color light-emitting device S13 onto the substrate 1 are at least partially overlapped, when the orthographic projection of the third pixel opening K3 onto the substrate 1 and the orthographic projection of the conductive structure in the second conductive layer 22 onto the substrate 1 do not overlap, in the orthographic projection onto the substrate 1, the portion of the first electrode 311 that overlaps with the third pixel opening K3 (i.e., the actual effective area of ​​the first electrode 311 in the third color light-emitting device S13) does not overlap with the conductive structure in the second conductive layer 22. This avoids the influence of the conductive structure in the second conductive layer 22 on the flatness of the actual effective area of ​​the first electrode 311 in the third color light-emitting device S13, which is beneficial to improving the flatness of the actual effective area of ​​the first electrode 311 in the third color light-emitting device S13, thereby improving the light emission uniformity of the third color light-emitting device S13, and thus improving the display effect of the display panel 100.

[0286] For example, please continue reading Figure 15 and combined Figure 7 The orthographic projection of one of the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3 in the pixel definition layer PDL onto the substrate 1 can be non-overlapping with the orthographic projection of the conductive structure in the second conductive layer 22 onto the substrate 1.

[0287] Alternatively, please continue reading Figure 14 and combined Figure 7 The orthographic projection of two of the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3 in the pixel definition layer PDL onto the substrate 1 can be non-overlapping with the orthographic projection of the conductive structure in the second conductive layer 22 onto the substrate 1.

[0288] Alternatively, please continue reading Figure 13 and combined Figure 7 The orthographic projections of the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3 within the pixel definition layer PDL onto the substrate 1 can all be non-overlapping with the orthographic projections of the conductive structure within the second conductive layer 22 onto the substrate 1.

[0289] For example, please continue reading Figure 13 , Figure 14 and Figure 15 and combined Figure 7 When the second conductive layer 22 includes the first voltage signal line V1, the orthogonal projection of at least one of the first pixel opening K1, the second pixel opening K2 and the third pixel opening K3 onto the substrate 1 can be non-overlapping with the orthogonal projection of the first voltage signal line V1 onto the substrate 1.

[0290] For example, please continue reading Figure 13 , Figure 14 and Figure 15 and combined Figure 7 When the second conductive layer 22 includes the second fan-out line F2, the orthographic projection of at least one of the first pixel opening K1, the second pixel opening K2 and the third pixel opening K3 onto the substrate 1 can be non-overlapping with the orthographic projection of the second fan-out line F2 onto the substrate 1.

[0291] In other embodiments, please continue to refer to Figure 10 , Figure 11 and Figure 12 The second conductive layer 22 may include a conductive pattern 221.

[0292] like Figure 16 As shown, and in combination Figure 14 , Figure 15 and Figure 7 , Figure 16 This is a plan view of a partial region of the second conductive layer 22 within the driving layer 2 and the pixel definition layer PDL within the light-emitting device layer 3 according to some embodiments. When the light-emitting device layer 3 includes the pixel definition layer PDL, and the pixel definition layer PDL includes a first pixel opening K1, a second pixel opening K2, and a third pixel opening K3, the orthogonal projection of at least one of the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3 onto the substrate 1 can be located within the boundary range of the orthogonal projection of the conductive pattern 221 onto the substrate 1.

[0293] In the aforementioned display panel 100, the orthographic projection of at least one of the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3 within the pixel definition layer PDL onto the substrate 1 lies within the boundary range of the orthographic projection of the conductive pattern 221 onto the substrate 1. Please continue reading. Figure 14 and Figure 16 and combined Figure 7 and Figure 8Since the orthographic projection of the first pixel opening K1 onto the substrate 1 and the orthographic projection of the first electrode 311 in the first color light-emitting device S11 onto the substrate 1 are at least partially overlapped, when the orthographic projection of the first pixel opening K1 onto the substrate 1 is within the boundary range of the orthographic projection of the conductive pattern 221 onto the substrate 1, the portion of the first electrode 311 that overlaps with the first pixel opening K1 in the orthographic projection onto the substrate 1 (i.e., the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11) is within the boundary range of the orthographic projection of the conductive pattern 221 onto the substrate 1. This allows the conductive pattern 221 to support the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11 and provide full support for the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11. This is beneficial to improving the flatness of the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11, thereby improving the light emission uniformity of the first color light-emitting device S11, and thus improving the display effect of the display panel 100.

[0294] Please continue reading. Figure 15 and Figure 16 and combined Figure 7 and Figure 8 Since the orthographic projection of the second pixel opening K2 onto the substrate 1 and the orthographic projection of the first electrode 311 in the second color light-emitting device S12 onto the substrate 1 are at least partially overlapped, when the orthographic projection of the second pixel opening K2 onto the substrate 1 is within the boundary range of the orthographic projection of the conductive pattern 221 onto the substrate 1, the portion of the first electrode 311 that overlaps with the second pixel opening K2 (i.e., the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12) in the orthographic projection onto the substrate 1 is within the boundary range of the orthographic projection of the conductive pattern 221 onto the substrate 1. This allows the conductive pattern 221 to support the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12 and provide full support for the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12. This is beneficial to improving the flatness of the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12, thereby improving the light emission uniformity of the second color light-emitting device S12, and thus improving the display effect of the display panel 100.

[0295] Please continue reading. Figure 15 and Figure 16 and combined Figure 7 and Figure 8Since the orthographic projection of the third pixel opening K3 onto the substrate 1 and the orthographic projection of the first electrode 311 in the third color light-emitting device S13 onto the substrate 1 are at least partially overlapped, when the orthographic projection of the third pixel opening K3 onto the substrate 1 is within the boundary range of the orthographic projection of the conductive pattern 221 onto the substrate 1, the portion of the first electrode 311 that overlaps with the third pixel opening K3 in the orthographic projection onto the substrate 1 (i.e., the actual effective area of ​​the first electrode 311 in the third color light-emitting device S13) is within the boundary range of the orthographic projection of the conductive pattern 221 onto the substrate 1. This allows the conductive pattern 221 to support the actual effective area of ​​the first electrode 311 in the third color light-emitting device S13 and provide full support for the actual effective area of ​​the first electrode 311 in the third color light-emitting device S13. This is beneficial to improving the flatness of the actual effective area of ​​the first electrode 311 in the third color light-emitting device S13, thereby improving the light emission uniformity of the third color light-emitting device S13, and thus improving the display effect of the display panel 100.

[0296] For example, please continue reading Figure 14 and Figure 16 and combined Figure 7 The conductive pattern 221 within the second conductive layer 22 may include the first conductive pattern 2211. The orthographic projection of the first pixel opening K1 onto the substrate 1 may be located within the boundary range of the orthographic projection of the first conductive pattern 2211 onto the substrate 1.

[0297] For example, please continue reading Figure 15 and Figure 16 and combined Figure 7 The conductive pattern 221 within the second conductive layer 22 may include the second conductive pattern 2212.

[0298] The orthographic projection of the second pixel opening K2 onto the substrate 1 can be located within the boundary range of the orthographic projection of the second conductive pattern 2212 onto the substrate 1. And / or, the orthographic projection of the third pixel opening K3 onto the substrate 1 can be located within the boundary range of the orthographic projection of the second conductive pattern 2212 onto the substrate 1.

[0299] For example, please continue reading Figure 14 and Figure 16 When the second conductive layer 22 includes a first conductive pattern 2211 and a first voltage signal line V1, the first conductive pattern 2211 can be connected to the first voltage signal line V1.

[0300] In the aforementioned display panel 100, the first conductive pattern 2211 in the second conductive layer 22 is connected to the first voltage signal line V1, so that the first conductive pattern 2211 can also be used to transmit the first voltage signal, which is beneficial to improving the transmission efficiency and stability of the first voltage signal, thereby improving the stability of the display panel 100 and thus improving the display effect of the display panel 100.

[0301] For example, please continue reading Figure 14 and Figure 16 The second conductive layer 22 may include a plurality of first conductive patterns 2211. A first voltage signal line V1 may be connected to a plurality of first conductive patterns 2211.

[0302] When the first voltage signal line V1 extends along a third direction X, multiple first conductive patterns 2211 connected to the same first voltage signal line V1 can be located on the same side of the first voltage signal line V1 along the second direction Y.

[0303] For example, please continue reading Figure 15 and Figure 16 When the second conductive layer 22 includes a second conductive pattern 2212 and a first voltage signal line V1, the second conductive pattern 2212 can be connected to the first voltage signal line V1.

[0304] In the aforementioned display panel 100, the second conductive pattern 2212 within the second conductive layer 22 is connected to the first voltage signal line V1, enabling the second conductive pattern 2212 to also be used to transmit the first voltage signal. This is beneficial for improving the transmission efficiency and stability of the first voltage signal, thereby improving the stability of the display panel 100 and ultimately enhancing the display effect of the display panel 100.

[0305] For example, please continue reading Figure 15 and Figure 16 The second conductive layer 22 may include a plurality of second conductive patterns 2212. A first voltage signal line V1 may be connected to a plurality of second conductive patterns 2212.

[0306] When the first voltage signal line V1 extends along a third direction X, multiple second conductive patterns 2212 connected to the same first voltage signal line V1 can be located on the same side of the first voltage signal line V1 along the second direction Y.

[0307] For example, please continue reading Figure 16When the second conductive layer 22 includes a first conductive pattern 2211, a second conductive pattern 2212 and a first voltage signal line V1, and both the first conductive pattern 2211 and the second conductive pattern 2212 are connected to the first voltage signal line V1, the first conductive pattern 2211 and the second conductive pattern 2212 connected to the same first voltage signal line V1 can be located on opposite sides of the first voltage signal line V1 along the second direction Y.

[0308] For example, please continue reading Figure 16 The second conductive layer 22 may include a plurality of first conductive patterns 2211 and a plurality of second conductive patterns 2212. The plurality of first conductive patterns 2211 may be arranged at intervals along a third direction X, and the plurality of second conductive patterns 2212 may also be arranged at intervals along a third direction X. Along the second direction Y, the first conductive pattern 2211 may correspond to the gap region between two adjacent second conductive patterns 2212, and the second conductive pattern 2212 may correspond to the gap region between two adjacent first conductive patterns 2211.

[0309] For example, please continue reading Figure 14 , Figure 15 and Figure 16 and combined Figure 7 The distance d1 between the boundary of the orthographic projection of at least one of the first pixel opening K1, the second pixel opening K2 and the third pixel opening K3 onto the substrate 1 and the boundary of the orthographic projection of the conductive pattern 221 onto the substrate 1 can be less than or equal to 9 μm.

[0310] For example, please continue reading Figure 14 , Figure 15 and Figure 16 and combined Figure 7 The distance d1 between the boundary of the orthographic projection of at least one of the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3 onto the substrate 1 and the boundary of the orthographic projection of the conductive pattern 221 onto the substrate 1 can be 0, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, or 9μm, etc.

[0311] Please continue reading. Figure 14 and Figure 16 and combined Figure 7 In the case where the conductive pattern 221 in the second conductive layer 22 includes the first conductive pattern 2211, and the orthographic projection of the first pixel opening K1 onto the substrate 1 is located within the boundary range of the orthographic projection of the first conductive pattern 2211 onto the substrate 1, the distance d1 between the boundary of the orthographic projection of the first pixel opening K1 onto the substrate 1 and the boundary of the orthographic projection of the first conductive pattern 2211 onto the substrate 1 can be less than or equal to 9 μm.

[0312] Please continue reading. Figure 15 and Figure 16 and combined Figure 7 In the case that the conductive pattern 221 in the second conductive layer 22 includes the second conductive pattern 2212, and the orthographic projection of the second pixel opening K2 onto the substrate 1 is located within the boundary range of the orthographic projection of the second conductive pattern 2212 onto the substrate 1, the spacing d1 between the boundary of the orthographic projection of the second pixel opening K2 onto the substrate 1 and the boundary of the orthographic projection of the second conductive pattern 2212 onto the substrate 1 can be less than or equal to 9 μm.

[0313] Please continue reading. Figure 15 and Figure 16 and combined Figure 7 In the case where the conductive pattern 221 in the second conductive layer 22 includes the second conductive pattern 2212, and the orthographic projection of the third pixel opening K3 onto the substrate 1 is located within the boundary range of the orthographic projection of the second conductive pattern 2212 onto the substrate 1, the spacing d1 between the boundary of the orthographic projection of the third pixel opening K3 onto the substrate 1 and the boundary of the orthographic projection of the second conductive pattern 2212 onto the substrate 1 can be less than or equal to 9 μm.

[0314] In some embodiments, such as Figure 17 As shown, Figure 17 This is a cross-sectional view of a partial region of the second conductive layer 22 and the second insulating layer 52 within the driving layer 2, and the first electrode layer 31 within the light-emitting device layer 3, according to some embodiments. In cases where the driving layer 2 includes the second conductive layer 22 and the light-emitting device layer 3 includes the first electrode layer 31, the driving layer 2 may further include the second insulating layer 52. The second insulating layer 52 is located between the second conductive layer 22 and the first electrode layer 31.

[0315] In the aforementioned display panel 100, the second insulating layer 52 is located between the second conductive layer 22 and the first electrode layer 31. The second insulating layer 52 can serve both as insulation and as a flat interface, which helps to improve the flatness of the first electrode 311 within the first electrode layer 31, thereby improving the light emission uniformity of the light-emitting device S1 and thus enhancing the display effect of the display panel 100.

[0316] For example, please continue reading Figure 17 The second insulating layer 52 may include a first insulating layer 521 and a second insulating layer 522. The first insulating layer 521 and the second insulating layer 522 may be stacked along the first direction Z.

[0317] In some embodiments, such as Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 As shown, Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 These are all plan views of a partial region of the first conductive layer 21 within the driving layer 2 according to some embodiments. The driving layer 2 may include the first conductive layer 21.

[0318] For example, please continue reading Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 The first conductive layer 21 may include a second voltage signal line V2. The second voltage signal line V2 may extend along a second direction Y, which is perpendicular to the first direction Z.

[0319] For example, please continue reading Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 The first conductive layer 21 may include multiple second voltage signal lines V2. The multiple second voltage signal lines V2 may be arranged at intervals along a third direction X.

[0320] For example, please continue reading Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 The data signal line D1 within the display panel 100 can be located within the first conductive layer 21. That is, the first conductive layer 21 can include the data signal line D1. The data signal line D1 can extend along the second direction Y.

[0321] For example, please continue reading Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 The first conductive layer 21 may include multiple data signal lines D1. The multiple data signal lines D1 may be arranged at intervals along a third direction X.

[0322] For example, please continue reading Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 When the first conductive layer 21 includes a data signal line D1 and a second voltage signal line V2, and both the data signal line D1 and the second voltage signal line V2 extend along the second direction Y, the data signal line D1 can be located on the side of the second voltage signal line V2 along the third direction X.

[0323] For example, please continue reading Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 When the first conductive layer 21 includes multiple second voltage signal lines V2, and the multiple second voltage signal lines V2 are arranged at intervals along the third direction X, the data signal line D1 can be located between two adjacent second voltage signal lines V2.

[0324] It should be noted that, Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 The illustrated embodiment uses the example of two data signal lines D1 arranged between two adjacent second voltage signal lines V2 to illustrate some embodiments of this disclosure. However, the number of data signal lines D1 between two adjacent second voltage signal lines V2 in this disclosure is not limited to this, and the number of data signal lines D1 between two adjacent second voltage signal lines V2 can be set according to actual needs.

[0325] For example, please continue reading Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 The first conductive layer 21 may include a first fan-out line F1. The first fan-out line F1 may extend along the second direction Y.

[0326] Please continue reading. Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 When the first conductive layer 21 further includes a second voltage signal line V2, and the second voltage signal line V2 extends along the second direction Y, the first fan-out line F1 can be located on the side of the second voltage signal line V2 along the third direction X.

[0327] For example, please continue reading Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 When the first conductive layer 21 includes multiple second voltage signal lines V2, and the multiple second voltage signal lines V2 are arranged at intervals along the third direction X, the first fan-out line F1 can be located between two adjacent second voltage signal lines V2.

[0328] Please continue reading. Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 In the case that the first conductive layer 21 also includes a second voltage signal line V2 and a data signal line D1, and both the second voltage signal line V2 and the data signal line D1 extend along the second direction Y, the second voltage signal line V2, the data signal line D1 and the first fan-out line F1 can be arranged at intervals along the third direction X.

[0329] For example, please continue reading Figure 18 , Figure 19 , Figure 20 , Figure 22 , Figure 23 and Figure 24 The data signal line D1 and the first fan-out line F1 can be located on opposite sides of the second voltage signal line V2 along the third direction X.

[0330] For example, please continue reading Figure 21 Along the third direction X, two data signal lines D1 can be set between two adjacent second voltage signal lines V2, and the first fan-out line F1 can be located between the two data signal lines D1.

[0331] For example, such as Figure 25 and Figure 26 As shown, and in combination Figure 7 , Figure 25 and Figure 26 These are plan views of partial regions of the first conductive layer 21 and the second conductive layer 22 within the driving layer 2 according to some embodiments. When the driving layer 2 further includes a second conductive layer 22, the second conductive layer 22 may be located on the side of the first conductive layer 21 away from the substrate 1.

[0332] Please continue reading. Figure 25 and Figure 26In the second conductive layer 22 within the driving layer 2, there is a first voltage signal line V1 and a second voltage signal line V2. When the first voltage signal line V1 extends along a third direction X and the second voltage signal line V2 extends along a second direction Y, the first voltage signal line V1 can be connected to the second voltage signal line V2.

[0333] In the aforementioned display panel 100, the first voltage signal line V1 is connected to the second voltage signal line V2, such that both the first voltage signal line V1 and the second voltage signal line V2 are used to transmit the first voltage signal. Since the first voltage signal line V1 extends along a third direction X, and the second voltage signal line V2 extends along a second direction Y, and the third direction X and the second direction Y intersect, the first voltage signal line V1 extending along the third direction X and the second voltage signal line V2 extending along the second direction Y can together form a mesh structure. This helps reduce the loss of the first voltage signal during transmission, thereby reducing the voltage drop difference between the first voltage signals in different areas within the display panel 100, and ultimately improving the display effect of the display panel 100.

[0334] For example, such as Figure 27 As shown, and in combination Figure 25 and Figure 26 , Figure 27 This is a plan view of a display panel 100 according to some embodiments. In the case where the first conductive layer 21 in the driving layer 2 includes a first fan-out line F1 and a data signal line D1, and the second conductive layer 22 includes a second fan-out line F2, the second fan-out line F2 can be connected to the first fan-out line F1 and the data signal line D1 respectively.

[0335] For example, please continue reading Figure 25 , Figure 26 and Figure 27 The second outgoing line F2 may include a first sub-line F21. The first sub-line F21 may be connected to the first outgoing line F1 and the data signal line D1 respectively.

[0336] In the aforementioned display panel 100, the second fan-out line F2 can be simultaneously connected to both the first fan-out line F1 and the data signal line D1. The first fan-out line F1 can be connected to the driver chip within the display device 1000, allowing the driver chip to transmit data signals to the data signal line D1 via the first fan-out line F1 and the second fan-out line F2. This configuration can be referred to as Fanout In AA (FIAA) or Fanout In Panel (FIP), which helps reduce the size of the peripheral area AN of the display panel 100, thereby facilitating a narrow bezel design for the display panel 100.

[0337] Please continue reading. Figure 1 and combined Figure 25and Figure 26 When the display device 1000 includes an optical element 200 (e.g., a camera), an opening for mounting the optical element 200 may be provided in the display panel 100. The first fan-out cable F1 and the second fan-out cable F2 may need to be wound around the opening. This arrangement can be called HIP (Hole Fanout in Panel).

[0338] Alternatively, please continue reading Figure 25 and Figure 26 and combined Figure 7 In the case that the first conductive layer 21 in the driving layer 2 includes the first fan-out line F1, the second conductive layer 22 includes the second fan-out line F2, and the second electrode layer 33 in the light-emitting device layer 3 includes the third voltage signal line V3, the second fan-out line F2 can be connected to the first fan-out line F1 and the third voltage signal line V3 respectively.

[0339] For example, please continue reading Figure 25 and Figure 26 The second sector outgoing line F2 may include a second sub-line F22. The second sub-line F22 may be connected to the first sector outgoing line F1 and the third voltage signal line V3 respectively.

[0340] In the aforementioned display panel 100, the second output line F2 is connected to both the first output line F1 and the third voltage signal line V3. The first output line F1 can be connected to the driver chip within the display device 1000, allowing the driver chip to transmit a second voltage signal to the third voltage signal line V3 via the first output line F1 and the second output line F2. This configuration can be referred to as SIP (VSS in Panel).

[0341] In some embodiments, please continue reading Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 When the driving layer 2 includes a first conductive layer 21, the first conductive layer 21 may include a first signal line M1. The first signal line M1 may extend along the second direction Y.

[0342] When the first conductive layer 21 further includes a second voltage signal line V2, and the second voltage signal line V2 extends along the second direction Y, the second voltage signal line V2 may be located on the side of the first signal line M1 along the third direction X.

[0343] like Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32 , Figure 33 and Figure 34 As shown, and in combination Figure 7 , Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32 , Figure 33 and Figure 34 These are partial plan views of the first conductive layer 21 in the driving layer 2 and the pixel definition layer PDL in the light-emitting device layer 3 according to some embodiments. When the light-emitting device layer 3 includes the pixel definition layer PDL, and the pixel definition layer PDL includes a first pixel opening K1, a second pixel opening K2, and a third pixel opening K3, the orthogonal projection of at least one of the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3 onto the substrate 1 can at least partially overlap with the orthogonal projection of the first signal line M1 onto the substrate 1, and can also at least partially overlap with the orthogonal projection of the second voltage signal line V2 onto the substrate 1.

[0344] Please continue reading. Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32 , Figure 33 and Figure 34 and combined Figure 7 and Figure 8In the aforementioned display panel 100, at least one of the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3 has its orthographic projection onto the substrate 1 overlapping with both the orthographic projection of the first signal line M1 onto the substrate 1 and the orthographic projection of the second voltage signal line V2 onto the substrate 1. Since the orthographic projection of the first pixel opening K1 onto the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 311 in the first color light-emitting device S11 onto the substrate 1, the orthographic projection of the second pixel opening K2 onto the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 311 in the second color light-emitting device S12 onto the substrate 1, and the orthographic projection of the third pixel opening K3 onto the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 311 in the third color light-emitting device S13 onto the substrate 1, when the orthographic projection of at least one of the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3 onto the substrate 1 overlaps with both the orthographic projection of the first signal line M1 onto the substrate 1 and the orthographic projection of the second voltage signal line V2 onto the substrate 1, in the orthographic projection onto the substrate 1, the portion of the first electrode 311 that overlaps with the first pixel opening K1 (i.e., the first electrode 311 in the first color light-emitting device S11) will overlap with the first pixel opening K1. At least one of the following: the actual effective area of ​​the first electrode 311, the portion of the first electrode 311 overlapping with the second pixel opening K2 (i.e., the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12), and the portion of the first electrode 311 overlapping with the third pixel opening K3 (i.e., the actual effective area of ​​the first electrode 311 within the third color light-emitting device S13), overlaps with both the first signal line M1 and the second voltage signal line V2. This allows the first signal line M1 and the second voltage signal line V2 to support the actual effective area of ​​the first electrode 311 from different positions, which helps to improve the flatness of the actual effective area of ​​the first electrode 311. This, in turn, helps to improve the light emission uniformity of at least one of the first color light-emitting device S11, the second color light-emitting device S12, and the third color light-emitting device S13, thereby improving the display effect of the display panel 100.

[0345] For example, please continue reading Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 The first signal line M1 can be the first sector output line F1.

[0346] For example, please continue reading Figure 18 , Figure 19 , Figure 20 , Figure 22 , Figure 23 and Figure 24 The first signal line M1 can be the data signal line D1.

[0347] In some embodiments, please continue reading Figure 28 , Figure 29 and Figure 30 and combined Figure 7 In a driving layer 2 including a first conductive layer 21, a light-emitting device layer 3 including a pixel definition layer PDL, a pixel definition layer PDL including a first pixel opening K1, and a first conductive layer 21 including a first signal line M1 and a second voltage signal line V2, where the second voltage signal line V2 is located on one side of the first signal line M1 along a third direction X, and the first signal line M1 is a first fan-out line F1, the orthogonal projection of the first fan-out line F1 onto the substrate 1 can at least partially overlap with the orthogonal projection of the first pixel opening K1 onto the substrate 1. Similarly, the orthogonal projection of the second voltage signal line V2 onto the substrate 1 can at least partially overlap with the orthogonal projection of the first pixel opening K1 onto the substrate 1.

[0348] In other words, the orthographic projection of the first pixel opening K1 onto the substrate 1 can overlap with the orthographic projection of the first fan-out line F1 onto the substrate 1, and can also overlap with the orthographic projection of the second voltage signal line V2 onto the substrate 1.

[0349] Please continue reading. Figure 28 , Figure 29 and Figure 30 and combined Figure 7 and Figure 8 In the aforementioned display panel 100, the orthographic projection of the first pixel opening K1 onto the substrate 1 overlaps with both the orthographic projection of the first fan-out line F1 onto the substrate 1 and the orthographic projection of the second voltage signal line V2 onto the substrate 1. Since the orthographic projection of the first pixel opening K1 onto the substrate 1 at least partially coincides with the orthographic projection of the first electrode 311 within the first color light-emitting device S11 onto the substrate 1, the portion of the first electrode 311 overlapping with the first pixel opening K1 (i.e., the actual effective area of ​​the first electrode 311 within the first color light-emitting device S11) overlaps with both the first fan-out line F1 and the second voltage signal line V2. This allows the first fan-out line F1 and the second voltage signal line V2 to support the actual effective area of ​​the first electrode 311 within the first color light-emitting device S11 from different positions, which helps improve the flatness of the actual effective area of ​​the first electrode 311 within the first color light-emitting device S11, thereby improving the light emission uniformity of the first color light-emitting device S11 and ultimately enhancing the display effect of the display panel 100.

[0350] Please continue reading. Figure 28 , Figure 29 and Figure 30 and combined Figure 7 and Figure 8Especially when the first conductive layer 21 includes multiple second voltage signal lines V2, the multiple second voltage signal lines V2 are arranged at intervals along the third direction X, and the first fan-out line F1 is located between two adjacent second voltage signal lines V2, the orthogonal projection of the first pixel opening K1 onto the substrate 1 can overlap with the orthogonal projection of the first fan-out line F1 onto the substrate 1, and can also overlap with the orthogonal projection of the two second voltage signal lines V2 onto the substrate 1. This allows the first fan-out line F1 and the two second voltage signal lines V2 to support the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11 from different positions. This is beneficial to further improve the flatness of the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11, and thus to further improve the light emission uniformity of the first color light-emitting device S11, thereby further improving the display effect of the display panel 100.

[0351] For example, please continue reading Figure 28 , Figure 29 and Figure 30 and combined Figure 7 The first pixel opening K1 can be symmetrically arranged with respect to the first virtual line N1 extending along the second direction Y. The orthographic projection of the first virtual line N1 onto the substrate 1 can be located within the boundary range of the orthographic projection of the first fan-out line F1 onto the substrate 1.

[0352] Please continue reading. Figure 28 , Figure 29 and Figure 30 and combined Figure 7 and Figure 8 In the aforementioned display panel 100, the first pixel opening K1 is symmetrically arranged with respect to the first virtual line N1 extending along the second direction Y, and the orthographic projection of the first virtual line N1 onto the substrate 1 is located within the boundary range of the orthographic projection of the first fan-out line F1 onto the substrate 1. When the first fan-out line F1 supports the actual effective area of ​​the first electrode 311 within the first color light-emitting device S11, the actual effective area of ​​the first electrode 311 within the first color light-emitting device S11 can be approximately symmetrically distributed with respect to the first fan-out line F1. This is beneficial to further improve the flatness of the actual effective area of ​​the first electrode 311 within the first color light-emitting device S11, and thus to further improve the light emission uniformity of the first color light-emitting device S11, thereby further improving the display effect of the display panel 100.

[0353] For example, please continue reading Figure 28 , Figure 29 and Figure 30 When the first fan-out line F1 is located between two adjacent second voltage signal lines V2, the two adjacent second voltage signal lines V2 can be symmetrically arranged relative to the first fan-out line F1.

[0354] Please continue reading. Figure 28 , Figure 29 and Figure 30 and combined Figure 8 In the aforementioned display panel 100, two adjacent second voltage signal lines V2 are symmetrically arranged relative to the first fan-out line F1. When the first fan-out line F1 and the two second voltage signal lines V2 support the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11 from different positions, the two second voltage signal lines V2 can be symmetrically distributed below the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11. This is beneficial to further improve the flatness of the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11, and thus further improve the light emission uniformity of the first color light-emitting device S11, thereby further improving the display effect of the display panel 100.

[0355] For example, please continue reading Figure 19 and Figure 20 The second voltage signal line V2 may include a main body V23 and a first extension V21. The first extension V21 is connected to the main body V23. Along the third direction X, the first extension V21 may be located between the main body V23 and the first fan-out line F1.

[0356] Please continue reading. Figure 19 and Figure 20 The main body V23 can extend along the second direction Y.

[0357] Please continue reading. Figure 19 The first extension V21 may include a first sub-part V211, which may extend along the second direction Y.

[0358] Alternatively, please continue reading Figure 20 The first extension V21 may include a plurality of first sub-parts V211, which may extend along the second direction Y, and the plurality of first sub-parts V211 may be arranged at intervals along the third direction X and connected in sequence.

[0359] Please continue reading. Figure 29 and Figure 30 The orthographic projection of the first pixel opening K1 onto the substrate 1 can overlap with the orthographic projection of the first sub-part V211 onto the substrate 1.

[0360] Please continue reading. Figure 29 and Figure 30 and combined Figure 7 and Figure 8In the aforementioned display panel 100, the orthographic projection of the first pixel opening K1 onto the substrate 1 and the orthographic projection of the first sub-part V211 within the first extension V21 onto the substrate 1 overlap, such that the first fan-out line F1 and the first sub-part V211 within the first extension V21 can support the actual effective area of ​​the first electrode 311 within the first color light-emitting device S11 from different positions. This is beneficial for improving the flatness of the actual effective area of ​​the first electrode 311 within the first color light-emitting device S11, thereby helping to suppress the color separation phenomenon of the first color light-emitting device S11 and improve the light emission uniformity of the first color light-emitting device S11, thus improving the display effect of the display panel 100.

[0361] Please continue reading. Figure 30 and combined Figure 7 and Figure 8 Especially when the first extension V21 includes a plurality of first sub-parts V211 and the plurality of first sub-parts V211 are arranged at intervals along the third direction X, the orthogonal projection of the first pixel opening K1 onto the substrate 1 can overlap with the orthogonal projection of the plurality of first sub-parts V211 into the substrate 1. This allows the first fan-out line F1 and the plurality of first sub-parts V211 into the first extension V21 to support the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11 from different positions. This is beneficial to further improve the flatness of the actual effective area of ​​the first electrode 311 in the first color light-emitting device S11, and thus to further improve the light emission uniformity of the first color light-emitting device S11, thereby further improving the display effect of the display panel 100.

[0362] For example, please continue reading Figure 19 and Figure 20 When the first fan-out line F1 is located between two adjacent second voltage signal lines V2, the first extension V21 within the two adjacent second voltage signal lines V2 can be symmetrically arranged relative to the first fan-out line F1.

[0363] Please continue reading. Figure 29 and Figure 30 and combined Figure 8In the aforementioned display panel 100, the first extension V21 within two adjacent second voltage signal lines V2 is symmetrically arranged relative to the first fan-out line F1. On the one hand, when the first fan-out line F1 and the first extension V21 within the two second voltage signal lines V2 support the actual effective area of ​​the first electrode 311 within the first color light-emitting device S11 from different positions, the first extension V21 within the two second voltage signal lines V2 can be symmetrically distributed below the actual effective area of ​​the first electrode 311 within the first color light-emitting device S11. This is beneficial to further improve the flatness of the actual effective area of ​​the first electrode 311 within the first color light-emitting device S11, thereby further suppressing the color separation phenomenon of the first color light-emitting device S11 and further improving the light emission uniformity of the first color light-emitting device S11, thus further improving the display effect of the display panel 100.

[0364] On the other hand, the signal line arrangement in the first conductive layer 21 can be optimized, thereby saving wiring space in the first conductive layer 21, which is beneficial to improving the PPI (Pixels Per Inch) of the display panel 100.

[0365] For example, please continue reading Figure 19 and Figure 20 The dimension h1 of the first outgoing line F1 along the third direction X can be equal to the dimension h2 of the first sub-part V211 within the first extension V21 along the third direction X.

[0366] For example, please continue reading Figure 19 and Figure 20 The dimension h1 of the first outgoing line F1 along the third direction X can be greater than or equal to 1.9μm and less than or equal to 2.8μm.

[0367] For example, please continue reading Figure 19 and Figure 20 The size h1 of the first outgoing line F1 along the third direction X can be 1.9μm, 2μm, 2.1μm, 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm, 2.7μm or 2.8μm, etc.

[0368] For example, please continue reading Figure 19 and Figure 20 The dimension h2 of the first sub-part V211 within the first extension V21 along the third direction X can be greater than or equal to 1.9 μm and less than or equal to 2.8 μm.

[0369] For example, please continue reading Figure 19 and Figure 20The size h2 of the first sub-part V211 within the first extension V21 along the third direction X can be 1.9μm, 2μm, 2.1μm, 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm, 2.7μm or 2.8μm, etc.

[0370] For example, please continue reading Figure 20 When the first extension V21 includes a plurality of first sub-parts V211, the distance d2 between the first fan-out line F1 and the first extension V21 along the third direction X can be equal to the distance d3 between two adjacent first sub-parts V211 along the third direction X.

[0371] For example, please continue reading Figure 20 The distance d2 between the first fan-out line F1 and the first extension V21 along the third direction X can be greater than or equal to 2μm and less than or equal to 2.9μm.

[0372] For example, please continue reading Figure 20 The distance d2 between the first outgoing line F1 and the first extension V21 along the third direction X can be 2μm, 2.1μm, 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm, 2.7μm, 2.8μm or 2.9μm, etc.

[0373] For example, please continue reading Figure 20 When the first extension V21 includes a plurality of first sub-parts V211, the distance d3 between two adjacent first sub-parts V211 along the third direction X can be greater than or equal to 2 μm and less than or equal to 2.9 μm.

[0374] For example, please continue reading Figure 20 The distance d3 between two adjacent first sub-parts V211 along the third direction X can be 2μm, 2.1μm, 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm, 2.7μm, 2.8μm or 2.9μm, etc.

[0375] In other embodiments, please continue to refer to Figure 31 and combined Figure 7 and Figure 21 In the case where the driving layer 2 includes a first conductive layer 21, the light-emitting device layer 3 includes a pixel definition layer PDL, and the pixel definition layer PDL includes a first pixel opening K1, the first conductive layer 21 may include a third conductive pattern 211. The orthogonal projection of the first pixel opening K1 onto the substrate 1 may be located within the boundary range of the orthogonal projection of the third conductive pattern 211 onto the substrate 1.

[0376] Please continue reading. Figure 31 and combined Figure 7and Figure 8 In the aforementioned display panel 100, the orthographic projection of the first pixel opening K1 within the pixel definition layer PDL onto the substrate 1 is located within the boundary range of the orthographic projection of the third conductive pattern 211 onto the substrate 1. Since the orthographic projection of the first pixel opening K1 onto the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 311 within the first color light-emitting device S11 onto the substrate 1, the portion of the first electrode 311 overlapping with the first pixel opening K1 (i.e., the actual effective area of ​​the first electrode 311 within the first color light-emitting device S11) in the orthographic projection onto the substrate 1 is located within the boundary range of the orthographic projection of the third conductive pattern 211 onto the substrate 1. This allows the third conductive pattern 211 to support the actual effective area of ​​the first electrode 311 within the first color light-emitting device S11 and provide comprehensive support for it. This improves the flatness of the actual effective area of ​​the first electrode 311 within the first color light-emitting device S11, thereby improving the light emission uniformity of the first color light-emitting device S11 and ultimately enhancing the display effect of the display panel 100.

[0377] For example, please continue reading Figure 21 In the case that the first conductive layer 21 also includes a second voltage signal line V2, and the second voltage signal line V2 extends along the second direction Y, the third conductive pattern 211 can be located on the side of the second voltage signal line V2 along the third direction X, and connected to the second voltage signal line V2 to form an integral structure.

[0378] In the aforementioned display panel 100, the third conductive pattern 211 in the first conductive layer 21 is connected to the second voltage signal line V2, so that the third conductive pattern 211 can also be used to transmit the first voltage signal, which is beneficial to improving the transmission efficiency and stability of the first voltage signal, thereby improving the stability of the display panel 100 and thus improving the display effect of the display panel 100.

[0379] For example, please continue reading Figure 21 When the first conductive layer 21 includes multiple second voltage signal lines V2, and the multiple second voltage signal lines V2 are arranged at intervals along the third direction X, the third conductive pattern 211 can be located between two adjacent second voltage signal lines V2, and connected to the two second voltage signal lines V2 respectively, forming an integral structure.

[0380] In some embodiments, please continue reading Figure 31 and combined Figure 7 and Figure 21In a driving layer 2 including a first conductive layer 21, and a light-emitting device layer 3 including a pixel definition layer PDL, the pixel definition layer PDL including a second pixel opening K2, and the first conductive layer 21 including a first signal line M1 and a data signal line D1, wherein the first signal line M1 is a first fan-out line F1, and the first fan-out line F1 is located on the side of the data signal line D1 along the third direction X, the orthographic projection of the first fan-out line F1 onto the substrate 1 can at least partially overlap with the orthographic projection of the second pixel opening K2 onto the substrate 1. Similarly, the orthographic projection of the data signal line D1 onto the substrate 1 can also at least partially overlap with the orthographic projection of the second pixel opening K2 onto the substrate 1.

[0381] In other words, the orthographic projection of the second pixel opening K2 onto the substrate 1 can overlap with the orthographic projection of the first fan-out line F1 onto the substrate 1, and also with the orthographic projection of the data signal line D1 onto the substrate 1.

[0382] Please continue reading. Figure 31 and combined Figure 7 and Figure 8 In the aforementioned display panel 100, the orthographic projection of the second pixel opening K2 onto the substrate 1 overlaps with both the orthographic projection of the first fan-out line F1 onto the substrate 1 and the orthographic projection of the data signal line D1 onto the substrate 1. Since the orthographic projection of the second pixel opening K2 onto the substrate 1 and the orthographic projection of the first electrode 311 within the second color light-emitting device S12 onto the substrate 1 are at least partially coincident, the portion of the first electrode 311 overlapping with the second pixel opening K2 (i.e., the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12) overlaps with both the first fan-out line F1 and the data signal line D1 in the orthographic projection onto the substrate 1. This allows the first fan-out line F1 and the data signal line D1 to support the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12 from different positions, which helps improve the flatness of the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12, thereby improving the light emission uniformity of the second color light-emitting device S12 and ultimately enhancing the display effect of the display panel 100.

[0383] Please continue reading. Figure 31 and combined Figure 7 and Figure 8Especially when the first conductive layer 21 includes multiple data signal lines D1, which are spaced apart along the third direction X, and the first fan-out line F1 is located between two adjacent data signal lines D1, the orthogonal projection of the second pixel opening K2 onto the substrate 1 can overlap with the orthogonal projection of the first fan-out line F1 onto the substrate 1, as well as with the orthogonal projections of the two data signal lines D1 onto the substrate 1. This allows the first fan-out line F1 and the two data signal lines D1 to support the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12 from different positions. This is beneficial to further improve the flatness of the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12, thereby further improving the light emission uniformity of the second color light-emitting device S12, and thus further improving the display effect of the display panel 100.

[0384] For example, please continue reading Figure 31 and combined Figure 7 The second pixel opening K2 can be symmetrically arranged with respect to the second virtual line N2 extending along the second direction Y. The orthogonal projection of the second virtual line N2 onto the substrate 1 can be located within the boundary range of the orthogonal projection of the first fan-out line F1 onto the substrate 1.

[0385] Please continue reading. Figure 31 and combined Figure 7 and Figure 8 In the aforementioned display panel 100, the second pixel opening K2 is symmetrically arranged with respect to the second virtual line N2 extending along the second direction Y, and the orthogonal projection of the second virtual line N2 onto the substrate 1 is located within the boundary range of the orthogonal projection of the first fan-out line F1 onto the substrate 1. When the first fan-out line F1 supports the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12, the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12 can be approximately symmetrically distributed with respect to the first fan-out line F1. This is beneficial to further improve the flatness of the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12, and thus to further improve the light emission uniformity of the second color light-emitting device S12, thereby further improving the display effect of the display panel 100.

[0386] For example, please continue reading Figure 21 and Figure 31 When the first fan-out line F1 is located between two adjacent data signal lines D1, the two adjacent data signal lines D1 can be symmetrically arranged with respect to the first fan-out line F1.

[0387] Please continue reading. Figure 31 and combined Figure 8In the aforementioned display panel 100, two adjacent data signal lines D1 are symmetrically arranged relative to the first fan-out line F1. When the first fan-out line F1 and the two data signal lines D1 support the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12 from different positions, the two data signal lines D1 can be symmetrically distributed below the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12. This is beneficial to further improve the flatness of the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12, and thus further improve the light emission uniformity of the second color light-emitting device S12, thereby further improving the display effect of the display panel 100.

[0388] For example, please continue reading Figure 31 and combined Figure 7 In the case that the first conductive layer 21 also includes a second voltage signal line V2, and the second voltage signal line V2, the data signal line D1 and the first fan-out line F1 are arranged at intervals along the third direction X, the orthogonal projections of the second voltage signal line V2, the data signal line D1 and the first fan-out line F1 onto the substrate 1 can all at least partially overlap with the orthogonal projections of the second pixel opening K2 onto the substrate 1.

[0389] Please continue reading. Figure 31 and combined Figure 7 and Figure 8 In the aforementioned display panel 100, the orthographic projections of the second voltage signal line V2, the data signal line D1, and the first fan-out line F1 onto the substrate 1 all overlap with the orthographic projections of the second pixel opening K2 onto the substrate 1. Since the orthographic projection of the second pixel opening K2 onto the substrate 1 and the orthographic projection of the first electrode 311 in the second color light-emitting device S12 onto the substrate 1 are at least partially overlapped, in the orthographic projection onto the substrate 1, the portion of the first electrode 311 that overlaps with the second pixel opening K2 (i.e., the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12) overlaps with the second voltage signal line V2, the data signal line D1, and the first fan-out line F1, respectively. This allows the second voltage signal line V2, the data signal line D1, and the first fan-out line F1 to support the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12 from different positions. This is beneficial to further improve the flatness of the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12, and thus to further improve the light emission uniformity of the second color light-emitting device S12, thereby further improving the display effect of the display panel 100.

[0390] In other embodiments, please continue to refer to Figure 28 , Figure 29 , Figure 30 , Figure 32 , Figure 33 and Figure 34and combined Figure 7 In a driving layer 2 including a first conductive layer 21, and a light-emitting device layer 3 including a pixel definition layer PDL, the pixel definition layer PDL including a second pixel opening K2, and the first conductive layer 21 including a first signal line M1 and a second voltage signal line V2, where the second voltage signal line V2 is located on the side of the first signal line M1 along a third direction X, and the first signal line M1 is a data signal line D1, the orthogonal projection of the data signal line D1 onto the substrate 1 can at least partially overlap with the orthogonal projection of the second pixel opening K2 onto the substrate 1. Similarly, the orthogonal projection of the second voltage signal line V2 onto the substrate 1 can also at least partially overlap with the orthogonal projection of the second pixel opening K2 onto the substrate 1.

[0391] In other words, the orthographic projection of the second pixel opening K2 onto the substrate 1 can overlap with the orthographic projection of the data signal line D1 onto the substrate 1, and can also overlap with the orthographic projection of the second voltage signal line V2 onto the substrate 1.

[0392] Please continue reading. Figure 28 , Figure 29 , Figure 30 , Figure 32 , Figure 33 and Figure 34 and combined Figure 7 and Figure 8 In the aforementioned display panel 100, the orthographic projection of the second pixel opening K2 onto the substrate 1 overlaps with both the orthographic projection of the data signal line D1 onto the substrate 1 and the orthographic projection of the second voltage signal line V2 onto the substrate 1. Since the orthographic projection of the second pixel opening K2 onto the substrate 1 at least partially coincides with the orthographic projection of the first electrode 311 within the second color light-emitting device S12 onto the substrate 1, the portion of the first electrode 311 overlapping with the second pixel opening K2 (i.e., the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12) overlaps with both the data signal line D1 and the second voltage signal line V2 in the orthographic projection onto the substrate 1. This allows the data signal line D1 and the second voltage signal line V2 to support the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12 from different positions, which helps improve the flatness of the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12, thereby improving the light emission uniformity of the second color light-emitting device S12 and ultimately enhancing the display effect of the display panel 100.

[0393] Please continue reading. Figure 28 , Figure 29 , Figure 30 , Figure 32 , Figure 33 and Figure 34 and combined Figure 7 and Figure 8Especially when the first conductive layer 21 includes multiple second voltage signal lines V2, the multiple second voltage signal lines V2 are arranged at intervals along the third direction X, and the data signal line D1 is located between two adjacent second voltage signal lines V2, the orthogonal projection of the second pixel opening K2 onto the substrate 1 can overlap with the orthogonal projection of the data signal line D1 onto the substrate 1, and can also overlap with the orthogonal projection of the two second voltage signal lines V2 onto the substrate 1. This allows the data signal line D1 and the two second voltage signal lines V2 to support the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12 from different positions, which is beneficial to further improve the flatness of the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12, and thus further improve the light emission uniformity of the second color light-emitting device S12, thereby further improving the display effect of the display panel 100.

[0394] For example, please continue reading Figure 28 , Figure 29 , Figure 30 , Figure 32 , Figure 33 and Figure 34 and combined Figure 7 and Figure 8 Two data signal lines D1 can be provided between two adjacent second voltage signal lines V2, so that the orthographic projection of the second pixel opening K2 onto the substrate 1 can overlap with the orthographic projection of the two data signal lines D1 onto the substrate 1, and also with the orthographic projection of the two second voltage signal lines V2 onto the substrate 1. This allows the two data signal lines D1 and the two second voltage signal lines V2 to support the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12 from different positions, which helps to further improve the flatness of the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12, and further improves the light emission uniformity of the second color light-emitting device S12, thereby further improving the display effect of the display panel 100.

[0395] For example, please continue reading Figure 28 , Figure 29 , Figure 30 , Figure 32 , Figure 33 and Figure 34 The second virtual line N2 can extend along the second direction Y and can be located between the two data signal lines D1. The two data signal lines D1 can be symmetrically arranged with respect to the second virtual line N2.

[0396] Please continue reading. Figure 28 , Figure 29 , Figure 30 , Figure 32 , Figure 33 and Figure 34 and combined Figure 8 In the aforementioned display panel 100, two data signal lines D1 are symmetrically arranged relative to the second virtual line N2. When the two data signal lines D1 support the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12 from different positions, the two data signal lines D1 are symmetrically distributed below the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12. This helps to further improve the flatness of the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12, thereby further improving the light emission uniformity of the second color light-emitting device S12, and thus further improving the display effect of the display panel 100.

[0397] For example, please continue reading Figure 28 , Figure 29 , Figure 30 , Figure 32 , Figure 33 and Figure 34 The second virtual line N2 can extend along the second direction Y and can be located between the two data signal lines D1. The second pixel opening K2 can be symmetrically arranged with respect to the second virtual line N2.

[0398] Please continue reading. Figure 28 , Figure 29 , Figure 30 , Figure 32 , Figure 33 and Figure 34 and combined Figure 8 In the aforementioned display panel 100, the second pixel opening K2 is symmetrically arranged with respect to the second virtual line N2 extending along the second direction Y, and the second virtual line N2 is located between two data signal lines D1. When the two data signal lines D1 support the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12, the two data signal lines D1 located below the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12 can be relatively evenly distributed. This is beneficial to further improve the flatness of the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12, and thus to further improve the light emission uniformity of the second color light-emitting device S12, thereby further improving the display effect of the display panel 100.

[0399] For example, please continue reading Figure 22 , Figure 23 and Figure 24 The second voltage signal line V2 may include a main body V23 and a second extension V22. The second extension V22 is connected to the main body V23. Along the third direction X, the second extension V22 may be located between the main body V23 and the data signal line D1.

[0400] Please continue reading. Figure 22, Figure 23 and Figure 24 The main body V23 can extend along the second direction Y.

[0401] Please continue reading. Figure 22 and Figure 23 The second extension V22 may include a second sub-part V221, which may extend along the second direction Y.

[0402] Alternatively, please continue reading Figure 24 The second extension V22 may include a plurality of second sub-parts V221, which may extend along the second direction Y, and the plurality of second sub-parts V221 may be arranged at intervals along the third direction X and connected in sequence.

[0403] Please continue reading. Figure 32 , Figure 33 and Figure 34 and combined Figure 7 The orthographic projection of the second pixel opening K2 onto the substrate 1 can overlap with the orthographic projection of the second sub-part V221 onto the substrate 1.

[0404] Please continue reading. Figure 32 , Figure 33 and Figure 34 and combined Figure 7 and Figure 8 In the aforementioned display panel 100, the orthographic projection of the second pixel opening K2 onto the substrate 1 and the orthographic projection of the second sub-part V221 within the second extension V22 onto the substrate 1 overlap, such that the data signal line D1 and the second sub-part V221 within the second extension V22 can support the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12 from different positions. This is beneficial to improving the flatness of the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12, thereby improving the light emission uniformity of the second color light-emitting device S12, and thus improving the display effect of the display panel 100.

[0405] Please continue reading. Figure 34 and combined Figure 7 and Figure 8Especially when the second extension V22 includes a plurality of second sub-parts V221 and the plurality of second sub-parts V221 are arranged at intervals along the third direction X, the orthogonal projection of the second pixel opening K2 onto the substrate 1 can overlap with the orthogonal projection of the plurality of second sub-parts V221 in the second extension V22 onto the substrate 1. This allows the data signal line D1 and the plurality of second sub-parts V221 in the second extension V22 to support the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12 from different positions. This is beneficial to further improve the flatness of the actual effective area of ​​the first electrode 311 in the second color light-emitting device S12, thereby further suppressing the color separation phenomenon of the second color light-emitting device S12 and further improving the light emission uniformity of the second color light-emitting device S12, which in turn is beneficial to further improve the display effect of the display panel 100.

[0406] For example, please continue reading Figure 32 , Figure 33 and Figure 34 When two data signal lines D1 are provided between two adjacent second voltage signal lines V2, and a second virtual line N2 extending along the second direction Y is located between the two data signal lines D1, the second extension V22 within the two adjacent second voltage signal lines V2 can be symmetrically arranged relative to the second virtual line N2.

[0407] Please continue reading. Figure 32 , Figure 33 and Figure 34 and combined Figure 8 In the aforementioned display panel 100, the second extensions V22 within two adjacent second voltage signal lines V2 are symmetrically arranged relative to the second virtual line N2. On the one hand, when the data signal line D1 and the second extensions V22 within the two second voltage signal lines V2 support the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12 from different positions, the second extensions V22 within the two second voltage signal lines V2 are symmetrically distributed below the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12. This helps to further suppress the color separation phenomenon of the second color light-emitting device S12 and further improve the flatness of the actual effective area of ​​the first electrode 311 within the second color light-emitting device S12. This, in turn, helps to further improve the light emission uniformity of the second color light-emitting device S12, thereby further improving the display effect of the display panel 100.

[0408] On the other hand, the signal line arrangement in the first conductive layer 21 can be optimized, thereby saving wiring space in the first conductive layer 21, which is beneficial to improving the PPI (Pixels Per Inch) of the display panel 100.

[0409] For example, please continue reading Figure 22 , Figure 23 and Figure 24 The dimension h3 of the data signal line D1 along the third direction X can be equal to the dimension h4 of the second sub-part V221 within the second extension V22 along the third direction X.

[0410] For example, please continue reading Figure 22 , Figure 23 and Figure 24 The dimension h3 of the data signal line D1 along the third direction X can be greater than or equal to 1.9 μm and less than or equal to 2.8 μm.

[0411] For example, please continue reading Figure 22 , Figure 23 and Figure 24 The size h3 of the data signal line D1 along the third direction X can be 1.9μm, 2μm, 2.1μm, 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm, 2.7μm or 2.8μm, etc.

[0412] For example, please continue reading Figure 22 , Figure 23 and Figure 24 The dimension h4 of the second sub-part V221 within the second extension V22 along the third direction X can be greater than or equal to 1.9 μm and less than or equal to 2.8 μm.

[0413] For example, please continue reading Figure 22 , Figure 23 and Figure 24 The size h4 of the second sub-part V221 within the second extension V22 along the third direction X can be 1.9μm, 2μm, 2.1μm, 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm, 2.7μm, or 2.8μm, etc.

[0414] For example, please continue reading Figure 24 When the second extension V22 includes a plurality of second sub-sections V221, the distance d4 between the data signal line D1 and the second extension V22 along the third direction X can be equal to the distance d5 between two adjacent second sub-sections V221 along the third direction X.

[0415] For example, please continue reading Figure 24 The distance d4 between the data signal line D1 and the second extension V22 along the third direction X can be greater than or equal to 2μm and less than or equal to 2.9μm.

[0416] For example, please continue reading Figure 24The spacing d4 between the data signal line D1 and the second extension V22 along the third direction X can be 2μm, 2.1μm, 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm, 2.7μm, 2.8μm or 2.9μm, etc.

[0417] For example, please continue reading Figure 24 When the second extension V22 includes a plurality of second sub-parts V221, the distance d5 between two adjacent second sub-parts V221 along the third direction X can be greater than or equal to 2 μm and less than or equal to 2.9 μm.

[0418] For example, please continue reading Figure 24 The spacing d5 between two adjacent second sub-parts V221 along the third direction X can be 2μm, 2.1μm, 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm, 2.7μm, 2.8μm or 2.9μm, etc.

[0419] For example, please continue reading Figure 28 , Figure 29 , Figure 30 , Figure 32 , Figure 33 and Figure 34 and combined Figure 7 In the orthographic projection onto the substrate 1, there can be at least two second pixel openings K2 with the same shape and area, and different total overlap areas with the data signal line D1 and the second voltage signal line V2.

[0420] Please continue reading. Figures 13-16 The relative positional relationship of the third pixel opening K3 in the pixel definition layer PDL and the conductive structure (e.g., the first voltage signal line V1, the second fan-out line F2, and the conductive pattern 221) in the second conductive layer 22 can be the same as or similar to the relative positional relationship of the second pixel opening K2 in the pixel definition layer PDL and the conductive structure in the second conductive layer 22, and will not be described in detail here.

[0421] Please continue reading. Figures 28-34 The relative positional relationship between the third pixel opening K3 in the pixel definition layer PDL and the conductive structure (e.g., the second voltage signal line V2, the data signal line D1, the first fan-out line F1, and the third conductive pattern 211) in the first conductive layer 21 can be the same as or similar to the relative positional relationship between the second pixel opening K2 in the pixel definition layer PDL and the conductive structure in the first conductive layer 21, and will not be elaborated here.

[0422] It should be noted that the above is only based on Figures 13-16 and Figures 28-34The relative positional relationships of the first pixel opening K1 within the pixel definition layer PDL and the conductive structures (e.g., the first voltage signal line V1, the second fan-out line F2, and the conductive pattern 221) within the second conductive layer 22, the relative positional relationships of the second pixel opening K2 within the pixel definition layer PDL and the conductive structures within the second conductive layer 22, and the relative positional relationships of the first pixel opening K1 within the pixel definition layer PDL and the conductive structures (e.g., the second voltage signal line V2, the data signal line D1, the first fan-out line F1, and the third conductive pattern 211) within the first conductive layer 21, and the relative positional relationships of the second pixel opening K2 within the pixel definition layer PDL and the conductive structures within the first conductive layer 21 are exemplarily described. However, when the driving layer 2 includes the first conductive layer 21 and the second conductive layer 22, Figures 13-16 The second conductive layer 22 in the embodiment shown, and Figures 28-34 The first conductive layer 21 in the illustrated embodiments can be arbitrarily combined, and any combination of the above embodiments is within the protection scope of this application.

[0423] For example, such as Figure 35 As shown, Figure 35 This is a plan view of a partial region of the first conductive layer 21 and the second conductive layer 22 in the driving layer 2 according to some embodiments, and the pixel definition layer (PDL) in the light-emitting device layer 3. Figure 13 The illustrated embodiment can be used with Figure 29 The illustrated embodiment combination is used to obtain Figure 35 The example shown.

[0424] For example, such as Figure 36 As shown, Figure 36 This is a plan view of a partial region of the first conductive layer 21 and the second conductive layer 22 in the driving layer 2 according to some embodiments, and the pixel definition layer (PDL) in the light-emitting device layer 3. Figure 13 The illustrated embodiment can be used with Figure 33 The illustrated embodiment combination is used to obtain Figure 36 The example shown.

[0425] For example, such as Figure 37 As shown, Figure 37 This is a plan view of a partial region of the first conductive layer 21 and the second conductive layer 22 in the driving layer 2 according to some embodiments, and the pixel definition layer (PDL) in the light-emitting device layer 3. Figure 13 The illustrated embodiment can be used with Figure 31 The illustrated embodiment combination is used to obtain Figure 37 The example shown.

[0426] For example, such as Figure 38 As shown, Figure 38This is a plan view of a partial region of the first conductive layer 21 and the second conductive layer 22 in the driving layer 2 according to some embodiments, and the pixel definition layer (PDL) in the light-emitting device layer 3. Figure 14 The illustrated embodiment can be used with Figure 29 The illustrated embodiment combination is used to obtain Figure 38 The example shown.

[0427] For example, such as Figure 39 As shown, Figure 39 This is a plan view of a partial region of the first conductive layer 21 and the second conductive layer 22 in the driving layer 2 according to some embodiments, and the pixel definition layer (PDL) in the light-emitting device layer 3. Figure 14 The illustrated embodiment can be used with Figure 33 The illustrated embodiment combination is used to obtain Figure 39 The example shown.

[0428] For example, such as Figure 40 As shown, Figure 40 This is a plan view of a partial region of the first conductive layer 21 and the second conductive layer 22 in the driving layer 2 according to some embodiments, and the pixel definition layer (PDL) in the light-emitting device layer 3. Figure 14 The illustrated embodiment can be used with Figure 31 The illustrated embodiment combination is used to obtain Figure 40 The example shown.

[0429] For example, such as Figure 41 As shown, Figure 41 This is a plan view of a partial region of the first conductive layer 21 and the second conductive layer 22 in the driving layer 2 according to some embodiments, and the pixel definition layer (PDL) in the light-emitting device layer 3. Figure 15 The illustrated embodiment can be used with Figure 29 The illustrated embodiment combination is used to obtain Figure 41 The example shown.

[0430] For example, such as Figure 42 As shown, Figure 42 This is a plan view of a partial region of the first conductive layer 21 and the second conductive layer 22 in the driving layer 2 according to some embodiments, and the pixel definition layer (PDL) in the light-emitting device layer 3. Figure 15 The illustrated embodiment can be used with Figure 33 The illustrated embodiment combination is used to obtain Figure 42 The example shown.

[0431] For example, such as Figure 43 As shown, Figure 43 This is a plan view of a partial region of the first conductive layer 21 and the second conductive layer 22 in the driving layer 2 according to some embodiments, and the pixel definition layer (PDL) in the light-emitting device layer 3. Figure 15 The illustrated embodiment can be used with Figure 31 The illustrated embodiment combination is used to obtain Figure 43 The example shown.

[0432] For example, such as Figure 44 As shown, Figure 44 This is a plan view of a partial region of the first conductive layer 21 and the second conductive layer 22 in the driving layer 2 according to some embodiments, and the pixel definition layer (PDL) in the light-emitting device layer 3. Figure 16 The illustrated embodiment can be used with Figure 29 The illustrated embodiment combination is used to obtain Figure 44 The example shown.

[0433] For example, such as Figure 45 As shown, Figure 45 This is a plan view of a partial region of the first conductive layer 21 and the second conductive layer 22 in the driving layer 2 according to some embodiments, and the pixel definition layer (PDL) in the light-emitting device layer 3. Figure 16 The illustrated embodiment can be used with Figure 33 The illustrated embodiment combination is used to obtain Figure 45 The example shown.

[0434] For example, such as Figure 46 As shown, Figure 46 This is a plan view of a partial region of the first conductive layer 21 and the second conductive layer 22 in the driving layer 2 according to some embodiments, and the pixel definition layer (PDL) in the light-emitting device layer 3. Figure 16 The illustrated embodiment can be used with Figure 31 The illustrated embodiment combination is used to obtain Figure 46 The example shown.

[0435] In some embodiments, please continue reading Figure 41 , Figure 42 , Figure 43 , Figure 44 , Figure 45 and Figure 46 and combined Figure 7 The driving layer 2 includes a first conductive layer 21 and a second conductive layer 22, and the first conductive layer 21 includes data signal lines.

[0436] When the second conductive layer 22 includes a conductive pattern 221, the orthogonal projection of the data signal line D1 onto the substrate 1 can overlap with the orthogonal projection of the conductive pattern 221 onto the substrate 1.

[0437] For example, please continue reading Figure 41 , Figure 42 , Figure 43 , Figure 44 , Figure 45 and Figure 46 and combined Figure 7 When the conductive pattern 221 includes the second conductive pattern 2212, the orthogonal projection of the data signal line D1 onto the substrate 1 can overlap with the orthogonal projection of the second conductive pattern 2212 onto the substrate 1.

[0438] For example, please continue reading Figure 14 , Figure 15 and Figure 16 and combined Figure 7 When the distance d1 between the boundary of the orthographic projection of at least one of the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3 in the pixel definition layer PDL onto the substrate 1 and the boundary of the orthographic projection of the conductive pattern 221 onto the substrate 1 is less than or equal to 9 μm, the planar area of ​​the conductive pattern 221 is small. When the orthographic projection of the data signal line D1 onto the substrate 1 and the orthographic projection of the conductive pattern 221 onto the substrate 1 overlap, the parasitic capacitance between the data signal line D1 and the conductive pattern 221 can be reduced, thereby reducing the crosstalk between the data signal line D1 and the conductive pattern 221, which is beneficial to improving the display effect of the display panel 100.

[0439] In some embodiments, such as Figure 47 As shown, Figure 47 This is a cross-sectional view of a partial region of the first conductive layer 21, the first insulating layer 51, and the second conductive layer 22 within the driving layer 2 according to some embodiments. In cases where the driving layer 2 includes the first conductive layer 21 and the second conductive layer 22, the driving layer 2 may further include the first insulating layer 51. The first insulating layer 51 may be located between the first conductive layer 21 and the second conductive layer 22.

[0440] For example, please continue reading Figure 47 The first insulating layer 51 may include a single-layer film structure.

[0441] Alternatively, the first insulating layer 51 may include a multilayer film structure.

[0442] For example, please continue reading Figure 47 and combined Figure 41 , Figure 42 , Figure 43 , Figure 44 , Figure 45 , Figure 46 and Figure 7 When the first conductive layer 21 includes a data signal line D1, the second conductive layer 22 includes a conductive pattern 221, and the orthographic projection of the data signal line D1 onto the substrate 1 and the orthographic projection of the conductive pattern 221 onto the substrate 1 overlap, the dimension h5 of the first insulating layer 51 along the first direction Z can be greater than or equal to 2 μm.

[0443] In the aforementioned display panel 100, the dimension h5 of the first insulating layer 51 along the first direction Z is greater than or equal to 2μm, which makes the dimension h5 of the first insulating layer 51 along the first direction Z larger. This can reduce the parasitic capacitance between the data signal line D1 and the conductive pattern 221, thereby reducing the crosstalk between the data signal line D1 and the conductive pattern 221, which is beneficial to improving the display effect of the display panel 100.

[0444] For example, such as Figure 48 As shown, and in combination Figure 35 , Figure 36 , Figure 37 and Figure 7 , Figure 48 This is a cross-sectional view of a portion of the first conductive layer 21, the first insulating layer 51, and the second insulating layer 52 within the driving layer 2, and the first electrode layer 31 within the light-emitting device layer 3, according to some embodiments. When at least one of the first pixel opening K1, the second pixel opening K2, and the third pixel opening K3 in the pixel definition layer PDL projects onto the substrate 1, and the projected onto the substrate 1 by the conductive structure (e.g., the first voltage signal line V1 and the second fan-out line F2, etc.) in the second conductive layer 22 does not overlap, the first insulating layer 51 and the second insulating layer 52 between at least one of the first electrode 311 in the first color light-emitting device S11, the first electrode 311 in the second color light-emitting device S12, and the first electrode 311 in the third color light-emitting device S13, and the first insulating layer 51 and the first conductive layer 21 are continuously disposed. This is beneficial to improving the flatness of the actual effective area of ​​at least one of the first electrode 311 in the first color light-emitting device S11, the first electrode 311 in the second color light-emitting device S12, and the first electrode 311 in the third color light-emitting device S13, thereby improving the light emission uniformity of at least one of the first color light-emitting device S11, the second color light-emitting device S12, and the third color light-emitting device S13, and thus improving the display effect of the display panel 100.

[0445] In some embodiments, such as Figure 49 As shown, and in combination Figure 7 and Figure 46 , Figure 49 This is a plan view of a partial area of ​​the driving layer 2 within a display panel 100 according to some embodiments. The driving layer 2 within the display panel 100 may include a light-shielding layer 27, a first active layer 29, a first gate layer 23, a second gate layer 24, a second active layer 25, a third gate layer 26, and a first source / drain conductive layer 28.

[0446] The light-shielding layer 27, the first active layer 29, the first gate layer 23, the second gate layer 24, the second active layer 25, the third gate layer 26, and the first source / drain conductive layer 28 can be stacked sequentially in a direction away from the substrate 1, and all of them are located on the side of the first conductive layer 21 in the driving layer 2 that is close to the substrate 1.

[0447] It should be noted that, Figure 49 Only the light-shielding layer 27, the first active layer 29, the first gate layer 23, the second gate layer 24, the second active layer 25, the third gate layer 26, and the first source / drain conductive layer 28 within the driving layer 2 are shown. Other films within the driving layer 2 are omitted, such as the buffer layer located on the side of the light-shielding layer 27 near the substrate 1, the gate insulating layer located between the first active layer 29 and the first gate layer 23, the gate insulating layer located between the first gate layer 23 and the second gate layer 24, the gate insulating layer located between the second gate layer 24 and the second active layer 25, the gate insulating layer located between the second active layer 25 and the third gate layer 26, the insulating layer located between the third gate layer 26 and the first source / drain conductive layer 28, the insulating layer located between the first source / drain conductive layer 28 and the first conductive layer 21, the first conductive layer 21, and the second conductive layer 22.

[0448] In some embodiments, such as Figure 50 As shown, Figure 50 This is a plan view of a partial region of the light-shielding layer 27 and the first active layer 29 within the driving layer 2 according to some embodiments. The light-shielding layer 27 within the driving layer 2 may be a bottom-shielding metal (BSM) layer.

[0449] For example, the material of the light-shielding layer 27 may include a metal. For instance, the material of the light-shielding layer 27 may include a metallic material such as molybdenum (Mo).

[0450] In some embodiments, such as Figure 51 As shown, and in combination Figure 6 , Figure 51 This is a plan view of a partial region of the first active layer 29 and the first gate layer 23 within the driving layer 2 according to some embodiments. When the pixel circuit S2 within the display panel 100 includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, and a third reset transistor T8, the first active layer 29 within the driving layer 2 may include an active pattern of at least a portion of the transistors selected from the first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8.

[0451] The active patterns of the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8 can all include a first electrode, a second electrode, and a channel region located between the first electrode and the second electrode.

[0452] For example, please continue reading Figure 51 The first active layer 29 may include the active pattern T11 of the first reset transistor T1, the active pattern T31 of the driving transistor T3, the active pattern T41 of the data writing transistor T4, the active pattern T51 of the first light-emitting control transistor T5, the active pattern T61 of the second light-emitting control transistor T6, the active pattern T71 of the second reset transistor T7, and the active pattern T81 of the third reset transistor T8.

[0453] For example, the material of the first active layer 29 may include low-temperature polycrystalline silicon.

[0454] Alternatively, the material of the first active layer 29 may include at least one of indium gallium zinc oxide and low-temperature polycrystalline oxide. For example, the material of the first active layer 29 may include indium gallium zinc oxide (IGZO).

[0455] For example, the material of the first active layer 29 may include indium gallium zinc tin oxide (IGZTO), etc.

[0456] In some embodiments, please continue reading Figure 51 and combined Figure 6 When the pixel circuit S2 in the display panel 100 includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, and a third reset transistor T8, the first gate layer 23 in the driving layer 2 may include the gate pattern of at least a portion of the transistors selected from the first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8.

[0457] For example, please continue reading Figure 51The first gate layer 23 may include the gate pattern T12 of the first reset transistor T1, the gate pattern T32 of the driving transistor T3, the gate pattern T42 of the data writing transistor T4, the gate pattern T52 of the first light-emitting control transistor T5, the gate pattern T62 of the second light-emitting control transistor T6, the gate pattern T72 of the second reset transistor T7, and the gate pattern T82 of the third reset transistor T8.

[0458] For example, please continue reading Figure 51 The first gate layer 23 may further include a second scan signal line Pgate. The second scan signal line Pgate may extend in a third direction X.

[0459] For example, please continue reading Figure 51 The first gate layer 23 may further include a first reset control signal line Reset1. The first reset control signal line Reset1 may extend along a third direction X.

[0460] For example, please continue reading Figure 51 The first gate layer 23 may further include a second reset control signal line Reset2. The second reset control signal line Reset2 may extend along a third direction X.

[0461] For example, please continue reading Figure 51 The first gate layer 23 may further include a light-emitting control signal line EM. The light-emitting control signal line EM may extend in a third direction X.

[0462] For example, please continue reading Figure 51 and combined Figure 6 In the case where the pixel circuit S2 in the display panel 100 includes a storage capacitor C1, the first gate layer 23 may also include a first electrode C11 of the storage capacitor C1.

[0463] For example, please continue reading Figure 51 The gate pattern T32 of the driving transistor T3 can also serve as the first plate C11 of the storage capacitor C1.

[0464] In some embodiments, such as Figure 52 As shown, and in combination Figure 6 , Figure 52 This is a plan view of a partial region of the first gate layer 23 and the second gate layer 24 within the driving layer 2 according to some embodiments. In the case where the pixel circuit S2 within the display panel 100 includes a storage capacitor C1, the second gate layer 24 within the driving layer 2 may include the second electrode C12 of the storage capacitor C1.

[0465] For example, please continue reading Figure 52 and combined Figure 6When the pixel circuit S2 in the display panel 100 includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, and a third reset transistor T8, the second gate layer 24 in the driving layer 2 may include the gate pattern of at least a portion of the transistors among the first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8.

[0466] For example, please continue reading Figure 52 The second gate layer 24 may include the gate pattern T22 of the threshold compensation transistor T2.

[0467] For example, please continue reading Figure 52 The second gate layer 24 may further include a first scan signal line Ngate. The first scan signal line Ngate may extend in a third direction X.

[0468] In some embodiments, such as Figure 53 As shown, and in combination Figure 6 , Figure 53 This is a plan view of a partial region of the second gate layer 24, the second active layer 25, and the third gate layer 26 within the driving layer 2 according to some embodiments. In the case where the pixel circuit S2 within the display panel 100 includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, and a third reset transistor T8, the second active layer 25 within the driving layer 2 may include an active pattern of at least a portion of the transistors selected from the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8.

[0469] For example, please continue reading Figure 53 The second active layer 25 may include the active pattern T21 of the threshold compensation transistor T2.

[0470] For example, the material of the second active layer 25 may include low-temperature polycrystalline silicon.

[0471] Alternatively, the material of the second active layer 25 may include at least one of indium gallium zinc oxide and low-temperature polycrystalline oxide. For example, the material of the second active layer 25 may include indium gallium zinc oxide, etc.

[0472] For example, the material of the second active layer 25 may include indium gallium zinc tin oxide, etc.

[0473] In some embodiments, please continue reading Figure 53 and combined Figure 6 When the pixel circuit S2 in the display panel 100 includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, and a third reset transistor T8, the third gate layer 26 in the driving layer 2 may include the gate pattern of at least a portion of the transistors among the first reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8.

[0474] For example, please continue reading Figure 53 The third gate layer 26 may include the gate pattern T22 of the threshold compensation transistor T2.

[0475] For example, please continue reading Figure 53 The third gate layer 26 may also include a first scan signal line Ngate. The first scan signal line Ngate may extend in the third direction X.

[0476] For example, please continue reading Figure 53 The third gate layer 26 may also include a first initialization signal line Vinit1. The first initialization signal line Vinit1 may extend along the third direction X.

[0477] For example, please continue reading Figure 53 The third gate layer 26 may also include a second initialization signal line Vinit2. The second initialization signal line Vinit2 may extend along a third direction X.

[0478] For example, please continue reading Figure 53 The third gate layer 26 may also include a third initialization signal line Vinit3. The third initialization signal line Vinit3 may extend along a third direction X.

[0479] In some embodiments, such as Figure 54 As shown, Figure 54 This is a plan view of a partial region of the third gate layer 26 and the first source / drain conductive layer 28 within the driver layer 2 according to some embodiments. The first source / drain conductive layer 28 within the driver layer 2 may include a fourth initialization signal line Vinit4. The fourth initialization signal line Vinit4 may extend along a second direction Y.

[0480] For example, please continue reading Figure 54 The fourth initialization signal line Vinit4 can be connected to the first initialization signal line Vinit1, so that the fourth initialization signal line Vinit4 and the first initialization signal line Vinit1 can form a mesh connection structure together. This allows the first initialization signal to be transmitted in a distributed manner through the mesh connection structure, thereby reducing the voltage drop of the first initialization signal on the transmission path, which is beneficial to improving the uniformity of the first initialization signal. This, in turn, is beneficial to improving the display uniformity of the display panel 100, thereby reducing the probability of display defects such as horizontal lines on the display panel 100.

[0481] For example, please continue reading Figure 54 The fourth initialization signal line Vinit4 can be connected to the second initialization signal line Vinit2, so that the fourth initialization signal line Vinit4 and the second initialization signal line Vinit2 can jointly form a mesh connection structure. This allows the second initialization signal to be transmitted in a distributed manner through the mesh connection structure, thereby reducing the voltage drop of the second initialization signal on the transmission path, which is beneficial to improving the uniformity of the second initialization signal. This, in turn, is beneficial to improving the display uniformity of the display panel 100, thereby reducing the probability of display defects such as horizontal lines on the display panel 100.

[0482] For example, please continue reading Figure 54 The fourth initialization signal line Vinit4 can be connected to the third initialization signal line Vinit3, so that the fourth initialization signal line Vinit4 and the third initialization signal line Vinit3 can jointly form a mesh connection structure. This allows the third initialization signal to be transmitted in a distributed manner through the mesh connection structure, thereby reducing the voltage drop of the third initialization signal on the transmission path, which is beneficial to improving the uniformity of the third initialization signal. This, in turn, is beneficial to improving the display uniformity of the display panel 100, thereby reducing the probability of display defects such as horizontal lines on the display panel 100.

[0483] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, It includes a substrate, a driving layer, and a light-emitting device layer; the substrate, the driving layer, and the light-emitting device layer are stacked sequentially along a first direction, the first direction being the thickness direction of the substrate; The driving layer includes: A first conductive layer includes data signal lines; the data signal lines extend along a second direction, which is perpendicular to the first direction. A second conductive layer is located on the side of the first conductive layer away from the substrate; the second conductive layer includes a conductive pattern. The light-emitting device layer includes multiple light-emitting devices, each light-emitting device including a first electrode; the multiple light-emitting devices include a first-color light-emitting device, a second-color light-emitting device, and a third-color light-emitting device; The light-emitting device layer further includes: First electrode layer; the first electrode layer is composed of the first electrode within the light-emitting device; A pixel definition layer is located on the side of the first electrode layer away from the substrate; the pixel definition layer includes a first pixel opening, a second pixel opening, and a third pixel opening; Wherein, the orthogonal projection of at least one of the first pixel opening, the second pixel opening, and the third pixel opening onto the substrate is located within the boundary range of the orthogonal projection of the conductive pattern onto the substrate.

2. The display panel according to claim 1, characterized in that, The conductive pattern includes a first conductive pattern; The orthographic projection of the first pixel opening onto the substrate is located within the boundary range of the orthographic projection of the first conductive pattern onto the substrate.

3. The display panel according to claim 2, characterized in that, The second conductive layer further includes a first voltage signal line; the first voltage signal line extends along a third direction, the third direction being perpendicular to the first direction and intersecting with the second direction; The first conductive pattern is connected to the first voltage signal line.

4. The display panel according to claim 3, characterized in that, The second conductive layer includes a plurality of the first conductive patterns; A first voltage signal line is connected to a plurality of first conductive patterns, and the plurality of first conductive patterns connected to the same first voltage signal line are located on the same side of the first voltage signal line along the second direction.

5. The display panel according to claim 1, characterized in that, The conductive pattern includes a second conductive pattern; The orthographic projection of the second pixel opening onto the substrate is located within the boundary range of the orthographic projection of the second conductive pattern onto the substrate; And / or, The orthogonal projection of the third pixel opening onto the substrate is located within the boundary range of the orthogonal projection of the second conductive pattern onto the substrate.

6. The display panel according to claim 5, characterized in that, The second conductive layer further includes a first voltage signal line; the first voltage signal line extends along a third direction, the third direction being perpendicular to the first direction and intersecting with the second direction; The second conductive pattern is connected to the first voltage signal line.

7. The display panel according to claim 6, characterized in that, The second conductive layer includes a plurality of the second conductive patterns; A first voltage signal line is connected to a plurality of second conductive patterns, and the plurality of second conductive patterns connected to the same first voltage signal line are located on the same side of the first voltage signal line along the second direction.

8. The display panel according to claim 6, characterized in that, The conductive pattern further includes a first conductive pattern; the orthographic projection of the first pixel opening onto the substrate is located within the boundary range of the orthographic projection of the first conductive pattern onto the substrate; the first conductive pattern is connected to the first voltage signal line; The first conductive pattern and the second conductive pattern, which are connected to the same first voltage signal line, are located on opposite sides of the first voltage signal line along the second direction.

9. The display panel according to claim 8, characterized in that, The second conductive layer includes: Multiple first conductive patterns are arranged at intervals along the third direction; Multiple second conductive patterns are arranged at intervals along the third direction; along the second direction, the first conductive pattern corresponds to the gap region between two adjacent second conductive patterns, and the second conductive pattern corresponds to the gap region between two adjacent first conductive patterns.

10. The display panel according to any one of claims 1 to 9, characterized in that, The distance between the boundary of the orthographic projection of at least one of the first pixel opening, the second pixel opening, and the third pixel opening onto the substrate, and the boundary of the orthographic projection of the conductive pattern onto the substrate is less than or equal to 9 μm.

11. The display panel according to any one of claims 1 to 9, characterized in that, The driving layer further includes a first insulating layer, which is located between the first conductive layer and the second conductive layer; The dimension of the first insulating layer along the first direction is greater than or equal to 2 μm.

12. The display panel according to any one of claims 1 to 9, characterized in that, The first conductive layer further includes a third conductive pattern; the orthographic projection of the first pixel opening onto the substrate is located within the boundary range of the orthographic projection of the third conductive pattern onto the substrate.

13. The display panel according to claim 12, characterized in that, The first conductive layer further includes a second voltage signal line, which extends along the second direction; The third conductive pattern is located on one side of the second voltage signal line along the third direction and is connected to the second voltage signal line to form an integral structure; the third direction is perpendicular to the first direction and intersects with the second direction.

14. The display panel according to claim 13, characterized in that, The first conductive layer includes a plurality of second voltage signal lines, which are spaced apart along the third direction; The third conductive pattern is located between two adjacent second voltage signal lines and is connected to the two second voltage signal lines respectively, forming an integral structure.

15. The display panel according to any one of claims 1 to 9, characterized in that, The first conductive layer further includes: The first fan-out line extends along the second direction; the orthographic projection of the first fan-out line onto the substrate and the orthographic projection of the first pixel opening onto the substrate at least partially overlap; The second voltage signal line extends along the second direction; the first fan-out line is located on one side of the second voltage signal line along a third direction, the third direction being perpendicular to the first direction and intersecting the second direction; the orthographic projection of the first pixel opening onto the substrate and the orthographic projection of the second voltage signal line onto the substrate at least partially overlap.

16. The display panel according to claim 15, characterized in that, The second voltage signal line includes: The main body extends along the second direction; A first extension is connected to the main body; along the third direction, the first extension is located between the main body and the first fan-out line; The first extension includes a first sub-part extending along the second direction; or, The first extension includes a plurality of first sub-parts, which extend along the second direction and are arranged at intervals along the third direction and connected in sequence; Wherein, the orthographic projection of the first pixel opening onto the substrate and the orthographic projection of the first sub-part onto the substrate overlap.

17. The display panel according to claim 16, characterized in that, The dimension of the first fan-out line along the third direction is equal to the dimension of the first sub-part along the third direction; and / or, When the first extension includes a plurality of first sub-parts, the spacing between the first fan-out line and the first extension along the third direction is equal to the spacing between two adjacent first sub-parts along the third direction.

18. The display panel according to claim 16, characterized in that, The dimension of the first fan-out line along the third direction is greater than or equal to 1.9 μm and less than or equal to 2.8 μm; and / or, the dimension of the first extension along the third direction is greater than or equal to 1.9 μm and less than or equal to 2.8 μm; The distance between the first fan-out line and the first extension along the third direction is greater than or equal to 2 μm and less than or equal to 2.9 μm; and / or, in the case where the first extension includes a plurality of first sub-parts, the distance between two adjacent first sub-parts along the third direction is greater than or equal to 2 μm and less than or equal to 2.9 μm.

19. The display panel according to claim 16, characterized in that, The first conductive layer includes a plurality of second voltage signal lines, which are spaced apart along the third direction; The first fan-out line is located between two adjacent second voltage signal lines, and the first extension portion within the two adjacent second voltage signal lines is symmetrically arranged with respect to the first fan-out line.

20. The display panel according to claim 15, characterized in that, The first pixel opening is symmetrically arranged with respect to the first virtual line extending along the second direction; The orthographic projection of the first virtual line onto the substrate is located within the boundary range of the orthographic projection of the first fan-out line onto the substrate.

21. The display panel according to any one of claims 1 to 9, characterized in that, The orthographic projection of the second pixel opening onto the substrate and the orthographic projection of the data signal line onto the substrate at least partially overlap; The first conductive layer further includes a second voltage signal line; the data signal line is located on one side of the second voltage signal line along a third direction, the third direction being perpendicular to the first direction and intersecting with the second direction; The orthographic projection of the second pixel opening onto the substrate and the orthographic projection of the second voltage signal line onto the substrate at least partially overlap.

22. The display panel according to claim 21, characterized in that, The second voltage signal line includes: The main body extends along the second direction; A second extension is connected to the main body; along the third direction, the second extension is located between the main body and the data signal line; The second extension includes a second sub-part extending along the second direction; or, The second extension includes a plurality of second sub-parts, which extend along the second direction and are arranged at intervals along the third direction and connected in sequence; The orthographic projection of the second pixel opening onto the substrate overlaps with the orthographic projection of the second sub-part onto the substrate.

23. The display panel according to claim 22, characterized in that, The dimension of the data signal line along the third direction is equal to the dimension of the second sub-part along the third direction; and / or, In the case where the second extension includes a plurality of second sub-sections, the spacing between the data signal line and the second extension along the third direction is equal to the spacing between two adjacent second sub-sections along the third direction.

24. The display panel according to claim 22, characterized in that, The dimension of the data signal line along the third direction is greater than or equal to 1.9 μm and less than or equal to 2.8 μm; and / or, the dimension of the second sub-part along the third direction is greater than or equal to 1.9 μm and less than or equal to 2.8 μm; The distance between the data signal line and the second extension along the third direction is greater than or equal to 2 μm and less than or equal to 2.9 μm; and / or, in the case where the second extension includes a plurality of second sub-parts, the distance between two adjacent second sub-parts along the third direction is greater than or equal to 2 μm and less than or equal to 2.9 μm.

25. The display panel according to claim 22, characterized in that, The first conductive layer includes multiple second voltage signal lines, which are spaced apart along the third direction. The data signal line is located between two adjacent second voltage signal lines.

26. The display panel according to claim 25, characterized in that, Two data signal lines are provided between two adjacent second voltage signal lines; The second virtual line extends along the second direction and is located between the two data signal lines; the second extension portion within the two adjacent second voltage signal lines is symmetrically arranged with respect to the second virtual line.

27. The display panel according to claim 26, characterized in that, The second pixel opening is symmetrically arranged with respect to the second virtual line.

28. The display panel according to claim 21, characterized in that, In the orthographic projection onto the substrate, at least two of the second pixel openings have the same shape and area, and their total overlap area with the data signal line and the second voltage signal line is different.

29. The display panel according to any one of claims 1 to 9, characterized in that, The orthographic projection of the second pixel opening onto the substrate and the orthographic projection of the data signal line onto the substrate at least partially overlap; The first conductive layer further includes a first fan-out line; the first fan-out line is located on one side of the data signal line along a third direction, the third direction being perpendicular to the first direction and intersecting with the second direction; The orthographic projection of the first fan-out line onto the substrate and the orthographic projection of the second pixel opening onto the substrate at least partially overlap.

30. The display panel according to claim 29, characterized in that, The first conductive layer includes multiple data signal lines, which are spaced apart along the third direction. The first fan-out line is located between two adjacent data signal lines.

31. The display panel according to claim 30, characterized in that, The second pixel opening is symmetrically arranged with respect to the second virtual line extending along the second direction; The orthographic projection of the second virtual line onto the substrate lies within the boundary range of the orthographic projection of the first fan-out line onto the substrate.

32. The display panel according to any one of claims 1 to 9, characterized in that, The first conductive layer further includes a second voltage signal line; the second voltage signal line extends along the second direction; The second conductive layer further includes a first voltage signal line; the first voltage signal line extends along a third direction, the third direction being perpendicular to the first direction and intersecting with the second direction; the first voltage signal line is connected to the second voltage signal line.

33. The display panel according to any one of claims 1 to 9, characterized in that, The first conductive layer further includes a first fan-out line; the first fan-out line extends along the second direction; The second conductive layer further includes a second fan-out line; the second fan-out line extends along a third direction, the third direction being perpendicular to the first direction and intersecting with the second direction; Wherein, the second fan-out line is connected to both the first fan-out line and the data signal line; or... The light-emitting device layer further includes a second electrode layer, which is located on the side of the pixel definition layer away from the substrate; the second electrode layer includes a third voltage signal line; the second fan-out line is connected to the first fan-out line and the third voltage signal line respectively.

34. A display panel, characterized in that, It includes a substrate, a driving layer, and a light-emitting device layer; the substrate, the driving layer, and the light-emitting device layer are stacked sequentially along a first direction, the first direction being the thickness direction of the substrate; The light-emitting device layer includes a plurality of light-emitting devices, and each light-emitting device includes a first electrode; The plurality of light-emitting devices include a first-color light-emitting device, a second-color light-emitting device, and a third-color light-emitting device; The light-emitting device layer further includes: First electrode layer; the first electrode layer is composed of the first electrode within the light-emitting device; A pixel definition layer is located on the side of the first electrode layer away from the substrate; the pixel definition layer includes a first pixel opening, a second pixel opening, and a third pixel opening; The driving layer includes a first conductive layer; the first conductive layer includes: A first signal line extends along a second direction, the second direction being perpendicular to the first direction; A second voltage signal line extends along the second direction; the second voltage signal line is located on one side of the first signal line along a third direction, the third direction being perpendicular to the first direction and intersecting the second direction; Wherein, the orthographic projection of at least one of the first pixel opening, the second pixel opening, and the third pixel opening onto the substrate at least partially overlaps with the orthographic projection of the first signal line onto the substrate, and at least partially overlaps with the orthographic projection of the second voltage signal line onto the substrate.

35. The display panel according to claim 34, characterized in that, The first signal line is the first fan-out line.

36. The display panel according to claim 35, characterized in that, The first conductive layer includes a plurality of second voltage signal lines, which are spaced apart along the third direction; The first fan-out line is located between two adjacent second voltage signal lines.

37. The display panel according to claim 35, characterized in that, The orthographic projection of the first pixel opening onto the substrate overlaps with both the orthographic projection of the first fan-out line onto the substrate and the orthographic projection of the second voltage signal line onto the substrate. The second voltage signal line includes: The main body extends along the second direction; A first extension is connected to the main body; along the third direction, the first extension is located between the main body and the first fan-out line; The first extension includes a first sub-part extending along the second direction; or, The first extension includes a plurality of first sub-parts, which extend along the second direction and are arranged at intervals along the third direction and connected in sequence; Wherein, the orthographic projection of the first pixel opening onto the substrate and the orthographic projection of the first sub-part onto the substrate overlap.

38. The display panel according to claim 37, characterized in that, The first fan-out line is located between two adjacent second voltage signal lines, and the first extension portion within the two adjacent second voltage signal lines is symmetrically arranged with respect to the first fan-out line.

39. The display panel according to claim 35, characterized in that, The first conductive layer further includes a data signal line extending along the second direction; The second voltage signal line, the data signal line, and the first fan-out line are arranged at intervals along the third direction; The orthographic projections of the second voltage signal line, the data signal line, and the first fan-out line onto the substrate all at least partially overlap with the orthographic projection of the second pixel opening onto the substrate.

40. The display panel according to claim 39, characterized in that, The first conductive layer includes multiple data signal lines, which are spaced apart along the third direction. The first fan-out line is located between two adjacent data signal lines, and the two adjacent data signal lines are symmetrically arranged with respect to the first fan-out line.

41. The display panel according to claim 40, characterized in that, The second pixel opening is symmetrically arranged with respect to the second virtual line extending along the second direction; The orthographic projection of the second virtual line onto the substrate lies within the boundary range of the orthographic projection of the first fan-out line onto the substrate.

42. The display panel according to claim 34, characterized in that, The first signal line is a data signal line; the orthographic projection of the second pixel opening onto the substrate overlaps with both the orthographic projection of the data signal line onto the substrate and the orthographic projection of the second voltage signal line onto the substrate. The second voltage signal line includes: The main body extends along the second direction; A second extension is connected to the main body; along the third direction, the second extension is located between the main body and the data signal line; The second extension includes a second sub-part extending along the second direction; or, The second extension includes a plurality of second sub-parts, which extend along the second direction and are arranged at intervals along the third direction and connected in sequence; The orthographic projection of the second pixel opening onto the substrate overlaps with the orthographic projection of the second sub-part onto the substrate.

43. The display panel according to claim 42, characterized in that, The first conductive layer includes multiple second voltage signal lines, which are spaced apart along the third direction. The data signal line is located between two adjacent second voltage signal lines.

44. The display panel according to claim 43, characterized in that, Two data signal lines are provided between two adjacent second voltage signal lines; The second virtual line extends along the second direction and is located between the two data signal lines; The two data signal lines are symmetrically arranged relative to the second virtual line; and / or, The second extensions within two adjacent second voltage signal lines are symmetrically arranged relative to the second virtual line.

45. The display panel according to any one of claims 34 to 44, characterized in that, The display panel includes a display area and a peripheral area located on at least one side of the display area; the first pixel opening, the second pixel opening and the third pixel opening are located in the display area; The driving layer further includes a second conductive layer, which is located on the side of the first conductive layer away from the substrate; Wherein, the orthographic projection of at least one of the first pixel opening, the second pixel opening, and the third pixel opening onto the substrate and the orthographic projection of the conductive structure in the second conductive layer onto the substrate do not overlap.

46. ​​The display panel according to claim 45, characterized in that, The orthographic projections of the first pixel opening, the second pixel opening, and the third pixel opening onto the substrate and the orthographic projections of the conductive structure in the second conductive layer onto the substrate do not overlap.

47. The display panel according to any one of claims 34 to 44, characterized in that, The driving layer further includes a second conductive layer; the second conductive layer is located on the side of the first conductive layer away from the substrate; the second conductive layer includes a conductive pattern; The orthographic projection of at least one of the first pixel opening, the second pixel opening, and the third pixel opening onto the substrate is located within the boundary range of the orthographic projection of the conductive pattern onto the substrate.

48. The display panel according to any one of claims 34 to 44, characterized in that, The driving layer further includes a second conductive layer located on the side of the first conductive layer away from the substrate; the second conductive layer includes a first voltage signal line extending along the third direction. The first voltage signal line is connected to the second voltage signal line.

49. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 48; The driver chip is connected to the display panel.

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