A semiconductor structure

Abstract

This application discloses a semiconductor structure, relating to the field of semiconductor technology. The semiconductor structure includes: a substrate; a structure under test (SUT), the bottom surface of which is disposed on the substrate; and an encapsulation layer covering the top and side surfaces of the SUT, wherein the encapsulation layer has a heating structure and a temperature-sensing structure disposed opposite to each other, the heating structure and the temperature-sensing structure being arranged at intervals along a direction parallel to the surface of the substrate, and at least a portion of the SUT being located between the heating structure and the temperature-sensing structure. It enables lateral thermal testing of a chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure. Background Technology

[0002] With the continuous development of integrated circuit technology, chip integration density is constantly increasing. In particular, large-scale integrated chips based on chip-to-chip architecture are gradually becoming an important development direction in fields such as high-performance computing and artificial intelligence. In this architecture, multiple small chips with different functions are integrated into the same package with high density through advanced packaging technology to form a high-performance large chip system. This type of integration typically uses interconnection technologies such as through-silicon vias (TSVs) and micro-bumps to achieve vertical and lateral interconnection between chips, significantly improving signal transmission efficiency and system performance.

[0003] However, with the increasing chip integration density and power consumption, the heat generated by chips during operation has increased dramatically. Especially in chip-to-chip stacked structures, where multiple chips are tightly stacked vertically, heat easily accumulates in localized areas, leading to significant temperature increases and the formation of hotspots. Adding to the complexity, significant thermal coupling effects also exist between the individual chips in the lateral direction. Heat generated by one chip can be conducted to neighboring chips through the substrate or packaging material, affecting their operating temperature and performance stability. This lateral thermal impact is not negligible in high-density integrated systems; if it cannot be accurately assessed and modeled, it will directly affect the chip's thermal reliability, performance, and even overall lifespan.

[0004] To address the aforementioned issues, a dedicated thermal testing structure is urgently needed for testing the lateral heat dissipation characteristics between chips. Obtaining actual data on lateral heat conduction through this structure can provide crucial information for the thermal design of chip systems, thereby enabling the construction of more accurate three-dimensional thermal distribution models and improving the thermal management capabilities and reliability of large chips under complex operating conditions. Utility Model Content

[0005] The purpose of this application is to provide a semiconductor structure that enables lateral thermal testing of chips.

[0006] The embodiments of this application are implemented as follows: This application provides a semiconductor structure, including: Base; The structure under test, wherein the bottom surface of the structure under test is disposed on the substrate; An encapsulation layer covers the top and side surfaces of the structure under test, and the encapsulation layer has a heating structure and a temperature sensing structure disposed opposite to each other. The heating structure and the temperature sensing structure are arranged at intervals along a direction parallel to the surface of the substrate, and at least a portion of the structure under test is located between the heating structure and the temperature sensing structure.

[0007] Optionally, as one possible implementation, the encapsulation layer includes multiple interlayer dielectric layers stacked on the substrate, the heating structure includes multiple first metal layers, adjacent first metal layers are separated and interconnected by the interlayer dielectric layers, and the temperature sensing structure includes multiple second metal layers, adjacent second metal layers are separated and interconnected by the interlayer dielectric layers.

[0008] Alternatively, as an implementable method, the first metal layer and the second metal layer have the same number of layers.

[0009] Optionally, as an implementable approach, the structure under test includes a plurality of chips stacked on the substrate, wherein the number of stacked layers of the chips is greater than or equal to the number of layers of the first metal layer.

[0010] Optionally, as one possible implementation, the multilayer first metal layer includes a first bottom layer, a first top layer, and a multilayer first intermediate layer located between the first bottom layer and the first top layer, wherein the first bottom layer is interconnected with the first top layer via the multilayer first intermediate layer.

[0011] Optionally, as an implementable approach, the first bottom layer includes a plurality of first bottom layer metal blocks that are distributed in the same layer and spaced apart, the first top layer includes a plurality of first top layer metal blocks that are distributed in the same layer and spaced apart, there is a first gap between two adjacent first top layer metal blocks, the plurality of first bottom layer metal blocks and the plurality of first gaps are directly corresponding to each other along the thickness direction of the substrate, the first intermediate layer includes a plurality of first intermediate layer metal blocks that are distributed in the same layer and spaced apart, and each first bottom layer metal block is connected in series with the first top layer metal blocks on both sides of the corresponding gap via the first intermediate layer metal blocks.

[0012] Optionally, as an implementable approach, the series path of the first bottom metal block and the first top metal block includes multiple parallel branches.

[0013] Optionally, as one possible implementation, the multilayer second metal layer includes a second bottom layer, a second top layer, and a multilayer second intermediate layer located between the second bottom layer and the second top layer, wherein the second bottom layer is interconnected with the second top layer via the multilayer second intermediate layer.

[0014] Optionally, as an implementable method, the second bottom layer includes a plurality of second bottom layer metal blocks that are distributed in the same layer and spaced apart, the second top layer includes a plurality of second top layer metal blocks that are distributed in the same layer and spaced apart, there is a second gap between two adjacent second top layer metal blocks, the plurality of second bottom layer metal blocks and the plurality of second gaps are directly corresponding to each other along the thickness direction of the substrate, and the second intermediate layer includes a plurality of second intermediate layer metal blocks that are distributed in the same layer and spaced apart, each of the second bottom layer metal blocks is connected in series with the second top layer metal blocks on both sides of the corresponding gap via the second intermediate layer metal blocks.

[0015] Optionally, as an implementable approach, the series path of the second bottom metal block and the second top metal block includes multiple parallel branches.

[0016] The beneficial effects of the embodiments of this application include: This application provides a semiconductor structure, including: a substrate; a structure under test (SUT), the bottom surface of which is disposed on the substrate; and a packaging layer covering the top and side surfaces of the SUT, wherein the packaging layer has a heating structure and a temperature sensing structure disposed opposite to each other, the heating structure and the temperature sensing structure being arranged at intervals along a direction parallel to the substrate surface, and at least a portion of the SUT being located between the heating structure and the temperature sensing structure. By providing heating and temperature sensing structures arranged parallel to the substrate surface within the packaging layer, accurate measurement of the lateral thermal coupling effect of the chip system can be achieved. This structure can provide key data for a three-dimensional thermal distribution model, significantly improving the thermal reliability and performance stability of the chip. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the semiconductor structure provided in the embodiments of this application; Figure 2 This is a schematic diagram of the heating structure in the semiconductor structure provided in the embodiments of this application; Figure 3 This is a schematic diagram of the temperature-sensing structure in the semiconductor structure provided in the embodiments of this application.

[0019] Icons: 100 - Semiconductor structure; 110 - Substrate; 120 - Structure under test; 130 - Heating structure; 131 - First bottom layer; 1311 - First bottom layer metal block; 132 - First top layer; 1321 - First top layer metal block; 1322 - First gap; 133 - First intermediate layer; 1331 - First intermediate layer metal block; 140 - Temperature sensing structure; 141 - Second bottom layer; 1411 - Second bottom layer metal block; 142 - Second top layer; 1421 - Second top layer metal block; 1422 - Second gap; 143 - Second intermediate layer; 1431 - Second intermediate layer metal block. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0023] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] Please refer to Figure 1 , Figure 2 and Figure 3This embodiment provides a semiconductor structure 100, including: a substrate 110; a structure under test 120, the bottom surface of which is disposed on the substrate 110; and an encapsulation layer, which covers the top and side surfaces of the structure under test 120, and has a heating structure 130 and a temperature sensing structure 140 disposed opposite to each other within the encapsulation layer. The heating structure 130 and the temperature sensing structure 140 are arranged at intervals along a direction parallel to the surface of the substrate 110, and at least a portion of the structure under test 120 is located between the heating structure 130 and the temperature sensing structure 140.

[0025] Specifically, this application pre-places a heating structure 130 and a temperature-sensing structure 140 within the encapsulation layer, ensuring that they are spaced apart along a direction parallel to the surface of the substrate 110, with at least a portion of the structure under test 120 located between them. A heat source with specific power is applied through the heating structure 130 to simulate the heat distribution during chip operation. The temperature-sensing structure 140 monitors the temperature change of the structure under test 120 in real time, recording temperature gradient data along the lateral heat conduction path. Based on the temperature data, parameters such as lateral thermal resistance and thermal conductivity are calculated using heat conduction equations (such as Fourier's law) to construct a three-dimensional thermal distribution model. By setting the heating structure 130 and the temperature-sensing structure 140 within the encapsulation layer along a direction parallel to the surface of the substrate 110, accurate measurement of the lateral thermal coupling effect of the chip system is achieved. This structure provides crucial data for the three-dimensional thermal distribution model, significantly improving the thermal reliability and performance stability of the chip.

[0026] This application provides a semiconductor structure 100, including: a substrate 110; a structure under test (SUT) 120, the bottom surface of which is disposed on the substrate 110; and an encapsulation layer covering the top and side surfaces of the SUT 120. The encapsulation layer contains a heating structure 130 and a temperature-sensing structure 140 disposed opposite to each other. The heating structure 130 and the temperature-sensing structure 140 are arranged at intervals along a direction parallel to the surface of the substrate 110, with at least a portion of the SUT 120 located between the heating structure 130 and the temperature-sensing structure 140. By providing the heating structure 130 and the temperature-sensing structure 140 arranged parallel to the surface of the substrate 110 within the encapsulation layer, accurate measurement of the lateral thermal coupling effect of the chip system can be achieved. This structure can provide key data for a three-dimensional thermal distribution model, significantly improving the thermal reliability and performance stability of the chip.

[0027] In one possible embodiment of this application, such as Figure 1 , Figure 2 and Figure 3 As shown, the encapsulation layer includes multiple interlayer dielectric layers stacked on the substrate 110, the heating structure 130 includes multiple first metal layers, with adjacent first metal layers separated and interconnected by interlayer dielectric layers, and the temperature sensing structure 140 includes multiple second metal layers, with adjacent second metal layers separated and interconnected by interlayer dielectric layers.

[0028] The heating structure 130 consists of multiple first metal layers, with adjacent first metal layers separated by an interlayer dielectric layer and interconnected. This multi-layer interconnected structure increases the heating area and uniformity of the heating structure 130, ensuring stable and controllable heat during testing. The temperature sensing structure 140 includes multiple second metal layers, similarly with adjacent second metal layers separated by an interlayer dielectric layer and interconnected. The multi-layer second metal layer design improves the sensitivity and accuracy of temperature sensing, enabling more precise detection of subtle changes in heat, thereby improving the accuracy of lateral heat dissipation characteristic testing. By setting the encapsulation layer as a multi-layer interlayer dielectric layer, a stable and reliable foundation is provided for the multi-layer layout of the heating structure 130 and the temperature sensing structure 140. The heating structure 130, with its multiple interconnected first metal layers, enhances the stability and uniformity of the heating effect, ensuring controllable heat input during testing. The multi-layer second metal layer design of the temperature sensing structure 140 improves the sensitivity and accuracy of sensing heat changes, making the test data more reliable. This structural design further improves the accuracy of the lateral heat dissipation characteristic test of the entire semiconductor structure 100, providing more valuable data support for the thermal design of the chip system.

[0029] In one possible embodiment of this application, such as Figure 1 , Figure 2 and Figure 3 As shown, the first and second metal layers have the same number of layers. Because of this equal number of layers, the heating structure 130 and the temperature-sensing structure 140 can maintain a relatively balanced state when interacting thermally with the structure under test 120. During the heat transfer from the heating structure 130 through the structure under test 120 to the temperature-sensing structure 140, the significant difference in heat conduction paths caused by the different number of layers is avoided, thus reducing test errors caused by structural asymmetry.

[0030] In one possible embodiment of this application, such as Figure 1 , Figure 2 and Figure 3 As shown, the structure under test 120 includes multiple chips stacked on the substrate 110, and the number of stacked layers of the chips is greater than or equal to the number of layers of the first metal layer.

[0031] Specifically, when it is necessary to test the lateral heat dissipation performance between some chip layers, the number of stacked chip layers is greater than the number of first metal layers, and the number of first metal layers is equal to the number of chip layers to be tested. When it is necessary to test the lateral heat dissipation performance between all chip layers, the number of first metal layers is equal to the number of all chip layers.

[0032] In one possible embodiment of this application, such as Figure 1 , Figure 2 and Figure 3As shown, the multilayer first metal layer includes a first bottom layer 131, a first top layer 132, and a multilayer first intermediate layer 133 located between the first bottom layer 131 and the first top layer 132. The first bottom layer 131 is interconnected with the first top layer 132 via the multilayer first intermediate layer 133.

[0033] Specifically, the multi-layered first metal layer is divided into a first bottom layer 131, a first top layer 132, and multiple first intermediate layers 133, which are interconnected. This makes the current distribution of the heating structure 130 more reasonable and enables more uniform heating. This structural design facilitates precise control of the heating process, improves the stability and reliability of the heating effect, provides a stable heat source for lateral heat dissipation characteristic testing, and helps to obtain more accurate test data.

[0034] Furthermore, the first bottom layer 131 includes a plurality of first bottom layer metal blocks 1311 distributed at intervals on the same layer, the first top layer 132 includes a plurality of first top layer metal blocks 1321 distributed at intervals on the same layer, and there is a first gap 1322 between two adjacent first top layer metal blocks 1321. The plurality of first bottom layer metal blocks 1311 and the plurality of first gaps 1322 are directly corresponding to each other along the thickness direction of the substrate 110. The first intermediate layer 133 includes a plurality of first intermediate layer metal blocks 1331 arranged at intervals on the same layer. Each first bottom layer metal block 1311 is connected in series with the first top layer metal blocks 1321 on both sides of the corresponding gap via the first intermediate layer metal block 1331.

[0035] This structural design cleverly connects multiple first bottom layer metal blocks 1311, first top layer metal blocks 1321, and first intermediate layer metal blocks 1331 to form a series current path, increasing the heating area and heating uniformity of the heating structure 130. Simultaneously, the spaced distribution of the metal blocks facilitates heat dissipation and transfer, allowing the heat generated by the heating structure 130 to act more evenly on the structure under test 120, thus improving the accuracy of the lateral heat dissipation characteristic test.

[0036] Furthermore, the series path of the first bottom metal block 1311 and the first top metal block 1321 includes multiple parallel branches.

[0037] The arrangement of multiple parallel branches allows current to flow from the first bottom metal block 1311 to the first top metal block 1321 through different paths. Even if one branch fails, the others can still operate normally, improving the reliability of the heating structure 130. At the same time, multiple parallel branches can shunt the current, avoiding local overheating caused by excessive current in a single branch, further ensuring the uniformity of heating.

[0038] In one possible embodiment of this application, such as Figure 1 , Figure 2 and Figure 3 As shown, the multilayer second metal layer includes a second bottom layer 141, a second top layer 142, and a multilayer second intermediate layer 143 located between the second bottom layer 141 and the second top layer 142. The second bottom layer 141 is interconnected with the second top layer 142 via the multilayer second intermediate layer 143.

[0039] By dividing the multi-layered second metal layer into a second bottom layer 141, a second top layer 142, and multiple second intermediate layers 143 and interconnecting them, the current distribution of the temperature-sensing structure 140 becomes more reasonable, enabling it to more sensitively detect heat changes. This structural design facilitates precise detection of the temperature sensing process, improves the accuracy and reliability of the temperature sensing effect, provides accurate heat sensing data for lateral heat dissipation characteristic testing, and helps to obtain more accurate test results.

[0040] Furthermore, the second bottom layer 141 includes a plurality of second bottom layer metal blocks 1411 distributed at intervals in the same layer, the second top layer 142 includes a plurality of second top layer metal blocks 1421 distributed at intervals in the same layer, and there is a second gap 1422 between two adjacent second top layer metal blocks 1421. The plurality of second bottom layer metal blocks 1411 and the plurality of second gaps 1422 are directly corresponding to each other along the thickness direction of the substrate 110. The second intermediate layer 143 includes a plurality of second intermediate layer metal blocks 1431 arranged at intervals in the same layer. Each second bottom layer metal block 1411 is connected in series with the second top layer metal blocks 1421 on both sides of the corresponding gap via the second intermediate layer metal blocks 1431.

[0041] By cleverly connecting multiple second bottom metal blocks 1411, second top metal blocks 1421, and second intermediate metal blocks 1431, multiple series current paths are formed, increasing the temperature sensing area and uniformity of the temperature sensing structure 140. Simultaneously, the spaced distribution of the metal blocks facilitates a more comprehensive perception of heat changes, enabling the temperature sensing structure 140 to more sensitively capture the heat conducted from the structure under test 120, thus improving the accuracy of the lateral heat dissipation characteristic test.

[0042] In one possible embodiment of this application, such as Figure 1 , Figure 2 and Figure 3 As shown, a first lead is provided on the heating structure 130, and a second lead is provided on the temperature sensing structure 140. The first lead and the second lead are respectively connected to the substrate 110.

[0043] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor structure, characterized in that, include: Base; The structure under test, wherein the bottom surface of the structure under test is disposed on the substrate; An encapsulation layer covers the top and side surfaces of the structure under test, and the encapsulation layer has a heating structure and a temperature sensing structure disposed opposite to each other. The heating structure and the temperature sensing structure are arranged at intervals along a direction parallel to the surface of the substrate, and at least a portion of the structure under test is located between the heating structure and the temperature sensing structure.

2. The semiconductor structure according to claim 1, characterized in that, The encapsulation layer includes multiple interlayer dielectric layers stacked on the substrate, the heating structure includes multiple first metal layers, with adjacent first metal layers spaced apart and interconnected by the interlayer dielectric layers, and the temperature sensing structure includes multiple second metal layers, with adjacent second metal layers spaced apart and interconnected by the interlayer dielectric layers.

3. The semiconductor structure according to claim 2, characterized in that, The first metal layer and the second metal layer have the same number of layers.

4. The semiconductor structure according to claim 3, characterized in that, The structure under test includes multiple chips stacked on the substrate, wherein the number of stacked layers of the chips is greater than or equal to the number of layers of the first metal layer.

5. The semiconductor structure according to claim 2, characterized in that, The first metal layer includes a first bottom layer, a first top layer, and a multi-layer first intermediate layer located between the first bottom layer and the first top layer, wherein the first bottom layer is interconnected with the first top layer via the multi-layer first intermediate layer.

6. The semiconductor structure according to claim 5, characterized in that, The first bottom layer includes multiple first bottom layer metal blocks that are distributed in the same layer and spaced apart. The first top layer includes multiple first top layer metal blocks that are distributed in the same layer and spaced apart. There is a first gap between two adjacent first top layer metal blocks. The multiple first bottom layer metal blocks and the multiple first gaps are directly corresponding to each other along the thickness direction of the substrate. The first intermediate layer includes multiple first intermediate layer metal blocks that are distributed in the same layer and spaced apart. Each first bottom layer metal block is connected in series with the first top layer metal blocks on both sides of the corresponding gap through the first intermediate layer metal blocks.

7. The semiconductor structure according to claim 6, characterized in that, The series path of the first bottom metal block and the first top metal block includes multiple parallel branches.

8. The semiconductor structure according to claim 2, characterized in that, The multilayer second metal layer includes a second bottom layer, a second top layer, and a multilayer second intermediate layer located between the second bottom layer and the second top layer, wherein the second bottom layer is interconnected with the second top layer via the multilayer second intermediate layer.

9. The semiconductor structure according to claim 8, characterized in that, The second bottom layer includes multiple second bottom layer metal blocks that are distributed in the same layer and spaced apart. The second top layer includes multiple second top layer metal blocks that are distributed in the same layer and spaced apart. There is a second gap between two adjacent second top layer metal blocks. The multiple second bottom layer metal blocks and the multiple second gaps are directly corresponding to each other along the thickness direction of the substrate. The second intermediate layer includes multiple second intermediate layer metal blocks that are distributed in the same layer and spaced apart. Each second bottom layer metal block is connected in series with the second top layer metal blocks on both sides of the corresponding gap via the second intermediate layer metal blocks.

10. The semiconductor structure according to claim 1, characterized in that, The heating structure is provided with a first lead, and the temperature sensing structure is provided with a second lead, which are respectively connected to the substrate.

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