Integrated chip

Abstract

This invention provides an integrated chip. The integrated chip includes a first chip and a second chip bonded to the first chip. The first chip includes a first substrate, a first transistor along the first substrate, a first interconnect above the first transistor, and a first bonding pad above the first interconnect. The second chip includes a second substrate, a second transistor along the second substrate, a second interconnect below the second transistor, and a second bonding pad below the second interconnect. The second bonding pad is bonded to the first bonding pad. The first chip also includes a trench capacitor above the first interconnect and below the first bonding pad. The trench capacitor includes a bottom electrode, a top electrode, and an insulating layer between the bottom electrode and the top electrode. The first bonding pad extends from the second bonding pad to the top electrode of the trench capacitor.

Description

Technical Field

[0001] This utility model relates to an integrated chip. Background Technology

[0002] Many modern integrated chips include transistors and passive components. Examples of passive components include capacitors, resistors, inductors, and varactor diodes. Passive components are widely used to control integrated chip characteristics such as gain and time constant. Some passive components include integrated passive devices (IPDs). An IPD is a collection of one or more passive components embedded in a single unit and packaged as an integrated circuit (IC). Utility Model Content

[0003] This invention provides an integrated chip, comprising: a first chip including a first semiconductor substrate, a first transistor along the first semiconductor substrate, a first conductive interconnect above the first transistor, and a first bonding pad above the first conductive interconnect; and a second chip bonded to the first chip, the second chip including a second semiconductor substrate, a second transistor along the second semiconductor substrate, a second conductive interconnect below the second transistor, and a second bonding pad below the second conductive interconnect, wherein the second bonding pad is bonded to the first bonding pad, the first chip further including a trench capacitor above the first conductive interconnect and below the first bonding pad, the trench capacitor including a bottom electrode, a top electrode, and an insulating layer between the bottom electrode and the top electrode, wherein the first bonding pad extends from the second bonding pad to the top electrode of the trench capacitor.

[0004] This invention provides an integrated chip, comprising: a first metal interconnect over a first semiconductor substrate; a first dielectric layer over the first metal interconnect; a trench capacitor extending through and over the first dielectric layer, the trench capacitor including a bottom electrode over the first metal interconnect, a top electrode over the bottom electrode, and an insulating layer between the top electrode and the bottom electrode; a first etch stop layer over the trench capacitor; a first bonding dielectric layer over the first etch stop layer; a first bonding pad over the trench capacitor and extending through the first bonding dielectric layer and the first etch stop layer; a second bonding dielectric layer over and bonded to the first bonding dielectric layer; a second bonding pad over the first bonding pad, the second bonding pad extending through the second bonding dielectric layer; and a second semiconductor substrate over the second bonding pad, wherein the upper surface of the first bonding pad is bonded to the lower surface of the second bonding pad, and wherein the lower surface of the first bonding pad is located on the top electrode of the trench capacitor. Attached Figure Description

[0005] The best understanding of the features of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0006] Figure 1 This illustration shows cross-sectional views of some embodiments of an integrated chip in a first bonding structure that includes a trench capacitor.

[0007] Figures 2 to 5 illustrate Figure 1 Cross-sectional views of some embodiments of the integrated chip portion.

[0008] Figure 6 illustrate Figure 1 Cross-sectional views of some other embodiments of integrated chips.

[0009] Figures 7 to 8 illustrate Figure 6 Cross-sectional views of some embodiments of the integrated chip portion.

[0010] Figure 9 illustrate Figure 1 Cross-sectional views of some other embodiments of integrated chips.

[0011] Figure 10 illustrate Figure 1 Cross-sectional views of some other embodiments of integrated chips.

[0012] Figures 11 to 12 illustrate Figure 10Cross-sectional views of some embodiments of the integrated chip portion.

[0013] Figures 13 to 42 Cross-sectional views illustrating some embodiments of a method for forming an integrated chip containing trench capacitors in a first bonding structure.

[0014] Figure 43 Flowcharts illustrating some embodiments of a method for forming an integrated chip containing trench capacitors in a bonding structure. Detailed Implementation

[0015] This disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of explanation, this document may use spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar expressions to describe the relationship between one device or feature shown in the figures and another device or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein can be interpreted accordingly.

[0017] An integrated chip includes a first chip and a second chip bonded to the first chip. The first chip includes a first transistor along a first semiconductor substrate, a first interconnect above and coupled to the first transistor, and a first bonding structure above the first interconnect. The second chip includes a second bonding structure above and bonded to the first bonding structure, a second conductive interconnect above the second bonding structure, a second semiconductor substrate above the second interconnect, a photodetector along the second semiconductor substrate, and a second transistor along the second semiconductor substrate. In some integrated chips, the second transistor is a transfer transistor, which includes a transfer gate located between a floating diffusion region and the photodetector.

[0018] The first chip also includes a trench capacitor. In some integrated chips, the trench capacitor is located below the first bonding structure, and a thick metal interconnect is configured and coupled between the top electrode of the trench capacitor and the first bonding structure. One challenge with these integrated chips is that the thick metal interconnect can increase the parasitic capacitance of the floating diffusion region of the second chip. Therefore, the performance of the integrated chip may be degraded. For example, the conversion gain of the photodetector may decrease and / or the noise of the photodetector may increase. Furthermore, the cost of forming the integrated chip may increase due to the thick metal interconnect between the trench capacitor and the first bonding structure.

[0019] In the various embodiments disclosed herein, the trench capacitor is located within the first bonding structure, and the first chip does not have thick metal interconnects. By configuring the trench capacitor within the bonding structure and removing the thick metal interconnects, the parasitic capacitance of the floating diffusion region can be reduced. Therefore, the performance of the integrated chip can be improved. For example, the conversion gain of the integrated chip may be improved and / or the noise of the integrated chip may be reduced. Furthermore, by removing the thick metal interconnects between the trench capacitor and the first bonding structure, the cost of forming the integrated chip can be reduced. Moreover, removing large interconnects allows for a reduction in the spacing of the integrated chip.

[0020] Figure 1 A cross-sectional view 100 of an integrated chip is shown, illustrating a trench capacitor 135 included in a first bonding structure 186 in some embodiments.

[0021] The integrated chip includes a first chip 102 and a second chip 104 bonded over the first chip 102. The first chip 102 includes a first semiconductor substrate 106 and a plurality of first transistors (e.g., transistors 108 and 110) along the first semiconductor substrate 106. A first dielectric structure 118 comprising a plurality of dielectric layers and a plurality of etch stop layers is located over the first semiconductor substrate 106. A plurality of first conductive interconnects (e.g., contacts 120, 121, conductive lines 122, 123, 126, 127, and conductive vias 124, 125) are located over the first semiconductor substrate 106 and within the first dielectric structure 118.

[0022] A first bonding structure 186 is located above the first dielectric structure 118 and the first conductive interconnects (120 to 127). The first bonding structure 186 includes a first bonding dielectric structure 128, a plurality of first bonding contacts (e.g., bonding contact 130), and a plurality of first bonding pads (e.g., bonding pads 132 and 134). The first bonding dielectric structure 128 includes one or more dielectric layers and one or more etch stop layers. The bonding contact 130 is located within the first bonding dielectric structure 128 and extends from the bonding pad 134 to the conductive line 127. Bonding pads 134 and 132 are located within the first bonding dielectric structure 128.

[0023] The second chip 104 includes an image sensor along a second semiconductor substrate 164. The image sensor includes a plurality of photodetectors 178 in the second semiconductor substrate 164 and a plurality of transfer gate transistors (e.g., transfer gate transistors 160 and 162) along the second semiconductor substrate 164. Transfer gate transistors 160 and 162 include gate electrodes 170 located between a photodiode region 166 and a floating diffusion region 168. A second dielectric structure 144, comprising a plurality of dielectric layers and a plurality of etch stop layers, is located beneath the second semiconductor substrate 164. A plurality of second conductive interconnects (e.g., contacts 158, 159, conductive lines 153, 154, 156, 157, and conductive vias 155) are located beneath the second semiconductor substrate 164 and within the second dielectric structure 144.

[0024] The second bonding structure 188 is located below the second dielectric structure 144 and the second conductive interconnects (153 to 159). The second bonding structure 188 includes a second bonding dielectric structure 142, a plurality of second bonding contacts (e.g., bonding contacts 150 and 152), and a plurality of second bonding pads (e.g., bonding pads 146 and 148). The second bonding dielectric structure 142 includes one or more dielectric layers and one or more etch stop layers. The bonding contacts 150 and 152 are located within the second bonding dielectric structure 142 and extend from the bonding pads 146 and 148 to the conductive lines 153 and 154, respectively. The bonding pads 146 and 148 are located within the second bonding dielectric structure 142.

[0025] First chip 102 and second chip 104 are bonded together along bonding interface 180. For example, second bonding dielectric structure 142 and first bonding dielectric structure 128 are bonded together along bonding interface 180. Bonding pad 132 and bonding pad 146 are bonded together along bonding interface 180. Bonding pad 134 and bonding pad 148 are bonded together along bonding interface 180.

[0026] The first chip 102 also includes a trench capacitor 135 located within a first bonding structure 186. The trench capacitor 135 is located within a bonding contact layer within a first bonding dielectric structure 128. For example, the trench capacitor 135 is located above the conductive interconnects (120 to 127) of the first chip 102 and below the bonding pads of the first chip 102, and is laterally spaced from the bonding contacts of the first chip 102. The trench capacitor 135 includes a bottom electrode 136, a top electrode 140, and an insulating layer 138 located between the bottom electrode 136 and the top electrode 140. The bottom electrode 136 directly contacts the conductive line 126. The top electrode 140 directly contacts the bonding pad 132. The bonding pad 132 extends from the top electrode 140, through the first bonding dielectric structure 128, and reaches the bonding pad 146.

[0027] By configuring the trench capacitor 135 within the first bonding structure 186 in the bonding contact layer, the performance of the integrated chip can be improved. For example, the current path length from the floating diffusion region 168 on the second chip 104 to the transistor 110 on the first chip 102 can be reduced. Reducing the current path length can reduce the parasitic capacitance of the floating diffusion region 168. Reducing parasitic capacitance can reduce noise and improve the conversion gain of the image sensor on the second chip 104.

[0028] Furthermore, by configuring the trench capacitor 135 within the first bonding structure 186 in the bonding contact layer, the cost of forming an integrated chip can be reduced. For example, by forming the trench capacitor 135 within the first bonding structure 186, instead of forming a thick interconnect between the trench capacitor 135 and the first bonding structure 186, the amount of conductive material required to form the integrated chip can be reduced, the amount of mask required to form the integrated chip can be reduced, and / or the time required to form the integrated chip can be reduced.

[0029] Furthermore, by avoiding the formation of large interconnects between the trench capacitor 135 and the first bonding structure 186, the spacing of the integrated chips can be reduced.

[0030] In some embodiments, transistors 108, 110 of the first chip 102 are pixel transistors (e.g., source follower transistors, reset transistors, select transistors, or the like) corresponding to photodetector 178 of the second chip 104, and are coupled to the photodetector via some first interconnects (120 to 127), some second interconnects (153 to 159), and junction structures 186, 188. In some other embodiments, the second chip 104 includes pixel transistors 182, 184 (e.g., source follower transistors, reset transistors, select transistors, or the like) corresponding to (and coupled to) photodetector 178 along the second semiconductor substrate 164 and located next to transmission gate transistors 160, 162. In some such embodiments, the first chip 102 is an application-specific integrated circuit (ASIC) chip (e.g., transistors 108, 110 are ASIC transistors), and the integrated chip comprises two chips (e.g., two wafers, two dies, etc.) stacked together.

[0031] In some embodiments, transistors 108, 110 include source / drain regions 112 and gate electrodes 114. The source / drain regions may refer to either the source or the drain, and may be referred to individually or jointly depending on the context. In some embodiments, a shallow trench isolation structure 116 is located between the transistors of the first chip 102. In some embodiments, a deep trench isolation structure 172 is located between the photodetectors 178 of the second chip 104. A color filter 174 and a microlens 176 are located above the photodetectors 178. In some embodiments, a monochrome filter 174 and a single microlens 176 are located above two or more photodetectors 178. In some other embodiments, such as Figure 9 As shown, each photodetector 178 has a corresponding color filter 174 and microlens 176.

[0032] In some embodiments, the first semiconductor substrate 106 and / or the second semiconductor substrate 164 comprises silicon or some other suitable material. In some embodiments, the dielectric layer and etch stop layer of the first dielectric structure 118 and / or the second dielectric structure 144 comprise silicon dioxide, silicon nitride, silicon carbide, aluminum oxide, hafnium oxide, or some other suitable material. In some embodiments, the conductive interconnects (120 to 127) and (153 to 159) comprise copper, tungsten, aluminum, or some other suitable material.

[0033] Figure 2 Show Figure 1 Cross-sectional view 200 of some embodiments of a portion of an integrated circuit chip.

[0034] The first bonding dielectric structure 128 includes a first etch stop layer 204 on top of the first dielectric structure 118, a first dielectric layer 206 on top of the first etch stop layer 204, a second etch stop layer 208 on top of the first dielectric layer 206, a second dielectric layer 210 on top of the second etch stop layer 208, a third etch stop layer 212 on top of the second etch stop layer 208 and within the second dielectric layer 210, and a first bonding dielectric layer 222 on top of the second dielectric layer 210. The first etch stop layer 204 extends along the top of the first dielectric structure 118 and the conductive lines 126, 127. In some embodiments, the etch stop layers 208 and 212 contain a dielectric different from that of the dielectric layers 206 and 210. In some embodiments, the first bonding dielectric layer 222 contains a dielectric different from that of the dielectric layers 206, 210 and the etch stop layers 208, 212.

[0035] A bonding contact 130 extends vertically from the conductive line 127 through the first etch stop layer 204 and the first dielectric layer 206 to the bonding pad 134. A trench capacitor 135 extends vertically through the second etch stop layer 208, the first dielectric layer 206, and the first etch stop layer 204. A bottom electrode 136 extends horizontally along the top surface of the second etch stop layer 208 and the top surface of the conductive line 126. The bottom electrode 136 extends vertically along the sidewalls of the etch stop layer 208, the sidewalls of the dielectric layer 206, and the sidewalls of the etch stop layer 204. An insulating layer 138 extends horizontally along the top surface and upper surface of the bottom electrode 136 and extends vertically along the sidewalls of the bottom electrode. A top electrode 140 extends horizontally along the top surface and upper surface of the insulating layer 138 and extends vertically along the sidewalls of the insulating layer 138. The outermost sidewall of the top electrode 140 is laterally offset from the outermost sidewall of the bottom electrode 136 and the outermost sidewall of the insulating layer 138. A third etch stop layer 212 extends from the first outermost sidewall of the top electrode 140 to the second outermost sidewall of the top electrode 140, extending along the top surface of the top electrode 140. A second dielectric layer 210 is located above the trench capacitor 135 and on opposite sides of the upper portion of the trench capacitor 135.

[0036] Bonding pad 134 extends from bonding contact 130 through second etch stop layer 208, second dielectric layer 210 and first bonding dielectric layer 222 to bonding pad 148. Bonding pad 132 extends from top electrode 140 through third etch stop layer 212, second dielectric layer 210 and first bonding dielectric layer 222 to bonding pad 146.

[0037] The second bonding dielectric structure 142 includes a second bonding dielectric layer 224, a third dielectric layer 214 above the second bonding dielectric layer 224, a fourth etch stop layer 216 above the third dielectric layer 214, a fourth dielectric layer 218 above the fourth etch stop layer 216, and a fifth etch stop layer 220 above the fourth dielectric layer 218. In some embodiments, the etch stop layer 216 contains a dielectric different from that of dielectric layers 214 and 218. In some embodiments, the second bonding dielectric layer 224 contains a dielectric different from that of dielectric layers 214, 218, and the etch stop layer 216.

[0038] Bonding pad 146 extends from bonding pad 132 through second bonding dielectric layer 224, dielectric layer 214 and etch stop layer 216 to bonding contact 150. Bonding pad 148 extends from bonding pad 134 through second bonding dielectric layer 224, dielectric layer 214 and etch stop layer 216 to bonding contact 152.

[0039] Bonding contact 150 extends from bonding pad 146 through dielectric layer 218 and etch stop layer 220 to conductive line 153. Bonding contact 152 extends from bonding pad 148 through dielectric layer 218 and etch stop layer 220 to conductive line 154.

[0040] Figure 3 illustrate Figure 2 Cross-sectional view 300 of some other embodiments of the IC chip.

[0041] In some embodiments, the bottom electrode 136 of the trench capacitor 135 extends below the etch stop layer 204 into the conductive line 126, as shown by dashed line 302. Similarly, in some embodiments, the bonding contact 130 extends below the etch stop layer 204 into the conductive line 127, as shown by dashed line 304.

[0042] In some embodiments, the bottom surface of dielectric layer 210 is located on the top surface of etch stop layer 208. In some other embodiments, the bottom surface of dielectric layer 210 is located on the upper surface of etch stop layer 208, which is lower than the top surface of etch stop layer 208. In some embodiments, the first bonding dielectric structure 128 further includes a dielectric layer 306 located above insulating layer 138 and bottom electrode 136, along the outermost sidewall of top electrode 140 and etch stop layer 212. Dielectric layer 210 is located above and on opposite sides of dielectric layer 306. In some embodiments, the bottom surface of dielectric layer 306 is located on the top surface of insulating layer 138. In some other embodiments, the bottom surface of dielectric layer 306 is located on the upper surface of insulating layer 138, which is lower than the top surface of insulating layer 138. In some embodiments, dielectric layer 306 contains a dielectric different from that of etch stop layer 208 and etch stop layer 212.

[0043] In some embodiments, bonding pad 132 extends below etch stop layer 212 into top electrode 140, as shown by dashed line 308. In some embodiments, bonding pad 134 extends below etch stop layer 208 into dielectric layer 206. In some embodiments, bonding pad 134 and bonding contact 130 are formed together using a dual damascene process and contain the same material.

[0044] In some embodiments, any one of dielectric layers 206, 210, 306, 214, and 218 comprises silicon dioxide or other suitable materials. In some embodiments, etch stop layer 204 and / or etch stop layer 220 comprises silicon carbide or other suitable materials. In some embodiments, any one of etch stop layers 208, 212, and 216 comprises silicon nitride or other suitable materials. In some embodiments, the first bonding dielectric layer 222 and / or the second bonding dielectric layer 224 comprises silicon oxynitride or other suitable materials.

[0045] In some embodiments, any one of the engagement contact 130, engagement contact 150, engagement contact 152, engagement pad 132, engagement pad 134, engagement pad 146, and engagement pad 148 comprises copper or other suitable material.

[0046] In some embodiments, the bottom electrode 136 comprises a different conductive material than the top electrode 140. In some embodiments, the bottom electrode 136 comprises titanium nitride, tantalum, tantalum nitride, a combination thereof, or other suitable materials. In some embodiments, the top electrode 140 comprises titanium nitride or other suitable materials. In some embodiments, the insulating layer 138 comprises a high-k dielectric (e.g., alumina, hafnium oxide, zirconium oxide, or the like) or other suitable materials.

[0047] Figure 4 Draw Figure 1 A cross-sectional view 400 of some other embodiments of a portion of an integrated circuit chip.

[0048] The first bonding dielectric structure 128 includes an etch stop layer 402 located between dielectric layers 206 and 210. The etch stop layer 402 extends along the top surface of dielectric layer 206 and covers the top portion of trench capacitor 135. For example, the etch stop layer 402 covers the outermost walls of bottom electrode 136, insulating layer 138, and top electrode 140, and further covers the top surface of insulating layer 138 and top surface of top electrode 140. Bonding pad 132 extends through the etch stop layer 402 to top electrode 140. Bonding pad 134 extends through the etch stop layer 402 to dielectric layer 206 and bonding contact 130. In some embodiments, the etch stop layer 402 contains a dielectric different from that of dielectric layers 206 and 210.

[0049] Figure 5 Draw Figure 4 Cross-sectional view 500 of some other embodiments of the IC chip.

[0050] In some embodiments, the bottom surface of the etch stop layer 402 is located on the top surface of the dielectric layer 206. In some other embodiments, the bottom surface of the etch stop layer 402 is located on the upper surface of the dielectric layer 206, which is lower than the top surface of the dielectric layer 206 on opposite sides of the trench capacitor 135.

[0051] In some embodiments, the first bonding dielectric structure 128 further includes an etch stop layer 502 located on the top surface of the top electrode 140 and a dielectric layer 504 covering the top electrode 140 and the outermost sidewall of the dielectric layer 504. In some embodiments, the bottom surface of the dielectric layer 504 is located on the top surface of the insulating layer 138. In some other embodiments, the bottom surface of the dielectric layer 504 is located on the upper surface of the insulating layer 138, which is lower than the top surface of the insulating layer 138. The etch stop layer 402 covers the sidewalls of the dielectric layer 504, the top surface of the dielectric layer 504, and the top surface of the etch stop layer 502. In some embodiments, the etch stop layer 502 contains a dielectric different from that of the dielectric layers 206 and 210. In some embodiments, the dielectric layer 504 contains a dielectric different from that of the etch stop layer 402 and the etch stop layer 502.

[0052] Bonding pad 132 extends through etch stop layer 402 and etch stop layer 502 to top electrode 140. In some embodiments, bonding pad 132 extends below etch stop layer 502 into top electrode 140, as shown by dashed line 506. In some embodiments, bonding pad 134 extends below etch stop layer 402 into dielectric layer 206.

[0053] In some embodiments, any one of the etch stop layer 402, etch stop layer 502, and dielectric layer 504 comprises silicon nitride or other suitable material.

[0054] Figure 6 Draw Figure 1 A cross-sectional view 600 of some embodiments of an integrated circuit chip, wherein a trench capacitor 135 is located in a second chip 104. Figures 7 to 8 Draw Figure 6 Cross-sectional views 700 and 800 of some embodiments of a portion of an integrated circuit chip.

[0055] The trench capacitor 135 is located on the second chip 104 and within the second bonding dielectric structure 142. The trench capacitor 135 is relative to... Figure 1 With a "flipped" orientation, the bottom electrode 136 is positioned above the insulating layer 138 and the top electrode 140. The conductive line 153 is located on the bottom electrode 136. The top electrode 140 is located on the bonding pad 146 and laterally spaced from the bonding contact 152. The bonding contact 602 extends from the bonding pad 132 to the conductive line 126.

[0056] The trench capacitor 135 is located in the dielectric layer 214 and passes through the etch stop layer 216, the dielectric layer 218, and the etch stop layer 220. The second bonding dielectric structure 142 includes the dielectric layer 306 and the etch stop layer 212 located in the dielectric layer 214.

[0057] In some embodiments, Figure 6 The integrated chip also includes a second trench capacitor located on the first chip 102 (e.g., such as...). Figure 1 As shown), the integrated chip includes a trench capacitor on a first chip 102 and a trench capacitor on a second chip 104. In some embodiments, the second trench capacitor (located on the first chip 102) is coupled to a trench capacitor 135 (located on the second chip 104). For example, in some embodiments, a bonding pad 132 is located on the top electrode of the second trench capacitor (e.g., as shown). Figure 1 As shown), bonding pads 132 and 146 couple the top electrodes of the two capacitors together. In some other embodiments, the second trench capacitor is not directly coupled to the trench capacitor 135 at the bonding interface 180. For example, in some embodiments, bonding pad 134 is located on the top electrode of the second trench capacitor.

[0058] In some embodiments, transistors 108 and 110 of the first chip 102 are pixel transistors corresponding to (and coupled to) the photodetector 178 of the second chip 104. In some other embodiments, the second chip 104 includes pixel transistors 182 and 184 corresponding to (and coupled to) the photodetector 178 along the second semiconductor substrate 164. In some such embodiments, the first chip 102 is an application-specific integrated circuit (ASIC) chip (e.g., transistors 108 and 110 are ASIC transistors), and the integrated chip comprises two chips (e.g., two wafers, two dies, etc.) stacked together.

[0059] Figure 9 Draw Figure 1 A cross-sectional view 900 of some embodiments of an integrated circuit chip, wherein a third chip 902 is bonded to a first chip 102.

[0060] A first chip 102 is situated on a third chip 902. The third chip 902 includes a third semiconductor substrate 904 and a plurality of third transistors (e.g., transistors 908) along the third semiconductor substrate 904. A third dielectric structure 910, comprising a plurality of dielectric layers and a plurality of etch stop layers, is situated on the third semiconductor substrate 904. A plurality of third conductive interconnects (e.g., contacts 912, conductive lines 914, and conductive vias) are situated on the third semiconductor substrate 904 and within the third dielectric structure 910. A third bonding dielectric structure 920 is situated on the third dielectric structure 910. A plurality of third bonding conductive pads (e.g., bonding pads 918) and a plurality of third bonding contacts (e.g., bonding contacts 916) are situated within the third bonding dielectric structure 920.

[0061] The first chip 102 also includes a fourth bonding dielectric structure 922 along the back side of the first semiconductor substrate 106, bonding pads 924 and bonding contacts 934 located in the bonding dielectric structure 922, a through-substrate via (TSV) 928 extending from a conductive interconnect 930 in the first dielectric structure 118 through the first semiconductor substrate 106 to the bonding contact 934, and a dielectric liner 926 surrounding the TSV 928. The bonding dielectric structure 922 is bonded to the bonding dielectric structure 920 along a bonding interface 932. The bonding pads 924 are bonded to the bonding pads 918 along the bonding interface 932.

[0062] In some embodiments, Figure 9 The integrated chip also includes a second trench capacitor on the second chip 104 (e.g., such as...). Figure 6 As shown), the integrated chip includes trench capacitors on the first chip 102 and trench capacitors on the second chip 104.

[0063] Figure 10 Draw Figure 1 A cross-sectional view 1000 of some embodiments of an integrated circuit chip, wherein a bonding pad 1002 is located on the bottom electrode 136 of a trench capacitor 135. Figures 11 to 12 Draw Figure 10 Cross-sectional views 1100 and 1200 of some embodiments of an integrated circuit chip.

[0064] The first chip 102 includes a bonding pad 1002. The bonding pad 1002 is laterally spaced between bonding pads 132 and 134. The second chip 104 includes a bonding pad 1004, a conductive interconnect 1008 located on the bonding pad 1004, and a bonding contact 1006 extending from the bonding pad 1004 to the conductive interconnect 1008.

[0065] Bonding pad 1002 is bonded to bonding pad 1004 along bonding interface 180. Bonding pad 1002 extends from bonding pad 1004 through first bonding dielectric layer 222, first bonding dielectric structure 128 and insulating layer 138 to the bottom electrode 136 of trench capacitor 135. Therefore, both electrodes of trench capacitor 135 on first chip 102 are coupled to interconnect structure on second chip 104.

[0066] Figures 13 to 42 Cross-sectional views 1300 to 4200 illustrate some embodiments of a method for forming an integrated chip including a trench capacitor 135 in a first bonding structure 186. Although Figures 13 to 42 It describes the method, but it should be understood that... Figures 13 to 42 The structure revealed in the paper is not limited to this method, but can exist independently of the method.

[0067] like Figure 13 As shown in cross-sectional view 1300, a plurality of transistors (e.g., transistors 108 and 110), including source / drain regions 112 and gate electrodes 114, are formed on a first semiconductor substrate 106. Shallow trench isolation (STI) structures 116 are formed between the transistors.

[0068] like Figure 14 As shown in the cross-sectional view 1400, a first dielectric structure 118 and a plurality of first conductive interconnects (e.g., contacts 120, 121, conductive lines 122, 123, 126, 127 and conductive vias 124, 125) are formed on a first semiconductor substrate 106.

[0069] Figures 15 to 26 Cross-sectional views 1500 to 2600 illustrating some embodiments of a method of forming a first bonding structure 186 over a first dielectric structure 118 and a first conductive interconnect (120 to 127).

[0070] like Figure 15As shown in the cross-sectional view 1500, an etch stop layer 204 is deposited over the first dielectric structure 118 and conductive lines 126, 127. A dielectric layer 206 is deposited over the etch stop layer 204. An etch stop layer 208 is deposited over the dielectric layer 206. In some embodiments, conductive lines 126, 127 comprise copper, aluminum, tungsten, or other suitable materials. In some embodiments, the etch stop layer 204 comprises silicon carbide or other suitable materials and is deposited using a chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) process. In some embodiments, the dielectric layer 206 comprises silicon dioxide or other suitable materials and is deposited using a CVD, PVD, ALD, or other suitable process. In some embodiments, the etch stop layer 208 comprises silicon nitride or other suitable materials and is deposited using a CVD, PVD, ALD, or other suitable process.

[0071] like Figure 16 As shown in the cross-sectional view 1600, etch stop layer 208, dielectric layer 206, and etch stop layer 204 are etched to form trench 1602 therein. In some embodiments, a masking layer 1604 (e.g., a photoresist layer, a hard masking layer, or the like) is formed on etch stop layer 208 and etched according to masking layer 1604. In some embodiments, etching includes dry etching processes (e.g., plasma etching processes, reactive ion etching processes, ion beam etching processes, or the like) or other suitable processes. In some embodiments, etching extends into conductive lines 126, as shown by the dashed lines below trench 1602. In some embodiments, the masking layer is removed after etching.

[0072] like Figure 17 As shown in cross-sectional view 1700, bottom electrode 136 is deposited on etch stop layer 208 and in trench 1602. Insulating layer 138 is deposited on bottom electrode 136 and in trench 1602. Top electrode 140 is deposited on insulating layer 138 and in trench 1602. Etch stop layer 212 is deposited on top electrode 140.

[0073] In some embodiments, the bottom electrode 136 comprises titanium nitride, tantalum, tantalum nitride, a combination thereof, or other suitable materials, and is deposited using CVD, PVD, ALD, or other suitable processes. In some embodiments, the insulating layer 138 comprises a high dielectric constant (e.g., alumina, hafnium oxide, zirconium oxide, or the like) or other suitable materials, and is deposited using CVD, PVD, ALD, or other suitable processes. In some embodiments, the top electrode 140 comprises titanium nitride or other suitable materials and is deposited using CVD, PVD, ALD, or other suitable processes. In some embodiments, the etch stop layer 212 comprises silicon nitride or other suitable materials and is deposited using CVD, PVD, ALD, or other suitable processes.

[0074] like Figure 18 As shown in the cross-sectional view 1800, the etch stop layer 212 and the top electrode 140 are etched to define the top electrode 140. In some embodiments, a mask layer 1802 (e.g., a photoresist layer, a hard mask layer, or the like) is formed on the etch stop layer 212 and etched according to the mask layer 1802. In some embodiments, the etching includes a dry etching process or other suitable process. An insulating layer 138 acts as an etch stop layer during etching (e.g., preventing the etching from reaching the bottom electrode 136). In some embodiments, the etching extends into the insulating layer 138 but does not penetrate the insulating layer 138.

[0075] like Figure 19 As shown in the cross-sectional view 1900, dielectric layer 306 is conformally deposited on insulating layer 138 and etch stop layer 212. In some embodiments, dielectric layer 306 comprises silicon dioxide or other suitable material and is deposited by CVD, PVD, ALD or other suitable processes.

[0076] like Figure 20As shown in the cross-sectional view 2000, the dielectric layer 306, insulating layer 138, and bottom electrode 136 are etched to define the insulating layer 138 and the bottom electrode 136. The etching includes a self-aligned etching process in which the bottom electrode 136 and the insulating layer 138 are etched on opposite sides of the top electrode 140 without the use of a masking layer. For example, the thickness of the dielectric layer 306 along the sidewalls of the top electrode 140 and the etch stop layer 212 is greater than the thickness along the top of the etch stop layer 212 and the top of the insulating layer 138 where the dielectric layer 306 extends "stepped" from the insulating layer 138 to the etch stop layer 212. Therefore, after the etching process, these "stepped" regions of the dielectric layer 306 remain on the insulating layer 138 and the bottom electrode 136 along the sidewalls of the top electrode 140 and the etch stop layer 212 due to the increased thickness of these regions. As a result, the insulating layer 138 and the bottom electrode 136 are self-aligned with the top electrode 140.

[0077] During etching, etch stop layer 212 prevents etching from reaching the top electrode 140, and etch stop layer 208 prevents etching from reaching the dielectric layer 206. In some embodiments, etching extends into etch stop layers 212 and etch stop layers 208 but does not penetrate these layers. In some embodiments, etching includes a dry etching process or other suitable process.

[0078] like Figure 21 As shown in cross-sectional view 2100, dielectric layer 210 is deposited on etch stop layer 208, dielectric layer 306, and etch stop layer 212. In some embodiments, dielectric layer 210 comprises silicon dioxide or other suitable material and is deposited by CVD, PVD, ALD, or other suitable processes. In some embodiments, a planarization process (e.g., chemical mechanical planarization (CMP) or other suitable process) is performed on dielectric layer 210 after deposition.

[0079] In addition, a first bonding dielectric layer 222 is deposited on dielectric layer 210. In some embodiments, the first bonding dielectric layer 222 comprises silicon oxynitride or other suitable materials and is deposited by CVD, PVD, ALD or other suitable processes.

[0080] like Figure 22As shown in cross-sectional view 2200, a bonding dielectric layer 222, a dielectric layer 210, an etch stop layer 208, and a dielectric layer 206 are etched to form an opening 2202 over the conductive line 127. In some embodiments, a masking layer 2204 (e.g., a photoresist layer, a hard masking layer, or the like) is formed on the bonding dielectric layer 222, and etching is performed according to the masking layer 2204. In some embodiments, the etching includes a dry etching process or other suitable process. The etch stop layer 204 prevents the etching from reaching the conductive line 127. In some embodiments, the etching extends into the etch stop layer 204 but does not penetrate the etch stop layer 204.

[0081] like Figure 23 As shown in cross-sectional view 2300, the bonding dielectric layer 222 and dielectric layer 210 are etched to widen the upper portion of the opening 2202 and form the opening 2302 above the trench capacitor 135. In some embodiments, a masking layer 2304 (e.g., a photoresist layer, a hard masking layer, or the like) is formed on the bonding dielectric layer 222 and in the lower portion of the opening 2202, and etching is performed according to the masking layer 2304. In some embodiments, the etching includes a dry etching process or other suitable process. An etch stop layer 208 and masking layer 2304 prevent etching from extending into the dielectric layer 206 at the opening 2202. An etch stop layer 212 prevents etching from reaching the top electrode 140 at the opening 2302. In some embodiments, the etch extends into the etch stop layer 208 at the opening 2202 but does not penetrate the etch stop layer 208. In some embodiments, the etch extends into the etch stop layer 212 at the opening 2302 but does not penetrate the etch stop layer 212.

[0082] like Figure 24 As shown in cross-sectional view 2400, etch stop layer 204 is etched (e.g., etched away by subsequent etch stop layers) to increase the depth of opening 2202 to expose conductive line 127. Furthermore, etch stop layer 212 is etched (e.g., etched away simultaneously using the same etch stop layer) to increase the depth of opening 2302 to expose top electrode 140. In some embodiments, the etching extends into the lower portion of conductive line 127 in opening 2202. In some embodiments, the etching penetrates etch stop layer 208 and extends into dielectric layer 206 in the upper portion of opening 2202. In some embodiments, the etching extends into top electrode 140 at opening 2302.

[0083] like Figure 25As shown in the cross-sectional view 2500, a conductive layer is deposited over the bonding dielectric layer 222 and in the openings 2202 and 2302 to form a bonding contact 130 in the lower portion of the opening 2202, a bonding pad 134 in the upper portion of the opening 2202, and a bonding pad 132 in the opening 2302. In some embodiments, the conductive layer comprises copper or other suitable material and is deposited by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or other suitable processes.

[0084] like Figure 26 As shown in the cross-sectional view 2600, a planarization process is performed on the conductive layer after deposition to remove the conductive layer above the bonding dielectric layer 222 and further define the bonding pads 132, 134. In some embodiments, the planarization process includes a chemical mechanical planarization process, a full-surface etching process, or other suitable processes.

[0085] Figures 27 to 39 Cross-sectional views 2700 to 3900 illustrating some other embodiments of the method of forming a first bonding structure 186 over a first dielectric structure 118 and a first conductive interconnect (120 to 127).

[0086] like Figure 27 As shown in the cross-sectional view 2700, an etch stop layer 204 is deposited over the dielectric structure 118 and the conductive lines 126, 127. Furthermore, a dielectric layer 206 is deposited over the etch stop layer 204.

[0087] like Figure 28 As shown in the cross-sectional view 2800, a dielectric layer 206 and an etch stop layer 204 are etched to form a trench 2802 therein, located above the conductive line 126. In some embodiments, a masking layer 2804 (e.g., a photoresist layer, a hard masking layer, or the like) is formed above the dielectric layer 206, and etching is performed against the masking layer 2804. In some embodiments, the etching extends into the conductive line 126.

[0088] like Figure 29 As shown in cross-sectional view 2900, a bottom electrode 136 is deposited over a dielectric layer 206 and in a trench 2802. An insulating layer 138 is deposited over the bottom electrode 136 and in the trench 2802. A top electrode 140 is deposited over the insulating layer 138 and in the trench 2802. An etch stop layer 502 is deposited over the top electrode 140. In some embodiments, the etch stop layer 502 comprises silicon nitride or other suitable material and is deposited by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or other suitable processes.

[0089] like Figure 30As shown in the cross-sectional view 3000, an etch stop layer 502 and a top electrode 140 are etched to define the top electrode 140. In some embodiments, a mask layer 3002 (e.g., a photoresist layer, a hard mask layer, or the like) is formed over the etch stop layer 502, and etching is performed against the mask layer 3002. In some embodiments, etching includes a dry etching process or other suitable process. An insulating layer 138 acts as an etch stop layer during etching to prevent etching from reaching the bottom electrode 136. In some embodiments, etching extends into the insulating layer 138 but does not penetrate the insulating layer 138.

[0090] like Figure 31 As shown in the cross-sectional view 3100, the dielectric layer 504 is conformally deposited over the insulating layer 138 and the etch stop layer 502. In some embodiments, the dielectric layer 504 comprises silicon nitride or other suitable materials and is deposited by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or other suitable processes.

[0091] like Figure 32 As shown in cross-sectional view 3200, dielectric layer 504, insulating layer 138, and bottom electrode 136 are etched to define the insulating layer 138 and bottom electrode 136 of the trench capacitor 135. The etching includes a self-aligned etching process, wherein the bottom electrode 136 and insulating layer 138 are etched on opposite sides of the top electrode 140 without a masking layer. For example, dielectric layer 504 has a significant thickness along the sidewalls of the top electrode 140 and the etch stop layer 502, extending in a "stepped" manner from above the insulating layer 138 to above the etch stop layer 502, being thicker than along the top of the etch stop layer 502 and along the top of the insulating layer 138. Therefore, due to the increased thickness in these regions, these "stepped" regions of dielectric layer 504 remain above the insulating layer 138 and bottom electrode 136 after etching, along the sidewalls of the top electrode 140 and the sidewalls of the etch stop layer 502. As a result, the insulating layer 138 and the bottom electrode 136 are self-aligned with the top electrode 140.

[0092] During etching, the etch stop layer 502 prevents etching from reaching the top electrode 140. In some embodiments, the etching extends into the etch stop layer 502 but does not penetrate it. In some other embodiments, the etching removes the etch stop layer 502 on the top electrode 140. In some embodiments, the etching extends into the dielectric layer 206 on the opposite side of the trench capacitor 135. In some embodiments, the etching includes a dry etching process or other suitable process.

[0093] like Figure 33As shown in cross-sectional view 3300, an etch stop layer 402 is deposited over dielectric layer 206, dielectric layer 504, and etch stop layer 502. In embodiments where the etch stop layer 502 is located over top electrode 140, the etch stop layer 402 increases the thickness of the etch stop layer over top electrode 140. In embodiments where the etch stop layer is removed from over top electrode 140 (e.g., by means of...), the etch stop layer 402 is deposited over top electrode 140. Figure 32 (As shown in the etch), etch stop layer 402 supplements the etch stop layer above top electrode 140. In some embodiments, etch stop layer 402 comprises silicon nitride or other suitable material and is deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable processes.

[0094] like Figure 34 As shown in the cross-sectional view 3400, dielectric layer 210 is deposited over etch stop layer 402. In some embodiments, a planarization process (e.g., chemical mechanical planarization or other suitable process) is performed on dielectric layer 210 after deposition. Furthermore, bonding dielectric layer 222 is deposited over dielectric layer 210.

[0095] like Figure 35 As shown in cross-sectional view 3500, bonding dielectric layer 222, dielectric layer 210, etch stop layer 402, and dielectric layer 206 are etched to form an opening 3502 over conductive line 127. In some embodiments, a masking layer 3504 (e.g., a photoresist layer, a hard masking layer, or the like) is formed over bonding dielectric layer 222, and etching is performed according to masking layer 3504. In some embodiments, etching includes a dry etching process or other suitable process. Etching stop layer 204 prevents etching from reaching conductive line 127. In some embodiments, etching extends into etch stop layer 204 but does not penetrate etch stop layer 204.

[0096] like Figure 36As shown in cross-sectional view 3600, the bonding dielectric layer 222 and dielectric layer 210 are etched to enlarge the upper portion of the opening 3502 and form the opening 3602 above the trench capacitor 135. In some embodiments, a masking layer 3604 (e.g., a photoresist layer, a hard masking layer, or the like) is formed above the bonding dielectric layer 222 and in the lower portion of the opening 3502, and etching is performed according to the masking layer 3604. In some embodiments, the etching includes a dry etching process or other suitable process. An etch stop layer 402 and the masking layer 3604 prevent etching from extending into the dielectric layer 206 at the opening 3502. The etch stop layer 402 prevents etching from reaching the top electrode 140 at the opening 3602. In some embodiments, the etching extends into the etch stop layer 402 at the opening 3502 but does not penetrate the etch stop layer 402. In some embodiments, the etching extends into the etch stop layer 402 at the opening 3602 but does not penetrate the etch stop layer 402 at the opening 3602.

[0097] like Figure 37 As shown in cross-sectional view 3700, etch stop layer 204 is etched (e.g., etched away by subsequent etch stop layers) to increase the depth of opening 3502 to expose conductive line 127. Furthermore, etch stop layers 402 and 502 are etched (e.g., etched away simultaneously using the same etch stop layers) to increase the depth of opening 3602 to expose top electrode 140. In some embodiments, the etch extends into conductive line 127 at the lower portion of opening 3502. In some embodiments, the etch penetrates etch stop layer 402 and extends into dielectric layer 206 at the upper portion of opening 3502. In some embodiments, the etch extends into top electrode 140 at opening 3602.

[0098] like Figure 38 As shown in the cross-sectional view 3800, a conductive layer is deposited above the bonding dielectric layer 222 and in the openings 3502 and 3602 to form a bonding contact 130 in the lower portion of the opening 3502, a bonding pad 134 in the upper portion of the opening 3502, and a bonding pad 132 in the opening 3602.

[0099] like Figure 39 As shown in the cross-sectional view 3900, a planarization process is performed on the conductive layer after deposition to remove the conductive layer above the bonding dielectric layer 222 and further define the bonding pads 132, 134. In some embodiments, the planarization process includes a chemical mechanical planarization process, a full-surface etching process, or other suitable processes.

[0100] like Figure 40 As shown in the cross-sectional view 4000, the second chip 104 is disposed on top of the first chip 102 such that the bonding pads of the first chip 102 and the bonding pads of the second chip 104 are aligned.

[0101] like Figure 41 As shown in the cross-sectional view 4100, the first bonding dielectric layer 222 and the second bonding dielectric layer 224 are bonded together by a fusion bonding process, a direct bonding process, or other suitable processes. In some embodiments, the bonding dielectric layers 222, 224 first undergo room temperature pre-bonding, followed by one or more subsequent annealing processes, wherein the bonding dielectric layers 222, 224 are heated to improve the bonding strength.

[0102] Furthermore, the bonding pads of the first chip 102 and the bonding pads of the second chip 104 are bonded together via a fusion bonding process, a direct bonding process, or other suitable processes. For example, bonding pads 132 and 146 are bonded together, and bonding pads 134 and 148 are bonded together. In some embodiments, the bonding pads are bonded together during an annealing process performed after pre-bonding of the bonding dielectric layers 222 and 224.

[0103] like Figure 42 As shown in the cross-sectional view 4200, in some embodiments, the third chip 902 is bonded to the back side of the first chip 102 via a fusion bonding process, a direct bonding process, or other suitable processes.

[0104] Figure 43 Flowcharts illustrating some embodiments of method 4300 for forming an integrated chip including trench capacitors in a bonding structure are provided. While method 4300 is illustrated and described as a series of actions or events, it should be understood that the illustrated order of these actions or events should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events illustrated and / or described herein. Furthermore, not all illustrated actions may require the implementation of one or more aspects or embodiments described herein. Moreover, one or more actions described herein may be performed in one or more independent actions and / or stages.

[0105] The first chip is formed in block 4302. Figures 13 to 14 The illustration shows cross-sectional views 1300 to 1400 corresponding to some embodiments of block 4302. Block 4302 includes blocks 4302a to 4302e.

[0106] In block 4302a, a transistor is formed along the semiconductor substrate. Figure 13 This describes a cross-sectional view 1300 corresponding to some embodiments of block 4302a.

[0107] In block 4302b, dielectric structures and interconnects are formed on the first semiconductor substrate. Figure 14 This describes a cross-sectional view 1400 corresponding to some embodiments of block 4302b.

[0108] In block 4302c, a bonding dielectric layer is formed on the dielectric structure. Figure 21 This describes a cross-sectional view 2100 corresponding to some embodiments of block 4302c. Figure 34 This describes a cross-sectional view 3400 corresponding to some other embodiments of block 4302c.

[0109] In block 4302d, trench capacitors and bonding contacts are formed on the interconnect. Figures 16 to 26 The illustration shows cross-sectional views 1600 to 2600 corresponding to some embodiments of block 4302d. Figures 28 to 39 The illustration shows cross-sectional views 2800 to 3900 corresponding to some other embodiments of block 4302d.

[0110] In block 4302e, a bonding pad is formed on the trench capacitor and the bonding contact. Figures 22 to 26 The illustration shows cross-sectional views 2200 to 2600 corresponding to some embodiments of block 4302e. Figures 35 to 39 The illustration shows cross-sectional views 3500 to 3900 corresponding to some embodiments of block 4302e.

[0111] In block 4304, the bonding dielectric layer and bonding pad of the first chip are bonded together with the bonding dielectric layer and bonding pad of the second chip. Figure 41 This describes a cross-sectional view 4100 corresponding to some embodiments of block 4304.

[0112] Therefore, in some embodiments, this disclosure relates to an integrated chip comprising a first chip and a second chip bonded to the first chip. The first chip includes a first semiconductor substrate, a first transistor along the first semiconductor substrate, a first conductive interconnect on the first transistor, and a first bonding pad on the first conductive interconnect. The second chip includes a second semiconductor substrate, a second transistor along the second semiconductor substrate, a second conductive interconnect under the second transistor, and a second bonding pad under the second conductive interconnect. The second bonding pad is bonded to the first bonding pad. The first chip also includes a trench capacitor on the first conductive interconnect and under the first bonding pad. The trench capacitor includes a bottom electrode, a top electrode, and an insulating layer between the bottom electrode and the top electrode. The first bonding pad extends from the second bonding pad to the top electrode of the trench capacitor.

[0113] In some embodiments, the bottom electrode of the trench capacitor extends from the insulating layer to the first conductive interconnect. In some embodiments, the first chip further includes a bonding contact laterally spaced from the trench capacitor, and a third bonding pad above the bonding contact and laterally spaced from the first bonding pad and the trench capacitor. In some embodiments, the bonding contact is in contact with the third bonding pad above the bottom of the trench capacitor and below the top of the trench capacitor, and the top electrode is in contact with the first bonding pad above the bottom of the third bonding pad and below the top of the third bonding pad. In some embodiments, the second chip further includes a photodetector along the second semiconductor substrate. In some embodiments, the chip further includes: a third chip bonded to the first chip, the third chip including a third semiconductor substrate, a third transistor along the third semiconductor substrate, a third conductive interconnect above the third transistor, and a third bonding pad above the third conductive interconnect, wherein the first chip further includes a fourth bonding pad between the first semiconductor substrate and the third chip, wherein the fourth bonding pad is bonded to the third bonding pad. In some embodiments, the first chip further includes a photodetector along the first semiconductor substrate.

[0114] In other embodiments, this disclosure relates to an integrated chip including a first metal interconnect on a first semiconductor substrate. A first dielectric layer is on the first metal interconnect. A trench capacitor extends through and onto the first dielectric layer. The trench capacitor includes a bottom electrode on the first metal interconnect, a top electrode on the bottom electrode, and an insulating layer between the top electrode and the bottom electrode. A first etch stop layer is above the trench capacitor. A first bonding dielectric layer is above the first etch stop layer. A first bonding pad is above the trench capacitor and extends through the first bonding dielectric layer and the first etch stop layer. A second bonding dielectric layer is above and bonded to the first bonding dielectric layer. A second bonding pad is above the first bonding pad. The second bonding pad extends through the second bonding dielectric layer. A second semiconductor substrate is above the second bonding pad. The upper surface of the first bonding pad is bonded to the lower surface of the second bonding pad. The lower surface of the first bonding pad is on the top electrode of the trench capacitor.

[0115] In some embodiments, the device further includes: a second metal interconnect laterally spaced from the first metal interconnect; a bonding contact above the second metal interconnect, laterally spaced from the trench capacitor, and extending through the first dielectric layer; a third bonding pad above the bonding contact, laterally spaced from the first bonding pad, and extending through the first bonding dielectric layer; and a fourth bonding pad above the third bonding pad, bonded to the third bonding pad, laterally spaced from the second bonding pad, and extending through the second bonding dielectric layer. In some embodiments, the trench capacitor extends from below the top of the bonding contact and below the bottom of the third bonding pad to above the top of the bonding contact and above the bottom of the third bonding pad, and the third bonding pad extends from below the top of the top electrode and below the bottom of the first bonding pad to above the top of the top electrode and above the bottom of the first bonding pad. In some embodiments, the first dielectric layer includes a first dielectric, the first etch stop layer includes a second dielectric different from the first dielectric, the first bonding dielectric layer includes a third dielectric different from both the first and second dielectrics, and the second bonding dielectric layer includes a fourth dielectric different from both the first and second dielectrics. In some embodiments, the first etch stop layer extends along the top surface of the top electrode, and the first bonding pad extends through the first etch stop layer to the top surface of the top electrode. In some embodiments, the system further includes: a second dielectric layer between the first dielectric layer and the first bonding dielectric layer and between the first etch stop layer and the first bonding dielectric layer, wherein the trench capacitor extends above the bottom of the second dielectric layer, and wherein the first bonding pad extends through the second dielectric layer; and a second etch stop layer between the first dielectric layer and the second dielectric layer, wherein the trench capacitor extends through the second etch stop layer and extends above the second etch stop layer. In some embodiments, the system further includes: a third dielectric layer extending laterally between the second dielectric layer and the top electrode, and extending laterally between the second dielectric layer and the first etch stop layer. In some embodiments, the device further includes: a second dielectric layer between the first etch stop layer and the first bonding dielectric layer, wherein the first etch stop layer is located between the first dielectric layer and the second dielectric layer, wherein the first etch stop layer is located between the second dielectric layer and the trench capacitor, wherein the trench capacitor extends above the bottom of the second dielectric layer and above the bottom of the first etch stop layer, and wherein the first bonding pad extends through the second dielectric layer.In some embodiments, the device further includes: a second etch stop layer extending vertically between the first etch stop layer and the top electrode; and a third dielectric layer extending laterally between the first etch stop layer and the top electrode, and laterally between the first etch stop layer and the second etch stop layer. In some embodiments, the device further includes: a third bonding pad above the trench capacitor, laterally spaced from the first bonding pad, and extending through the first bonding dielectric layer; and a fourth bonding pad above and bonded to the third bonding pad, laterally spaced from the second bonding pad, and extending through the second bonding dielectric layer, wherein the third bonding pad extends from the fourth bonding pad to the bottom electrode.

[0116] In other embodiments, this disclosure relates to a method of forming an integrated chip. The method includes forming a first transistor along a first semiconductor substrate. Forming a first dielectric structure on the first semiconductor substrate. Forming a first conductive interconnect and a second conductive interconnect in the first dielectric structure. Forming a trench capacitor on the first conductive interconnect. The trench capacitor includes a bottom electrode, a top electrode, and an insulating layer between the bottom electrode and the top electrode. Forming a first bonding contact on the second conductive interconnect and laterally spaced from the trench capacitor. Forming a first bonding pad on the top electrode of the trench capacitor. Forming a second bonding pad on top of the first bonding contact and laterally spaced from the first bonding pad. Arranging a chip on the first semiconductor substrate. The chip includes a second transistor along the second semiconductor substrate, a second dielectric structure under the second semiconductor substrate, a third conductive interconnect and a fourth conductive interconnect in the second dielectric structure, a third bonding pad under the third conductive interconnect, and a fourth bonding pad under the fourth conductive interconnect and laterally spaced from the third bonding pad. The third bonding pad is bonded to the first bonding pad. The fourth bonding pad is bonded to the second bonding pad.

[0117] In some embodiments, the method further includes: forming a first bonding dielectric layer over the trench capacitor, wherein a first bonding pad extends through the first bonding dielectric layer, and a second bonding pad extends through the first bonding dielectric layer, and wherein the chip includes a second bonding dielectric layer extending between the third bonding pad and the fourth bonding pad; and bonding the second bonding dielectric layer to the first bonding dielectric layer. In some embodiments, forming the first bonding pad on the top electrode of the trench capacitor includes etching the first bonding dielectric layer to expose the upper surface of the top electrode and depositing metal directly on the upper surface of the top electrode.

[0118] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of this disclosure.

Claims

1. An integrated chip, characterized in that, include: The first chip includes a first semiconductor substrate, a first transistor along the first semiconductor substrate, a first conductive interconnect above the first transistor, and a first bonding pad above the first conductive interconnect. as well as A second chip is bonded to the first chip. The second chip includes a second semiconductor substrate, a second transistor along the second semiconductor substrate, a second conductive interconnect below the second transistor, and a second bonding pad below the second conductive interconnect, wherein the second bonding pad is bonded to the first bonding pad. The first chip also includes a trench capacitor above the first conductive interconnect and below the first bonding pad, the trench capacitor including a bottom electrode, a top electrode and an insulating layer between the bottom electrode and the top electrode, wherein the first bonding pad extends from the second bonding pad to the top electrode of the trench capacitor.

2. The integrated chip according to claim 1, characterized in that, The bottom electrode of the trench capacitor extends from the insulating layer to the first conductive interconnect.

3. The integrated chip according to claim 1, characterized in that, The first chip further includes a bonding contact spaced laterally from the trench capacitor, and a third bonding pad above the bonding contact and spaced laterally from the first bonding pad and the trench capacitor.

4. The integrated chip according to claim 1, characterized in that, The second chip also includes a photodetector along the second semiconductor substrate.

5. The integrated chip according to claim 1, characterized in that, The first chip also includes a photodetector along the first semiconductor substrate.

6. An integrated chip, characterized in that, include: A first metal interconnect above a first semiconductor substrate; A first dielectric layer above the first metal interconnect; A trench capacitor extending through and above the first dielectric layer, the trench capacitor including a bottom electrode above the first metal interconnect, a top electrode above the bottom electrode, and an insulating layer between the top electrode and the bottom electrode; A first etch stop layer above the trench capacitor; A first bonding dielectric layer above the first etch stop layer; A first bonding pad above the trench capacitor and extending through the first bonding dielectric layer and the first etch stop layer; A second bonding dielectric layer above and bonded to the first bonding dielectric layer; A second bonding pad above the first bonding pad, the second bonding pad extending through the second bonding dielectric layer; as well as The second semiconductor substrate above the second bonding pad The upper surface of the first bonding pad is bonded to the lower surface of the second bonding pad, and the lower surface of the first bonding pad is located on the top electrode of the trench capacitor.

7. The integrated chip according to claim 6, characterized in that, Also includes: A second metal interconnect laterally spaced from the first metal interconnect; A bonding contact that is above the second metal interconnect, laterally spaced from the trench capacitor, and extends through the first dielectric layer; A third bonding pad is located above the bonding contact, laterally spaced from the first bonding pad, and extending through the first bonding dielectric layer; as well as A fourth bonding pad is located above and bonded to the third bonding pad, laterally spaced from the second bonding pad, and extending through the second bonding dielectric layer.

8. The integrated chip according to claim 6, characterized in that, The first dielectric layer contains a first dielectric, the first etch stop layer contains a second dielectric that is different from the first dielectric, the first bonding dielectric layer contains a third dielectric that is different from the first dielectric and the second dielectric, and the second bonding dielectric layer contains a fourth dielectric that is different from the first dielectric and the second dielectric.

9. The integrated chip according to claim 6, characterized in that, The first etch stop layer extends along the top surface of the top electrode, and wherein the first bonding pad extends through the first etch stop layer to the top surface of the top electrode.

10. The integrated chip according to claim 6, characterized in that, Also includes: A second dielectric layer between the first dielectric layer and the first bonding dielectric layer and between the first etch stop layer and the first bonding dielectric layer, wherein the trench capacitor extends above the bottom of the second dielectric layer, and wherein the first bonding pad extends through the second dielectric layer. as well as A second etch stop layer is provided between the first dielectric layer and the second dielectric layer, wherein the trench capacitor extends through the second etch stop layer and extends above the second etch stop layer.

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