Semiconductor structure and semiconductor devices

Abstract

This disclosure provides a semiconductor structure and a semiconductor device. The semiconductor structure includes: a substrate having a first surface and a second surface disposed opposite to each other; a plurality of transistor structures arranged in an array on the first surface of the substrate; the transistor structures include: a gate structure and source / drain structures located on opposite sides of the gate structure in a first direction; wherein an isolation layer is provided between adjacent source / drain structures in a second direction; at least a portion of the surface of the source / drain structures is covered with a metal silicide layer; the first direction and the second direction intersect and are both parallel to the first surface; a conductive structure located within the isolation structure between adjacent source / drain structures in the second direction for achieving gate cut-off, and penetrating the substrate and exposed on the second surface of the substrate; a contact structure covering at least a portion of the surface of the metal silicide layer; at least a portion of the contact structure is located between the metal silicide and the conductive structure, and is electrically connected to the conductive structure and the source / drain structures.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and semiconductor device. Background Technology

[0002] In traditional semiconductor device fabrication processes, power supply networks are typically arranged on the front side of the chip to provide power. However, arranging the power supply network on the front side of the wafer occupies a significant amount of space, making it difficult to further reduce the overall size of the semiconductor device.

[0003] To optimize the layout of circuit layers and improve overall chip performance, the concept of Backside Power Delivery Network (BSPDN) was proposed. In BPDN, transistors are connected to the power supply network on the back of the chip via power vias, effectively reducing the area of ​​logic cells in semiconductor devices. However, with the continuous development of semiconductor technology, increasingly higher requirements are being placed on BPDN technology to further improve the performance of semiconductor devices. Utility Model Content

[0004] In view of the above, this disclosure provides a semiconductor structure and a semiconductor device.

[0005] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0006] On one hand, embodiments of this disclosure provide a semiconductor structure, the semiconductor structure comprising:

[0007] A substrate having a first surface and a second surface disposed opposite to each other;

[0008] Multiple transistor structures are arrayed on a first surface of the substrate; each transistor structure includes a gate structure and source / drain structures located on opposite sides of the gate structure in a first direction; wherein an isolation layer is provided between adjacent source / drain structures in a second direction; at least a portion of the surface of each source / drain structure is covered with a metal silicide layer; the first direction and the second direction intersect and are both parallel to the first surface.

[0009] A conductive structure is located within an isolation structure between adjacent source / drain structures in the second direction for achieving gate cutoff, and extends through the substrate and is exposed on the second surface of the substrate;

[0010] A contact structure covering at least a portion of the surface of the metal silicide layer; at least a portion of the contact structure is located between the metal silicide layer and the conductive structure, and is electrically connected to the conductive structure and the source / drain structure.

[0011] In some embodiments, the contact structure at least fills the space between the source / drain structure and the conductive structure, and contacts the first surface of the substrate.

[0012] In some embodiments, the semiconductor structure further includes:

[0013] A dielectric layer fills a portion of the space between the source / drain structure and the conductive structure, and contacts the first surface of the substrate;

[0014] The contact structure covers the dielectric layer and at least fills the remaining space between the source / drain structure and the conductive structure.

[0015] In some embodiments, the contact structure also covers at least a portion of the top surface of the conductive structure away from the substrate.

[0016] In some embodiments, the junction of the sidewall of the contact structure and the conductive structure is located on the top surface of the conductive structure, or the sidewall of the contact structure and the sidewall of the conductive structure on the side away from the source / drain structure are aligned on the plane containing the first direction and the third direction; wherein, the third direction is a direction perpendicular to the first plane.

[0017] In some embodiments, the metal silicide layer covers at least a portion of the top surface of the source / drain structure and at least a portion of the side of the source / drain structure near the conductive structure in the second direction.

[0018] In some embodiments, the metal silicide layer covers a portion of the top surface of the source / drain structure near the conductive structure in the second direction, and covers at least a portion of the side surface of the source / drain structure near the conductive structure in the second direction.

[0019] In some embodiments, the isolation layer includes:

[0020] A first isolation sublayer is in contact with a first surface of the substrate;

[0021] A second isolation sublayer is located on the surface of the first isolation sublayer; the contact structure extends from the surface of the second isolation sublayer to the surface of the source / drain structure, and the contact structure extends from the surface of the second isolation sublayer to the top surface of the conductive structure away from the substrate.

[0022] In some embodiments, the conductive structure includes:

[0023] A conductive pillar extending through the substrate in a direction perpendicular to the first surface; a portion of the side surface of the conductive pillar contacts the contact structure; the conductive pillar comprises: a metal pillar, and an adhesive layer covering at least a portion of the surface of the metal pillar;

[0024] A barrier layer covers the remaining side of the conductive post that is not in contact with the contact structure.

[0025] On the other hand, embodiments of this disclosure also provide a semiconductor device, the semiconductor device comprising:

[0026] One or more semiconductor structures as described in the above embodiments;

[0027] The circuit structure is connected to the conductive structure exposed on the second surface of the substrate in the semiconductor structure.

[0028] In this embodiment, a metal silicide layer is located between the source / drain structure and the contact structure to reduce the parasitic resistance of the source / drain structure. Furthermore, at least a portion of the contact structure is located between the source / drain structure and the conductive structure, allowing the conductive structure and the contact structure to be electrically connected in a second direction. This increases the contact area between the conductive structure and the contact structure, thereby significantly reducing the resistance and improving the electrical performance of the device. Attached Figure Description

[0029] Figure 1 A cross-sectional view of a first semiconductor structure provided in an embodiment of this disclosure;

[0030] Figure 2 A cross-sectional view of a second semiconductor structure provided in an embodiment of this disclosure;

[0031] Figure 3 A cross-sectional view of a third semiconductor structure provided in an embodiment of this disclosure;

[0032] Figure 4 A cross-sectional view of a semiconductor device provided in an embodiment of this disclosure in the YZ plane;

[0033] Figure 5 A cross-sectional view of a semiconductor device provided in an embodiment of this disclosure in the XZ plane;

[0034] Figures 6 to 34 This is a structural diagram of the manufacturing process of a semiconductor device in an example. Detailed Implementation

[0035] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0037] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0041] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0042] As transistor sizes continue to shrink, front-side power supply architectures can no longer reduce cell height. Back-side power supply architectures, on the other hand, can move power lines to the back of the wafer, thus maintaining the trend of cell height reduction, improving power efficiency, and freeing up front-side wiring resources.

[0043] In back-side routing solutions, power vias can be formed during the contact (CT) formation process. Specifically, during contact formation, trenches with a high aspect ratio are etched through contact holes to serve as power vias, and then conductive material is simultaneously filled into the contact holes and trenches to form the contact structure and power vias. However, this solution has high process complexity, produces excessively large aspect ratio vias, and lacks compatibility and integration with existing processes.

[0044] In view of this, embodiments of the present disclosure provide a semiconductor structure, such as... Figure 1As shown, the semiconductor structure includes:

[0045] Substrate 101, substrate 101 has a first surface 101a and a second surface 101b disposed opposite to each other;

[0046] Multiple transistor structures are arrayed on the first surface 101a of the substrate 101; the transistor structures include: gate structures ( Figure 1 (not shown) and source / drain structures 103 located on opposite sides of the gate structure in the first direction (X direction); wherein an isolation layer 104 is provided between adjacent source / drain structures 103 in the second direction (Y direction); at least a portion of the surface of the source / drain structures 103 is covered with a metal silicide layer 105; the first direction and the second direction intersect and are both parallel to the first surface 101a.

[0047] The conductive structure 106 is located within the isolation structure between adjacent source / drain structures 103 in the second direction for achieving gate cut-off, and penetrates the substrate 101 and is exposed on the second surface 101b of the substrate 101.

[0048] Contact structure 107 covers at least a portion of the surface of metal silicide layer 105; at least a portion of contact structure 107 is located between metal silicide layer 105 and conductive structure 106, and is electrically connected to conductive structure 106 and source / drain structure 103.

[0049] In this embodiment, the metal silicide layer 105 is located between the source / drain structure 103 and the contact structure 107 to reduce the parasitic resistance of the source / drain structure 103. Furthermore, at least a portion of the contact structure 107 is located between the source / drain structure 103 and the conductive structure 106, allowing the conductive structure 106 and the contact structure 107 to be electrically connected in a second direction. This increases the contact area between the conductive structure 106 and the contact structure 107, thereby significantly reducing resistance and improving the electrical performance of the device.

[0050] The material of the substrate 101 is not specifically limited in this embodiment. As an example, the substrate 101 may be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 101 may be a single-layer structure or a multi-layer structure. For example, the substrate 101 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate 101 may be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0051] The transistor structure disclosed herein refers to a device comprising at least three terminals: a gate, a source, and a drain. The gate structure forms the gate of the transistor structure, and the source and drain structures 103 located on opposite sides of the gate structure in a first direction respectively form the source and drain of the transistor structure. The transistor structure has a channel region between the drain and the source, and the gate can control the conductivity of the channel region, thereby enabling current to flow between the source, the channel region, and the drain based on gate control.

[0052] Here, transistor structures include, but are not limited to, multi-channel transistors, 3D transistors, stacked transistors, flip-chip stacked transistors (FlipFETs), or other types of transistors.

[0053] A metal silicide layer 105 covers at least a portion of the surface of the source / drain structure 103.

[0054] In some embodiments, the metal silicide layer 105 covers at least a portion of the top surface of the source / drain structure 103 and at least a portion of the side of the source / drain structure 103 near the conductive structure 106 in the second direction (Y direction).

[0055] like Figure 1 As shown, Figure 1 The diagram shows two source / drain structures 103 arranged sequentially in the Y direction. A metal silicide layer 105 covers at least a portion of the top surface of the source / drain structure 103 on the left side and the side of the source / drain structure 103 near the conductive structure 106 in the second direction (Y direction). The metal silicide layer 105 also covers at least a portion of the top surface of the source / drain structure 103 on the right side.

[0056] In other embodiments, the metal silicide layer 105 covers a portion of the top surface of the source / drain structure 103 near the conductive structure 106 in the second direction (Y direction), and covers at least a portion of the side surface of the source / drain structure 103 near the conductive structure 106 in the second direction.

[0057] like Figure 2 As shown, Figure 2 The diagram shows two source / drain structures 103 arranged sequentially in the Y direction. A metal silicide layer 105 covers at least a portion of the top surface of the source / drain structure 103 located on the left side, near the conductive structure 106 in the second direction, as well as the side surface of the source / drain structure 103 near the conductive structure 106 in the second direction (Y direction). Furthermore, the metal silicide layer 105 covers at least a portion of the top surface of the source / drain structure 103 located on the right side.

[0058] Here, the metal silicide layer 105 is used to form a good ohmic contact between the source / drain structure 103 and the contact structure 107, thereby reducing the parasitic resistance of the source / drain structure 103. The materials of the metal silicide layer 105 include titanium silicide (TiSi2), cobalt silicide (CoSi2), nickel silicide (NiSi), and nickel-platinum silicide (NiPtSi).

[0059] In this embodiment of the disclosure, the conductive structure 106 includes a power via, through which the source-drain structure 103 in the transistor structure can be connected to the power supply network located on the second surface 101b of the substrate 101 via the conductive structure 106.

[0060] In some embodiments, the conductive structure 106 includes: a conductive pillar 108 extending through the substrate 101 in a direction perpendicular to the first surface 101a; a portion of the side surface of the conductive pillar 108 contacting the contact structure 107; the conductive pillar 108 includes: a metal pillar 109, and an adhesion layer 110 covering at least a portion of the surface of the metal pillar 109; a barrier layer 111 covering the remaining side surface of the conductive pillar 108 not in contact with the contact structure, such as... Figure 1 As shown.

[0061] Here, the barrier layer can be a portion of the isolation material in the isolation structure used to achieve the gate cut-off function, and the conductive structure can be entirely located within the isolation structure. Furthermore, the conductive structure 106 can be formed during the gate cut process to form the isolation structure. In this embodiment, the conductive structure 106 is placed within the space of the isolation structure, avoiding the high aspect ratio problem caused by fabricating the conductive structure 106 through CT holes, thereby reducing the process difficulty and exhibiting strong compatibility with current semiconductor processes.

[0062] The materials of the metal pillar 109 include ruthenium (Ru), tungsten (W), molybdenum (Mo), etc. The materials of the adhesive layer 110 include titanium (Ti), titanium nitride (TiN), etc. The adhesive layer 110 is used to enhance the adhesion between the metal pillar 109 and the barrier layer 111 and prevent the metal pillar 109 from peeling off from the barrier layer 111.

[0063] The barrier layer 111 effectively prevents metal atoms in the metal pillar 109 from diffusing into the surrounding silicon (Si) or dielectric material (e.g., SiO2), thereby preventing device contamination. The materials of the barrier layer 111 include tantalum (Ta) / tantalum nitride (TaN), titanium (Ti) / titanium nitride (TiN), ruthenium (Ru), etc.

[0064] In some embodiments, the conductive structure 106 does not include a barrier layer. In this case, the portion of the adhesive layer 110 that is not in contact with the contact structure 107 is in direct contact with other dielectric layers (e.g., the first isolation sublayer 113).

[0065] In this embodiment of the disclosure, the conductive structure 106 and the source / drain structure 103 are electrically connected to each other through a contact structure 107. The material of the contact structure 107 includes, but is not limited to, tungsten (W) and titanium nitride (TiN).

[0066] In some embodiments, the contact structure 107 at least fills the space between the source / drain structure 103 and the conductive structure 106, and contacts the first surface 101a of the substrate 101, such as... Figure 1 As shown.

[0067] Specifically, Figure 1 The contact structure 107 is filled between the source / drain structure 103 and the conductive structure 106 located on the left side, and the contact structure 107 covers the surface of the metal silicide layer 105 located on the surface of the source / drain structure 103.

[0068] In other embodiments, the semiconductor structure further includes: a dielectric layer 112 filling a portion of the space between the source / drain structure 103 and the conductive structure 106, and contacting a first surface 101a of the substrate 101; and a contact structure 107 covering the dielectric layer 112 and at least filling the remaining space between the source / drain structure 103 and the conductive structure 106, such as... Figure 3 As shown.

[0069] Specifically, Figure 3 The dielectric layer 112 fills part of the space between the source / drain structure 103 and the conductive structure 106 on the left side, and the contact structure 107 fills the remaining space between the source / drain structure 103 and the conductive structure 106 on the left side.

[0070] Here, the material of dielectric layer 112 includes silicon dioxide (SiO2). The material of dielectric layer 112 can be the same as that of isolation layer 104, and dielectric layer 112 and isolation layer 104 can be formed simultaneously during the manufacturing process of semiconductor structure.

[0071] In this embodiment of the present disclosure, at least a portion of the contact structure 107 is located between the metal silicide layer 105 and the conductive structure 106. The source / drain structure 103 and the conductive structure 106 are electrically connected in the second direction through the contact structure 107 and the metal silicide layer 105, thereby increasing the contact area between the conductive structure 106 and the contact structure 107 and thus reducing the resistance.

[0072] In some embodiments, the contact structure 107 also covers at least a portion of the top surface of the conductive structure 106 away from the substrate 101, such as... Figure 1 As shown.

[0073] Figure 1In this configuration, the contact structure 107 fills the space between the source / drain structure 103 and the conductive structure 106 located on the left side, and also covers the surface of the conductive structure 106. Thus, the source / drain structure 103 and the conductive structure 106 located on the left side can be electrically connected via the contact structure 107 in the second direction (Y direction) and the third direction perpendicular to the first surface 101a (Z direction), respectively, thereby further increasing the contact area between the conductive structure 106 and the contact structure 107 located on the left side.

[0074] In some embodiments, the junction between the sidewall of the contact structure 107 and the conductive structure 106 is located on the top surface of the conductive structure 106, such as... Figure 1 As shown.

[0075] In other embodiments, the sidewall of the contact structure 107 is aligned with the sidewall of the conductive structure 106 on the side away from the source / drain structure 103 in the plane containing the first direction (X direction) and the third direction (Z direction), such as... Figure 2 As shown. The third direction is the direction perpendicular to the first surface 101a.

[0076] In some embodiments, the isolation layer 104 includes: a first isolation sublayer 113, which contacts a first surface 101a of the substrate 101; a second isolation sublayer 114 located on the surface of the first isolation sublayer 113; and a contact structure 107 extending from the surface of the second isolation sublayer 114 to the surface of the source / drain structure 103, and the contact structure 107 extending from the surface of the second isolation sublayer 114 to the top surface of the conductive structure 106 away from the substrate 101, such as... Figures 1 to 3 As shown.

[0077] Here, both the first isolation sublayer 113 and the second isolation sublayer 114 are made of insulating materials, such as silicon dioxide. Furthermore, the material of the first isolation sublayer 113 can be the same as the material of the dielectric layer 112.

[0078] In some embodiments, different source / drain structures 103 can be connected to the same or different conductive structures 106 via contact structures 107.

[0079] This disclosure also provides a semiconductor device comprising: one or more semiconductor structures as described in the above embodiments; and a circuit structure 401 connected to a conductive structure 106 exposed on the second surface 101b of the substrate 101 in the semiconductor structure.

[0080] In one example, Figure 4 and Figure 5 The semiconductor devices in the process can be manufactured through the following process steps, such as Figures 6 to 34 As shown.

[0081] Specifically, step S1: epitaxially growing a superlattice structure 601 on a first surface 101a of a substrate 101, the superlattice structure 601 comprising first sacrificial layers 602 and semiconductor layers 603 that are alternately stacked in a direction perpendicular to the first surface 101a, as Figure 6 is shown. Wherein, the material of the semiconductor layer 603 comprises Si 1-y Ge y , and the material of the first sacrificial layer 602 comprises Si 1-x Ge x . In some embodiments, y<x. In other embodiments, 0≤x≤1, 0≤y≤0.6.

[0082] Step S2: patterning the superlattice structure 601 to form fin structures 604 extending in a first direction (X direction) and spaced apart in a second direction (Y direction), as Figure 6 is shown.

[0083] Step S3: forming a shallow trench isolation (Shallow Trench Isolation, STI) structure 115 between adjacent fin structures 604 in the second direction. In this way, the shallow trench isolation structure 115 can realize isolation between adjacent transistors in the second direction.

[0084] Step S4: forming a plurality of dummy gate structures 605 spaced apart along the first direction and sidewall spacer structures 606 located on sidewalls of the dummy gate structures 605 on the surface of the superlattice structure. Each of the dummy gate structures 605 extends along the second direction, so that the plurality of fin structures 604 spaced apart in the second direction are connected to each other through the dummy gate structures 605.

[0085] Step S5: using the dummy gate structures 605 and the sidewall spacer structures 606 as a mask, patterning the superlattice structure 601 to form a plurality of initial stacked structures 607 spaced apart along the first direction. At this time, the semiconductor layers 603 located in the initial stacked structures 607 are used to form channels of transistor structures, as Figure 7 is shown.

[0086] Step S6: laterally etching the initial stacked structures 607 along the first direction to remove part of the first sacrificial layers 602. In this way, isolation trenches 608 are formed between adjacent semiconductor layers 603 in a direction perpendicular to the first surface 101a (Z direction), and between the semiconductor layers 603 and the substrate 101. An isolation material is filled in the isolation trenches 608 to form a stacked structure 609, as Figure 8 is shown.

[0087] Here, the isolation material filling the isolation trench 608 can form an interlayer isolation structure 610 within the isolation trench 608. The interlayer isolation structure 610 is used to achieve isolation between the gate structure and the source / drain structure. The interlayer isolation structure 610 can be a single-layer structure. Alternatively, the interlayer isolation structure 610 can include multiple layers of isolation material stacked in the first direction. That is, the interlayer isolation structure 610 can be a multilayer structure.

[0088] Step S7: Form source / drain structures 103 on the exposed substrate 101 surface, such as... Figure 9 As shown.

[0089] Step S8: Form an inter-layer dielectric (ILD) on the surface of the source / drain structure 103, such as... Figure 10 As shown. Here, the interlayer dielectric can also be understood as the first isolation sublayer 113 and the dielectric layer 112 mentioned above. The first isolation sublayer 113 and the dielectric layer 112 can be formed simultaneously in a one-step process.

[0090] Step S9: Remove the first sacrificial layer to form a gap 611 located between the semiconductor layers, such as Figure 11 As shown.

[0091] Step S10: Form a gate structure 403 within the gap 611, such as Figure 12 and Figure 13 As shown. Here, the gate structure 403 includes a high-k gate dielectric layer, a work function layer, and a gate electrode layer stacked sequentially.

[0092] Step S11: Perform a gate cut isolation method to form a corresponding isolation structure 612. Specifically, form a gate cut groove 613 extending along the first direction to cut the gate, such as... Figure 14 As shown.

[0093] Step S12: Fill the gate cut-off groove 613 with isolation material to form an isolation structure 612, such as... Figure 15 As shown. Here, while forming the isolation structure 612 in the gate cut-off groove 613, part of the isolation material also covers the surface of the first isolation sublayer 113.

[0094] Here, the materials of the isolation structure 612 include silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon nitride (SiN), silicon carbonitride oxynitride (SiOCN), silicon carbonitride (SiOC), etc. In some examples, the source / drain structure 103 is not touched during gate dicing, thereby reducing device performance degradation caused by damage to the source / drain structure 103.

[0095] Step S13: Form a conductive trench 614 within the isolation structure 612 of the region in the semiconductor structure that needs to be connected to the back power supply, such as... Figure 16 As shown. At this time, the insulating material that was not removed in the Y direction of the conductive groove forms a barrier layer 111.

[0096] Step S14: Fill the conductive trench 614 with conductive material 615, such as... Figure 17 As shown. Here, while the conductive trench 614 is filled with conductive material 615, part of the conductive material 615 also covers the surface of the first isolation sublayer 113.

[0097] Step S15: Perform a chemical-mechanical polishing (CMP) process to remove the insulating and conductive materials located on the surface of the first insulating sublayer 113 to form a conductive structure 106, such as... Figure 18 and Figure 19 As shown.

[0098] Here, for areas in the semiconductor structure that do not require connection to the back power supply, the material in the isolation structure 612 can still be the aforementioned isolation material, thereby improving insulation. In some examples, during the gate dicing process, the conductive structure 106 can be formed directly within the gate dicing groove 613 after the gate dicing groove 613 is formed, but the insulation of this approach is slightly inferior.

[0099] Figures 14 to 19 In this scheme, the fabrication process of the conductive structure 106 used to realize the back power supply function is integrated into the gate cutting process, and the conductive structure 106 is placed in the space of the isolation structure 612. This avoids the problem of high depth-to-width ratio caused by fabricating the conductive structure 106 through CT holes, thereby reducing the process difficulty and having strong inheritability with current semiconductor processes.

[0100] Step S16: Subsequently, a middle end of line (MEOL) process is performed on the surface of the semiconductor structure to form the second isolation sublayer 114, such as... Figure 20 and Figure 21 As shown.

[0101] Step S17: Etch the first isolation sublayer 113 and the second isolation sublayer 114 to expose at least a portion of the surface of the source / drain structure 103, such as... Figures 22 to 24 As shown, where Figure 23 and Figure 24 They are respectively Figure 22 The cross section at the tangents AA and BB.

[0102] Step S18: Form photoresist (or SOC, BARC, or other materials) 616 on the exposed surface of the source / drain structure 103, and etch the first isolation sublayer 113 and the second isolation sublayer 114 again, so that at least a portion of the side surfaces of the source / drain structure 103 are exposed, such as... Figures 25 to 26 As shown.

[0103] It should be noted that during the etching process in step S18, while removing the first isolation sublayer 113, a portion of the barrier layer 111 is also exposed. Subsequently, this exposed portion of the barrier layer 111 can be removed in the second etching process, thereby exposing a portion of the adhesion layer 110. In some examples, the second etching process can also remove a portion of the metal pillar 109 or the adhesion layer 110.

[0104] Here, in order to ensure the electrical connection between the source / drain structure 103 and the conductive structure 106, the etched areas in the etching processes of steps S17 and S18 partially overlap, making the etching process compatible with modern semiconductor processes.

[0105] Step S19: Remove the photoresist (or SOC, BARC, etc.) introduced in step S18, such as... Figure 27 As shown.

[0106] Step S20: Form a metal silicide layer 105 on at least a portion of the surface of the source / drain structure 103, for example, forming a metal silicide layer 105 on a portion of the top surface and a portion of the side surface of the source / drain structure 103, such as... Figure 28 As shown. Understandably, during this process, the top and sidewalls of the conductive structure 106 may also have metal corresponding to the metal silicide layer attached, which can be removed in a subsequent process.

[0107] Step S21: Form a contact structure 107 on a portion of the surface of the metal silicide layer 105, such as... Figure 29 and Figure 30 As shown. Since the conductive structure 106 and the contact structure 107 are electrically connected in both the second direction and the direction perpendicular to the first surface, the contact area between the conductive structure 106 and the contact structure 107 is increased, thereby greatly reducing the resistance and improving the electrical performance of the device.

[0108] Step S22: Continue the back-end of line (BEOL) process on the front side of the semiconductor structure to form a multilayer interconnect structure 617, such as... Figure 31 As shown. Furthermore, a carrier wafer 618 is bonded to the surface of the multilayer interconnect structure 617, as... Figure 32 As shown.

[0109] Step S23: Flip the entire semiconductor structure and thin the second surface 101b of the substrate 101 until the conductive structure 106 is exposed, as shown below. Figure 33 As shown.

[0110] Step S24: A circuit structure 401 is formed on the second surface 101b of the substrate 101. The circuit structure 401 is connected to the conductive structure 106 exposed on the second surface 101b of the substrate 101 in the semiconductor structure, such as... Figure 34 As shown.

[0111] It should be noted that the specific structures of the semiconductor structures and semiconductor devices involved in the embodiments of this disclosure can also be based on the above steps S1 to S24, and Figures 6 to 34 The descriptions in the text are for reference only, and will not be elaborated upon here.

[0112] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0113] The above description is only a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. All equivalent structural transformations made under the concept of this disclosure using the contents of this specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a first surface and a second surface disposed opposite to each other; Multiple transistor structures are arrayed on the first surface of the substrate; The transistor structure includes: a gate structure and source / drain structures located on opposite sides of the gate structure in a first direction; wherein an isolation layer is provided between adjacent source / drain structures in a second direction; at least a portion of the surface of the source / drain structures is covered with a metal silicide layer; the first direction and the second direction intersect and are both parallel to the first surface; A conductive structure is located within an isolation structure between adjacent source / drain structures in the second direction for achieving gate cutoff, and extends through the substrate and is exposed on the second surface of the substrate; A contact structure covering at least a portion of the surface of the metal silicide layer; at least a portion of the contact structure is located between the metal silicide layer and the conductive structure, and is electrically connected to the conductive structure and the source / drain structure.

2. The semiconductor structure according to claim 1, characterized in that, The contact structure fills at least between the source / drain structure and the conductive structure, and contacts the first surface of the substrate.

3. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A dielectric layer fills a portion of the space between the source / drain structure and the conductive structure, and contacts the first surface of the substrate; The contact structure covers the dielectric layer and at least fills the remaining space between the source / drain structure and the conductive structure.

4. The semiconductor structure according to claim 1, characterized in that, The contact structure also covers at least a portion of the top surface of the conductive structure away from the substrate.

5. The semiconductor structure according to claim 4, characterized in that, The junction between the sidewall of the contact structure and the conductive structure is located on the top surface of the conductive structure, or the sidewall of the contact structure and the sidewall of the conductive structure on the side away from the source / drain structure are aligned on the plane containing the first direction and the third direction; wherein, the third direction is a direction perpendicular to the first plane.

6. The semiconductor structure according to claim 1, characterized in that, The metal silicide layer covers at least a portion of the top surface of the source / drain structure and at least a portion of the side of the source / drain structure near the conductive structure in the second direction.

7. The semiconductor structure according to claim 6, characterized in that, The metal silicide layer covers a portion of the top surface of the source / drain structure near the conductive structure in the second direction, and covers at least a portion of the side surface of the source / drain structure near the conductive structure in the second direction.

8. The semiconductor structure according to claim 1, characterized in that, The isolation layer includes: A first isolation sublayer is in contact with a first surface of the substrate; A second isolation sublayer is located on the surface of the first isolation sublayer; the contact structure extends from the surface of the second isolation sublayer to the surface of the source / drain structure, and the contact structure extends from the surface of the second isolation sublayer to the top surface of the conductive structure away from the substrate.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The conductive structure includes: A conductive pillar extending through the substrate in a direction perpendicular to the first surface; a portion of the side surface of the conductive pillar contacts the contact structure; the conductive pillar comprises: a metal pillar, and an adhesive layer covering at least a portion of the surface of the metal pillar; A barrier layer covers the remaining side of the conductive post that is not in contact with the contact structure.

10. A semiconductor device, characterized in that, include: One or more semiconductor structures as described in any one of claims 1 to 9; The circuit structure is connected to the conductive structure exposed on the second surface of the substrate in the semiconductor structure.

Images