A low-cost semiconductor packaging structure

Abstract

This utility model discloses a low-cost semiconductor packaging structure, relating to the field of semiconductor packaging structures. It includes a packaging substrate, on the upper surface of which a bottom-layer chip is soldered. A multifunctional interposer heat insulation layer is soldered to the upper surface of the bottom-layer chip, and a first copper pillar is soldered to the lower surface of the multifunctional interposer heat insulation layer. The multifunctional interposer heat insulation layer, made of heat-insulating material, can block heat transfer between the bottom-layer chip and the top-layer chip, solving the problem of localized overheating. The first copper pillar, connecting copper sheet, and second copper pillar form a stable interconnect channel, adapting to the pin spacing and signal requirements of chips with different processes, avoiding signal interference caused by direct chip contact or thin adhesive layer separation. An L-shaped heat sink can quickly absorb the heat generated by the top-layer chip, and thermally conductive copper wires conduct heat from the L-shaped heat sink to the heat dissipation pads, achieving efficient heat dissipation and preventing localized overheating from affecting chip performance.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging structures, and in particular to a semiconductor packaging structure with low packaging cost. Background Technology

[0002] With advancements in chip manufacturing processes, traditional monolithic integration methods have encountered technological bottlenecks, such as Moore's Law approaching physical limits and manufacturing costs increasing exponentially. Chiplet technology breaks down a single chip into multiple functional modules and integrates them together using advanced packaging technology. Different functional modules can be manufactured using the most suitable process according to actual needs, avoiding process conflicts, reducing costs, and improving performance and energy efficiency.

[0003] In existing technologies, when reducing the cost and efficiency of semiconductor packaging, dual-chip stacking (such as back-to-back stacking or face-to-face stacking) is usually adopted, thereby reducing the package size and simplifying system-level interconnection. However, in actual use, existing dual-chip stacking relies on direct contact between chips or is separated only by a thin adhesive layer, and is prone to problems such as signal interference and local overheating during subsequent use.

[0004] Therefore, it is necessary to propose a semiconductor packaging structure with low packaging cost to solve the above problems. Utility Model Content

[0005] The purpose of this invention is to provide a semiconductor packaging structure with low packaging cost to solve the problems of signal interference and local overheating in existing dual-chip stacked packaging.

[0006] To achieve the above objectives, this utility model provides the following technical solution: a low-cost semiconductor packaging structure, comprising a packaging substrate, a bottom chip welded to the upper surface of the packaging substrate, a multifunctional intermediate heat insulation layer welded to the upper surface of the bottom chip, a first copper pillar welded to the lower surface of the multifunctional intermediate heat insulation layer, a connecting copper sheet welded inside the multifunctional intermediate heat insulation layer, a second copper pillar welded to the upper surface of the multifunctional intermediate heat insulation layer, the first copper pillar being welded to the connecting copper sheet, the first copper pillar being welded to the upper surface of the bottom chip, the upper surface of the bottom chip being an active surface, the connecting copper sheet being welded to the second copper pillar, a top chip welded to the upper surface of the multifunctional intermediate heat insulation layer, the second copper pillar being welded to the lower surface of the top chip, the lower surface of the top chip being an active surface; An L-shaped heat sink is welded to the upper surface of the multifunctional intermediate heat insulation layer, and a heat insulation frame is welded to the lower surface of the L-shaped heat sink. The heat insulation frame is fitted onto the outside of the top layer chip. A thermally conductive copper wire is welded to the upper surface of the L-shaped heat sink, and a heat dissipation pad is welded inside the packaging substrate. The end of the thermally conductive copper wire away from the L-shaped heat sink is welded to the upper surface of the heat dissipation pad.

[0007] Preferably, the outer side of the encapsulation substrate has a first groove.

[0008] Preferably, the outer side of the multifunctional intermediate heat insulation layer is provided with a second groove.

[0009] Preferably, the outer surface of the underlying chip is welded with bonding leads.

[0010] Preferably, a bonding sheet is welded inside the packaging substrate, and the end of the bonding lead away from the underlying chip is welded to the upper surface of the bonding sheet.

[0011] Preferably, the lower surface of the bonding sheet is welded with solder balls.

[0012] Preferably, the upper surface of the encapsulation substrate is encapsulated with an epoxy molding compound, and the vertical height of the epoxy molding compound covers all components from the upper surface of the encapsulation substrate to the upper surface of the subsequent L-shaped heat sink.

[0013] The technical effects and advantages of this utility model are as follows: In this invention, a multifunctional intermediate heat insulation layer made of heat-insulating material is used to block heat transfer between the bottom chip and the top chip, thus solving the problem of local overheating. The first copper pillar, the connecting copper sheet, and the second copper pillar form a stable interconnect channel, which can adapt to the pin spacing and signal requirements of chips with different processes, avoiding signal interference caused by direct chip contact or thin adhesive layer separation. The L-shaped heat sink can quickly absorb the heat generated by the top chip, and the heat-conducting copper wire conducts the heat from the L-shaped heat sink to the heat dissipation pad, realizing efficient heat dissipation and avoiding local overheating from affecting chip performance. Furthermore, the second groove can increase the bonding force with the epoxy molding shell, further improving the molding connection effect. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the appearance structure of the semiconductor packaging structure with low packaging cost of this utility model.

[0015] Figure 2 This is a schematic diagram of the unpackaged semiconductor structure with low packaging cost according to this utility model.

[0016] Figure 3 This is a front cross-sectional view of the unpackaged semiconductor structure with low packaging cost according to this utility model.

[0017] Figure 4 This utility model Figure 2 A schematic diagram of the front cross-sectional structure of the central heat-conducting section.

[0018] In the diagram: 1. Packaging substrate; 2. Epoxy molding compound shell; 3. Bottom chip; 4. Bonding wire; 5. Bonding sheet; 6. Solder ball; 7. First copper pillar; 8. Multifunctional interlayer thermal insulation layer; 9. Connecting copper sheet; 10. Second copper pillar; 11. Top chip; 12. L-shaped heat sink; 13. First groove; 14. Second groove; 15. Thermal insulation frame; 16. Thermally conductive copper wire; 17. Thermal pad. Detailed Implementation

[0019] This utility model provides, for example Figures 1-4 The semiconductor packaging structure shown is designed to solve the problems of signal interference and local overheating in existing dual-chip stacked packaging. Through the structural design of multifunctional interlayer heat insulation layer, heat dissipation components and other components, the packaging cost is reduced while the performance is optimized.

[0020] The packaging substrate 1 serves as the basic carrier of the entire packaging structure. It has a pre-welded heat dissipation pad 17 inside and a first groove 13 on its outer side. After all internal components are assembled on the upper surface of the packaging substrate 1, an epoxy molding shell 2 is molded. The vertical height of the epoxy molding shell 2 covers all components from the upper surface of the packaging substrate 1 to the upper surface of the L-shaped heat sink 12. The heat dissipation pad 17 provides a heat dissipation endpoint for the thermally conductive copper wire 16, thus achieving heat dissipation. The first groove 13 can increase the contact area between the epoxy molding shell 2 and the packaging substrate 1, improving the molding connection effect. The epoxy molding shell 2 can isolate external dust and moisture, protect the internal chips and circuits, and ensure the long-term stability of the packaging structure.

[0021] The upper surface of the bottom chip 3 is the active surface, and its lower surface is soldered to the upper surface of the packaging substrate 1. Bonding leads 4 are soldered to the outer side. The end of the bonding lead 4 away from the bottom chip 3 is soldered to the upper surface of the bonding sheet 5 soldered inside the packaging substrate 1. Solder balls 6 are soldered to the lower surface of the bonding sheet 5. The active surface of the bottom chip 3 faces upward, which facilitates connection with the multifunctional intermediate heat insulation layer 8. The bonding lead 4 and the bonding sheet 5 work together to realize the signal and power transmission between the bottom chip 3 and the packaging substrate 1, avoiding signal loss from direct interconnection. The solder balls 6 can realize the quick docking of the entire package structure with the external circuit board, simplifying system-level interconnection.

[0022] The multifunctional intermediate heat insulation layer 8 is made of heat-insulating material, specifically aluminum nitride ceramic. A first copper pillar 7 is welded to its lower surface, and a connecting copper sheet 9 is welded inside. A second copper pillar 10 and an L-shaped heat sink 12 are welded to its upper surface. A second groove 14 is formed on its outer side. The end of the first copper pillar 7 furthest from the multifunctional intermediate heat insulation layer 8 is welded to the upper surface of the bottom chip 3, and the first copper pillar 7 is welded to the connecting copper sheet 9 for conductivity. The end of the second copper pillar 10 furthest from the multifunctional intermediate heat insulation layer 8 is welded to the lower surface of the top chip 11. The lower surface of the top chip 11 is the active surface, and the second copper pillar 10 is welded to the connecting copper sheet 9 for conductivity. The heat insulation properties of the multifunctional intermediate heat insulation layer 8 can block heat transfer between the bottom chip 3 and the top chip 11, solving the problem of localized overheating. The first copper pillar 7, the connecting copper sheet 9, and the second copper pillar 10 form a stable interconnect channel, adapting to the pin spacing and signal requirements of chips with different processes, avoiding signal interference caused by direct chip contact or thin adhesive layer separation. The second groove 14 increases the bonding force with the epoxy molding shell 2, further improving the molding connection effect.

[0023] A heat insulation frame 15 is welded to the lower surface of the L-shaped heat sink 12, and the heat insulation frame 15 is fitted on the outside of the top chip 11. A thermally conductive copper wire 16 is welded to the upper surface of the L-shaped heat sink 12. The end of the thermally conductive copper wire 16 away from the L-shaped heat sink 12 is welded to the upper surface of the heat dissipation pad 17 inside the packaging substrate 1. The L-shaped heat sink 12 can quickly absorb the heat generated by the top chip 11, and the heat insulation frame 15 can prevent the heat from spreading to the surrounding components. The thermally conductive copper wire 16 conducts the heat from the L-shaped heat sink 12 to the heat dissipation pad 17, realizing efficient heat dissipation and avoiding local overheating that could affect chip performance.

[0024] In use, the heat dissipation pad 17 is first soldered to a preset position inside the packaging substrate 1, then the bonding sheet 5 is fixed to the corresponding area inside the packaging substrate 1, and finally the solder ball 6 is soldered to the lower surface of the bonding sheet 5 to complete the basic assembly of the packaging substrate 1. The lower surface of the bottom chip 3 is soldered to the designated position on the upper surface of the packaging substrate 1. Then, one end of the bonding wire 4 is soldered to the pin on the outer side of the bottom chip 3 and the other end is soldered to the upper surface of the bonding sheet 5 to realize the signal and power connection between the bottom chip 3 and the packaging substrate 1. Before further assembly, the first copper pillar 7 is soldered to the lower surface of the multifunctional intermediate heat insulation layer 8, the connecting copper sheet 9 is soldered inside the multifunctional intermediate heat insulation layer 8, and the second copper pillar 10 is soldered to the upper surface of the multifunctional intermediate heat insulation layer 8 to ensure that the first copper pillar 7, the connecting copper sheet 9, and the second copper pillar 10 are soldered and connected in sequence. Then, the multifunctional intermediate heat insulation layer 8 is soldered to the upper surface of the bottom chip 3 through the first copper pillar 7, and finally the lower surface of the top chip 11 is soldered to the upper surface of the multifunctional intermediate heat insulation layer 8 through the second copper pillar 10.

[0025] Next, the heat insulation frame 15 is placed on the outside of the top chip 11, and then the lower surface of the L-shaped heat sink 12 is welded to the upper surface of the heat insulation frame 15, while ensuring that the lower surface of the L-shaped heat sink 12 is bonded to the upper surface of the multi-functional intermediate heat insulation layer 8; then, the upper surface of the L-shaped heat sink 12 is connected to the upper surface of the heat dissipation pad 17 inside the packaging substrate 1 using thermally conductive copper wire 16 to complete the heat dissipation path construction.

[0026] Furthermore, an epoxy molding shell 2 is formed on the upper surface of the packaging substrate 1 using a molding process to ensure that it completely covers all components from the upper surface of the packaging substrate 1 to the upper surface of the L-shaped heat sink 12. After the molding material has cured, the signal integrity and heat dissipation performance of the packaging structure are tested. Once it passes the test, it can be put into subsequent use.

Claims

1. A low-cost semiconductor packaging structure, comprising a packaging substrate (1), characterized in that: The upper surface of the packaging substrate (1) is welded with a bottom chip (3), the upper surface of the bottom chip (3) is welded with a multifunctional intermediate heat insulation layer (8), the lower surface of the multifunctional intermediate heat insulation layer (8) is welded with a first copper pillar (7), the interior of the multifunctional intermediate heat insulation layer (8) is welded with a connecting copper sheet (9), the upper surface of the multifunctional intermediate heat insulation layer (8) is welded with a second copper pillar (10), the first copper pillar (7) is welded to the connecting copper sheet (9), the first copper pillar (7) is welded to the upper surface of the bottom chip (3), the upper surface of the bottom chip (3) is an active surface, the connecting copper sheet (9) is welded to the second copper pillar (10), the upper surface of the multifunctional intermediate heat insulation layer (8) is welded with a top chip (11), the second copper pillar (10) is welded to the lower surface of the top chip (11), the lower surface of the top chip (11) is an active surface; The upper surface of the multifunctional intermediate heat insulation layer (8) is welded with an L-shaped heat sink (12), the lower surface of the L-shaped heat sink (12) is welded with a heat insulation frame (15), the heat insulation frame (15) is sleeved on the outside of the top chip (11), the upper surface of the L-shaped heat sink (12) is welded with a thermally conductive copper wire (16), the inside of the packaging substrate (1) is welded with a heat dissipation pad (17), and the end of the thermally conductive copper wire (16) away from the L-shaped heat sink (12) is welded to the upper surface of the heat dissipation pad (17).

2. The semiconductor packaging structure with low packaging cost according to claim 1, characterized in that: The outer side of the encapsulation substrate (1) is provided with a first groove (13).

3. The semiconductor packaging structure with low packaging cost according to claim 2, characterized in that: The outer side of the multifunctional intermediate heat insulation layer (8) is provided with a second groove (14).

4. The low-cost semiconductor packaging structure according to claim 3, characterized in that: The outer surface of the underlying chip (3) is welded with bonding leads (4).

5. A low-cost semiconductor packaging structure according to claim 4, characterized in that: The packaging substrate (1) has a bonding sheet (5) welded inside, and the bonding lead (4) is welded to the upper surface of the bonding sheet (5) at the end away from the bottom chip (3).

6. The semiconductor packaging structure with low packaging cost according to claim 5, characterized in that: The lower surface of the bonding sheet (5) is welded with solder balls (6).

7. A low-cost semiconductor packaging structure according to claim 6, characterized in that: The upper surface of the encapsulation substrate (1) is encapsulated with an epoxy encapsulation shell (2), and the vertical height of the epoxy encapsulation shell (2) covers all components from the upper surface of the encapsulation substrate (1) to the upper surface of the subsequent L-shaped heat sink (12).

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