Integrated packaging structure and computing system

Abstract

This application relates to an integrated packaging structure and a computing system. The integrated packaging structure includes: a glass substrate, comprising a glass core layer and a first wiring layer and a second wiring layer located on a first surface and a second surface of the glass core layer, respectively; thermally conductive pillar holes and heat sink mounting holes, respectively penetrating the first wiring layer, the glass core layer, and the second wiring layer; a plurality of first chips mounted on the first wiring layer; thermally conductive pillars disposed in corresponding thermally conductive pillar holes; a first heat sink, a second heat sink, and a plurality of fixing members. The fixing members pass through corresponding heat sink mounting holes to fix the first heat sink to the surface of the plurality of first chips away from the glass core layer, and fix the second heat sink to the surface of the second wiring layer away from the glass core layer. The two ends of the thermally conductive pillars contact the surfaces of the first and second heat sinks closest to the glass core layer, respectively. The integrated packaging structure of this application improves heat dissipation efficiency and reduces the risk of warpage.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and in particular to an integrated packaging structure and computing system. Background Technology

[0002] Due to the rapid development of technologies such as Artificial Intelligence (AI), server systems can be built using a multi-chip architecture, including memory chips (such as High Bandwidth Memory (HBM), Random Access Memory (RAM), and Non-Volatile Solid State Disk (NAND SSD) for processing exponentially growing data), processor chips (such as Central Processing Unit (CPU), Graphics Processing Unit (GPU), and Deep Computing Unit (DCU)), Application Specific Integrated Circuit (ASIC), Integrated Voltage Regulator (IVR), and Field Programmable Gate Array (FPGA).

[0003] Currently, key chips such as processor chips and memory chips are first packaged and then integrated onto a large motherboard (the motherboard is a PCB substrate). The motherboard interconnects with each other to form a complete server system. However, this packaging structure still has warping and heat dissipation problems. Utility Model Content

[0004] Based on this, this application provides an integrated packaging structure and computing system that can improve heat dissipation efficiency and reduce the risk of warpage.

[0005] In a first aspect, embodiments of this application provide an integrated packaging structure, including:

[0006] A glass substrate, comprising a glass core layer and a first wiring layer and a second wiring layer respectively located on a first surface and a second surface of the glass core layer, wherein the first surface and the second surface are opposite to each other.

[0007] Multiple heat-conducting pillar holes and multiple heat sink mounting holes penetrate the first wiring layer, the glass core layer and the second wiring layer respectively;

[0008] Multiple first chips are mounted on a first wiring layer, and the first chips are interconnected through the first wiring layer;

[0009] Multiple heat-conducting pillars are disposed in corresponding heat-conducting pillar holes, and the opposite ends of the heat-conducting pillars protrude from the surfaces of the first wiring layer and the second wiring layer away from the glass core layer, respectively.

[0010] The device comprises a first heat sink, a second heat sink, and multiple fasteners. The fasteners pass through corresponding heat sink mounting holes to fix the first heat sink to the surface of multiple first chips away from the glass core layer, and fix the second heat sink to the surface of the second wiring layer away from the glass core layer. The two ends of the heat-conducting pillars are in contact with the surfaces of the first and second heat sinks near the glass core layer, respectively.

[0011] In some embodiments of this application, the thermal conductivity of the heat-conducting pillar is greater than that of the glass core layer.

[0012] In some embodiments of this application, the heat-conducting pillar is made of metal or diamond.

[0013] In some embodiments of this application, a plurality of first chips include a high-power chip, and a number of heat-conducting pillars are located on one side or around the high-power chip.

[0014] In some embodiments of this application, the fastener includes a bolt, or a bolt and a nut.

[0015] In some embodiments of this application, the first radiator has a first mounting hole that penetrates two opposing surfaces of the first radiator, and the second radiator has a first threaded hole. A bolt passes through the first mounting hole and the radiator mounting hole and is screwed into the corresponding first threaded hole to fix the first radiator and the second radiator.

[0016] In some embodiments of this application, the second radiator has a second mounting hole that penetrates two opposing surfaces of the first radiator, and the first radiator has a second threaded hole. A bolt passes through the second mounting hole and the radiator mounting hole and is screwed into the corresponding second threaded hole to fix the first radiator and the second radiator.

[0017] In some embodiments of this application, the first radiator has a first mounting hole penetrating two opposing surfaces of the first radiator, and the second radiator has a second mounting hole penetrating two opposing surfaces of the first radiator. Bolts pass through the first mounting hole, the radiator mounting hole, and the second mounting hole, and are screwed into the corresponding nuts to fix the first radiator and the second radiator.

[0018] In some embodiments of this application, the contact interface between the first heat sink and the first chip and the heat-conducting pillar has a first thermally conductive layer.

[0019] In some embodiments of this application, the material of the first thermally conductive layer is thermally conductive silicone grease, thermally conductive gel, graphene, or carbon nanotubes.

[0020] In some embodiments of this application, a second thermally conductive layer is provided between the second heat sink and the second wiring layer.

[0021] In some embodiments of this application, the material of the second thermally conductive layer is a thermally conductive metal, or a combination of a thermally conductive metal and one of thermally conductive silicone grease, thermally conductive gel, graphene, or carbon nanotubes.

[0022] In some embodiments of this application, the glass core layer has a glass via interconnect structure that interconnects the first wiring layer and the second wiring layer.

[0023] The first wiring layer includes a first dielectric layer and a first connection line located in the first dielectric layer; the interconnection of the first chips through the first wiring layer includes: the interconnection of the first chips through the first connection line;

[0024] The second wiring layer includes a second dielectric layer and a second connection line located in the second dielectric layer; the glass via interconnect structure interconnects the first wiring layer and the second wiring layer, including: the glass via interconnect structure interconnects the first connection line and the second connection line.

[0025] In some embodiments of this application, the first wiring layer further includes a first ground line located in the first dielectric layer, and the second wiring layer further includes a second ground line located in the second dielectric layer;

[0026] The inner walls of the heat-conducting column holes and radiator mounting holes also have a metal shielding layer, which is electrically connected to the first ground wire and the second ground wire.

[0027] In some embodiments of this application, at least a portion of the first chips do not have a packaging substrate.

[0028] In some embodiments of this application, the plurality of first chips include: a central processing unit chip, a deep computing processor chip, an input / output interface chip, an integrated power supply chip, a random access memory chip, and a non-volatile memory chip, or a combination thereof;

[0029] Furthermore, the central processing unit chip, deep computing processor chip, and input / output interface chip do not have a packaging substrate.

[0030] In some embodiments of this application, a second chip is also mounted on the second wiring layer outside the second heat sink, and the second chip is electrically connected to the second wiring layer; the second chip includes one or a combination of an integrated power chip or a passive device.

[0031] In some embodiments of this application, it further includes: a co-packaged optoelectronic device and a connector mounted on the first wiring layer outside the first heat sink, wherein the co-packaged optoelectronic device and the connector are electrically connected to the first wiring layer.

[0032] Secondly, embodiments of this application also provide a computing system, including:

[0033] The aforementioned integrated packaging structure.

[0034] The embodiments of this application may have, or at least have, the following advantages:

[0035] This application embodiment integrates a packaging structure and a computing system. The integrated packaging structure includes: a glass substrate, which includes a glass core layer and a first wiring layer and a second wiring layer located on a first surface and a second surface of the glass core layer, respectively, with the first surface and the second surface facing away from each other; a plurality of heat-conducting pillar holes and a plurality of heat sink mounting holes, which respectively penetrate the first wiring layer, the glass core layer, and the second wiring layer; a plurality of first chips mounted on the first wiring layer, which are interconnected with each other through the first wiring layer; a plurality of heat-conducting pillars disposed in corresponding heat-conducting pillar holes, with the opposing ends of the heat-conducting pillars protruding from the surfaces of the first wiring layer and the second wiring layer away from the glass core layer; a first heat sink, a second heat sink, and a plurality of fasteners, which pass through corresponding heat sink mounting holes to fix the first heat sink to the surfaces of the plurality of first chips away from the glass core layer and to fix the second heat sink to the surface of the second wiring layer away from the glass core layer, with the ends of the heat-conducting pillars contacting the surfaces of the first heat sink and the second heat sink near the glass core layer, respectively. Since a first heat sink and a second heat sink are respectively provided on both sides of the glass substrate, the first heat sink and the second heat sink can dissipate heat from the upper and lower surfaces of the glass substrate respectively, thereby improving the heat dissipation efficiency.

[0036] Furthermore, since a glass substrate is used, which has high thermal conductivity, the heat generated by the first chip can be quickly transferred and dissipated to the second heat sink for release. And because the second heat sink is in direct contact with the second wiring layer of the glass substrate, the heat dissipation efficiency is further improved. In addition, the glass substrate has a low coefficient of thermal expansion, thereby effectively reducing the risk of warpage during the fabrication of integrated packaging structures using glass substrates (especially large-sized glass substrates).

[0037] Furthermore, since the glass substrate has heat-conducting pillar holes, and heat-conducting pillars are provided in the heat-conducting pillar holes, with the opposite ends of the heat-conducting pillars contacting the surfaces of the first heat sink and the second heat sink near the glass core layer respectively, the heat-conducting pillars can quickly transfer some of the heat generated in the glass substrate to the first heat sink and the second heat sink for release, preventing local overheating in the glass substrate and further improving the heat dissipation efficiency.

[0038] Furthermore, since the first heat sink and the second heat sink are mechanically fixed by fasteners, the first heat sink and the surface of the first chip away from the glass substrate have a good contact interface (reducing the risk of delamination or warping), and the second heat sink and the surface of the second wiring layer away from the glass core layer also have a good contact interface (reducing the risk of delamination or warping), so as to further improve heat dissipation efficiency.

[0039] Furthermore, in addition to securing the first and second heat sinks, the fasteners can also transfer some of the heat generated in the glass substrate to the first and second heat sinks for release, further improving heat dissipation efficiency. Moreover, the fasteners, the first heat sink, and the second heat sink can mechanically clamp the glass substrate, and the rigidity of the first and second heat sinks effectively reduces the risk of warping of the glass substrate (especially large-sized glass substrates).

[0040] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a cross-sectional schematic diagram of the integrated packaging structure provided in some embodiments of this application;

[0043] Figure 2 A cross-sectional structural diagram of the integrated packaging structure provided in some embodiments of this application for heat dissipation;

[0044] Figure 3 A schematic cross-sectional view of the integrated packaging structure fabrication method provided in some embodiments of this application after the glass core layer is provided;

[0045] Figure 4 This is a schematic cross-sectional view of the integrated packaging structure fabrication method provided in some embodiments of the present application, after forming glass through-holes penetrating the first and second surfaces, a first initial heat-conducting pillar hole, and a first initial heat sink mounting hole in the glass core layer;

[0046] Figure 5 This is a schematic cross-sectional view of the integrated packaging structure fabrication method provided in some embodiments of this application after forming a first metal layer and a second metal layer in the glass core layer;

[0047] Figure 6 This is a schematic cross-sectional view of the second metal layer and the first metal layer on the patterned first and second surfaces in the integrated packaging structure fabrication method provided in some embodiments of this application.

[0048] Figure 7 This is a schematic cross-sectional view of the integrated packaging structure fabrication method provided in some embodiments of this application after forming a portion of the first wiring layer and a portion of the second wiring layer;

[0049] Figure 8 This is a cross-sectional view of the integrated packaging structure fabrication method provided in some embodiments of this application after the formation of the first wiring layer and the second wiring layer.

[0050] Explanation of reference numerals in the attached figures:

[0051] Glass substrate 101; glass core layer 102; first wiring layer 103; second wiring layer 104; first dielectric layer 105; first connection line 106; second dielectric layer 107; second connection line 108; glass through-hole interconnection structure 109; heat-conducting pillar hole 110; first initial heat-conducting pillar hole 110a; heat-conducting pillar 111; heat sink mounting hole 112; first initial heat sink mounting hole 112a; fastener 113; glass through-hole 114; first metal layer 115; isolation layer 116; second metal layer 117; connecting pad 118; metal shielding layer 119; first ground wire 120; second ground wire 121; second thermally conductive layer 122;

[0052] First chip 201; Second chip 202; Connector 203; Optoelectronic co-packaged device 204; Optical fiber 205;

[0053] First radiator 301; Second radiator 302. Detailed Implementation

[0054] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0055] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0056] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0057] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0058] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0059] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.

[0060] Therefore, embodiments of this application provide an integrated packaging structure. Figure 1This is a cross-sectional schematic diagram of the integrated packaging structure provided in some embodiments of this application.

[0061] refer to Figure 1 The integrated packaging structure includes:

[0062] The glass substrate 101 includes a glass core layer 102 and a first wiring layer 103 and a second wiring layer 104 located on a first surface and a second surface of the glass core layer 102, respectively, with the first surface and the second surface facing away from each other.

[0063] Multiple heat-conducting pillar holes 110 and multiple heat sink mounting holes 112 respectively penetrate the first wiring layer 103, the glass core layer 102 and the second wiring layer 104;

[0064] Multiple first chips 201 are mounted on the first wiring layer 103, and the first chips 201 are interconnected through the first wiring layer 103.

[0065] Multiple heat-conducting pillars 111 are disposed in corresponding heat-conducting pillar holes 110, and the opposite ends of the heat-conducting pillars 111 protrude from the surfaces of the first wiring layer 103 and the second wiring layer 104 away from the glass core layer 102, respectively.

[0066] The first heat sink 301, the second heat sink 302, and a plurality of fasteners 113 pass through the corresponding heat sink mounting holes 112 to fix the first heat sink 301 to the surface of the plurality of first chips 201 away from the glass core layer 102, and fix the second heat sink 302 to the surface of the second wiring layer 104 away from the glass core layer 102. The two ends of the heat-conducting pillars 111 are in contact with the surfaces of the first heat sink 301 and the second heat sink 302 near the glass core layer 102, respectively.

[0067] Specifically, the glass substrate 101 serves as a support carrier for the integrated packaging structure and is used for signal connection between devices (such as the first chip 201). The thickness of the glass substrate 101 is designed according to actual needs, ranging from 0.5mm to 2mm. In some embodiments, the glass substrate 101 is a large-sized glass substrate to meet the packaging requirements of the integrated packaging structure. The glass substrate 101 is a square substrate, which can be a rectangular substrate or a square substrate. The length of the glass substrate 101 ranges from 100mm to 650mm, and the width of the glass substrate 101 ranges from 100mm to 650mm. In a specific example, the length of the glass substrate 101 is 512mm, and the width of the glass substrate 101 is 512mm, that is, the size of the glass substrate 101 is 512mm * 512mm. In another specific example, the size of the glass substrate 101 is 240mm * 240mm.

[0068] The glass substrate 101 may include a glass core layer 102, a first wiring layer 103 and a second wiring layer 104. The glass core layer 102 includes a first surface and a second surface that are opposite to each other. The first wiring layer 103 is located on the first surface of the glass core layer 102 and the second wiring layer 104 is located on the second surface of the glass core layer 102.

[0069] In some embodiments, the glass core layer 102 is selected from glass materials with low coefficient of thermal expansion (≤5 ppm / K) and high thermal conductivity (≥1W / m·K), such as borosilicate glass or quartz glass. The glass core layer 102 has a low coefficient of thermal expansion and high thermal conductivity, thereby effectively reducing the risk of warping when using glass substrate 101 (especially large-size glass substrate 101) in the process of preparing integrated packaging structure, while improving heat dissipation capacity.

[0070] In some embodiments, the glass core layer 102 has a glass via interconnect structure 109 that penetrates through the first surface and the second surface. The glass via interconnect structure 109 interconnects the first wiring layer 103 and the second wiring layer 104, that is, the first wiring layer 103 is electrically connected to the second wiring layer 104 through the glass via interconnect structure 109. In one example, the material of the glass via interconnect structure 109 may include one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0071] In some embodiments, the first wiring layer 103 includes a first dielectric layer 105 and a first connection line 106 located in the first dielectric layer 105; the interconnection of the first chips 201 through the first wiring layer 103 includes: the first chips 201 being interconnected through the first connection line 106. The first dielectric layer 105 may be a single-layer or multi-layer stacked structure, and the corresponding first connection line 106 may also be a single-layer or multi-layer stacked structure. In one example, the first dielectric layer 105 is a multi-layer stacked structure. For example, the first dielectric layer 105 can be a stacked structure with two, three, four or more layers. The corresponding first connection line 106 is also a multi-layer stacked structure. The number of layers of the first connection line 106 is the same as the number of layers of the first dielectric layer 105. The first connection line 106 of the upper layer is electrically connected to the first connection line 106 of the adjacent lower layer. For example, when the first dielectric layer 105 is two, three or four layers, the corresponding first connection line 106 can also be two, three or four layers. That is, each layer of the first dielectric layer 105 corresponds to one layer of the first connection line 106, and there is an electrical connection between the first connection lines 106 of the upper and lower layers.

[0072] In some embodiments, the first dielectric layer 105 is made of a resin material, including epoxy resin (such as ABF (Ajinomoto Build-up Film) resin), polyimide resin, benzocyclobutene resin, or polybenzoxazole resin. The material of the first connection line 106 may include one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. In other embodiments, the material of the first dielectric layer 105 may also be an inorganic dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.

[0073] In some embodiments, the second wiring layer 104 includes a second dielectric layer 107 and a second connection line 108 located in the second dielectric layer 107; the glass via interconnect structure 109 interconnects the first wiring layer 103 and the second wiring layer 104 by interconnecting the first connection line 106 and the second connection line 108. The second dielectric layer 107 can be a single-layer or multi-layer stacked structure, and the corresponding second connection line 108 can also be a single-layer or multi-layer stacked structure. In one example, the second dielectric layer 107 is a multi-layer stacked structure. For example, the second dielectric layer 107 can be a stacked structure with two, three, four or more layers. The corresponding second connection line 108 is also a multi-layer stacked structure. The number of layers of the second connection line 108 is the same as the number of layers of the second dielectric layer 107. The upper layer of the second connection line 108 is electrically connected to the adjacent lower layer of the second connection line 108. For example, when the second dielectric layer 107 is two, three or four layers, the corresponding second connection line 108 can also be two, three or four layers. That is, each layer of the second dielectric layer 107 corresponds to one layer of the second connection line 108, and there is an electrical connection between the upper and lower layers of the second connection line 108.

[0074] In some embodiments, the material of the second dielectric layer 107 is a resin material, including epoxy resin (such as ABF (Ajinomoto Build-up Film) resin), polyimide resin, benzocyclobutene resin, or polybenzoxazole resin. The material of the second connection line 108 may include one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. In other embodiments, the material of the second dielectric layer 107 may also be an inorganic dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.

[0075] In some embodiments, the first and / or second surfaces of the glass core layer 102 have microstructures (such as microchannels or micropores) for integration into a liquid cooling system to enhance heat conduction and heat dissipation efficiency.

[0076] In some embodiments, reference Figure 8 In addition to the first connection line 106 located in the first dielectric layer 105, the first wiring layer 103 also includes a first ground line 120 located in the first dielectric layer 105. In addition to the second connection line 108 located in the second dielectric layer 107, the second wiring layer 104 also includes a second ground line 121 located in the second dielectric layer 107. The inner walls of the heat-conducting pillar hole 110 and the heat sink mounting hole 112 also have a metal shielding layer 119, which is electrically connected to the first ground line 120 and the second ground line 121. On the one hand, by setting up the first ground wire 120, the second ground wire 121, and the metal shielding layer 119, the electrical signals transmitted in the first connection line 106 and the second connection line 108 can be prevented from being affected by external electromagnetic interference, and the transmission quality of the high-speed signals transmitted in the first connection line 106 and the second connection line 108 can be guaranteed and the loss reduced. On the other hand, the metal shielding layer 119 is made of a metal material with high thermal conductivity. The metal shielding layer 119 can quickly transfer the heat in the glass substrate 101 to the heat-conducting pillar 111 and the fixing member 113, and the heat in the heat-conducting pillar 111 and the fixing member 113 can be quickly transferred to the first heat sink 301 and the second heat sink 302 for release. In one example, the materials of the first ground wire 120, the second ground wire 121, and the metal shielding layer 119 include one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0077] Continue to refer to Figure 1 In conjunction with references Figure 8 The glass substrate 101 also has multiple heat-conducting pillar holes 110 and multiple heat sink mounting holes 112, which respectively penetrate the first wiring layer 103, the glass core layer 102, and the second wiring layer 104. Heat-conducting pillars 111 are provided in the heat-conducting pillar holes 110, and the opposite ends of the heat-conducting pillars 111 protrude from the surfaces of the first wiring layer 103 and the second wiring layer 104 away from the glass core layer 102. Fixing members 113 are provided in the heat sink mounting holes 112, and the fixing members 113 pass through the corresponding heat sink mounting holes 112 to fix the first heat sink 301 to the multiple first chips 2. The surface of the first heat sink 301 away from the glass core layer 102 is fixed to the surface of the second wiring layer 104 away from the glass core layer 102, and the two ends of the heat-conducting column 111 are in contact with the surfaces of the first heat sink 301 and the second heat sink 302 near the glass core layer 102, respectively (for example, the heat-conducting column 111 may include a first end and a second end that are opposite to each other, the first end of the heat-conducting column 111 is in contact with the surface of the first heat sink 301 near the glass core layer 102, and the second end of the heat-conducting column 111 is in contact with the surface of the second heat sink 302 near the glass core layer 102).

[0078] In the integrated packaging structure of this application, the first chip 201 includes a high-power chip, meaning that the first chip 201 generates a large amount of heat during operation. The heat generated by the first chip 201 is transferred towards the glass substrate 101 and the first heat sink 301 (see reference). Figure 2 , Figure 2 (The middle arrow 20 indicates the direction of heat transfer). In this application, since a first heat sink 301 and a second heat sink 302 are respectively provided on both sides of the glass substrate 101, the first heat sink 301 and the second heat sink 302 can dissipate heat from the upper and lower surfaces of the glass substrate 101 respectively, improving the heat dissipation efficiency. Furthermore, since a glass substrate 101 is used, it has a high thermal conductivity, which can quickly transfer and dissipate the heat generated by the first chip 201 to the second heat sink 302 for release. And since the second heat sink 302 is directly in contact with the glass substrate 101... The second wiring layer 104 of 01 is in contact, further improving the heat dissipation efficiency; and, since the glass substrate 101 has heat-conducting pillar holes 110, and heat-conducting pillars 111 are provided in the heat-conducting pillar holes 110, the two opposite ends of the heat-conducting pillars 111 are in contact with the surfaces of the first heat sink 301 and the second heat sink 302 near the glass core layer 102, the heat-conducting pillars 111 can quickly transfer some of the heat generated in the glass substrate 101 to the first heat sink 301 and the second heat sink 302 for release, preventing local overheating in the glass substrate 101 and further improving the heat dissipation efficiency. Furthermore, since the first heat sink 301 and the second heat sink 302 are mechanically fixed by the fastener 113, the first heat sink 301 has a good contact interface with the surface of the first chip 201 away from the glass substrate (reducing the risk of delamination or warping), and the second heat sink 302 also has a good contact interface with the surface of the second wiring layer 104 away from the glass core layer 102 (reducing the risk of delamination or warping), thereby further improving heat dissipation efficiency. In addition to fixing the first heat sink 301 and the second heat sink 302, the fastener 113 can also transfer some of the heat generated in the glass substrate 101 to the first heat sink 301 and the second heat sink 302 for release, further improving heat dissipation efficiency. Moreover, the glass substrate 101 can be clamped by the fastener 113, the first heat sink 301 and the second heat sink 302 through mechanical clamping, and the rigidity of the first heat sink 301 and the second heat sink 302 can effectively reduce the risk of warping of the glass substrate 101 (especially large-sized glass substrates 101).

[0079] In some embodiments, the thermal conductivity of the heat-conducting pillar 111 is greater than that of the glass core layer 102. In one example, the material of the heat-conducting pillar 111 is metal or diamond to improve the rate and efficiency of heat transfer by the heat-conducting pillar 111.

[0080] In some embodiments, a plurality of first chips 201 include a high-power chip, and a number of heat-conducting pillars 111 are located on one side or around the high-power chip to improve the heat dissipation efficiency of the glass substrate 101 under the high-power chip and avoid local overheating of the glass substrate 101.

[0081] In some embodiments, the fastener 113 includes bolts, or bolts and nuts, that is, the first radiator 301 and the second radiator 302 are mechanically fixed by bolts, or the first radiator 301 and the second radiator 302 are mechanically fixed by bolts and nuts. The bolts and nuts can be made of metal or alloy, specifically copper, copper alloy, aluminum, aluminum alloy, or stainless steel. In other embodiments, the fastener 113 can fix the first radiator 301 and the second radiator 302 by other mechanical fixing methods, such as fixing the first radiator 301 and the second radiator 302 by snap-fit, fitting, or buckling.

[0082] When the fastener 113 includes bolts, in some embodiments, the first radiator 301 has a first mounting hole penetrating two opposing surfaces of the first radiator 301, and the second radiator 302 has a first threaded hole. The bolt passes through the first mounting hole and the radiator mounting hole 112 and is screwed into the corresponding first threaded hole to fix the first radiator 301 and the second radiator 302.

[0083] When the fastener 113 includes bolts, in some embodiments, the second radiator 302 has a second mounting hole that penetrates two opposing surfaces of the first radiator 301, and the first radiator 301 has a second threaded hole. The bolt passes through the second mounting hole and the radiator mounting hole 112 and is screwed into the corresponding second threaded hole to fix the first radiator 301 and the second radiator 302.

[0084] When the fastener 113 includes bolts and nuts, in some embodiments, the first radiator 301 has a first mounting hole penetrating two opposing surfaces of the first radiator 301, and the second radiator 302 has a second mounting hole penetrating two opposing surfaces of the first radiator 301. The bolt passes through the first mounting hole, the radiator mounting hole 112, and the second mounting hole, and is screwed into the corresponding nut to fix the first radiator 301 and the second radiator 302.

[0085] The first heat sink 301 and the second heat sink 302 are made of materials with high thermal conductivity (such as copper or aluminum). In some examples, the surfaces of the first heat sink 301 and the second heat sink 302 may be coated with a high-efficiency heat-dissipating coating to enhance heat conduction and radiative heat dissipation. In some examples, a phase change material, such as paraffin wax or a metal alloy, may be embedded in the first heat sink 301 and the second heat sink 302. The phase change material undergoes a phase change when absorbing heat, absorbing a large amount of latent heat, thereby improving heat dissipation efficiency.

[0086] In some embodiments, the contact interface between the first heat sink 301 and the first chip 201 and the heat-conducting pillar 111 has a first thermally conductive layer (not shown in the figure). The first thermally conductive layer can improve the heat transfer efficiency, thereby further improving the heat dissipation efficiency. In one example, the material of the first thermally conductive layer is thermally conductive grease, thermally conductive gel, graphene, or carbon nanotubes.

[0087] In some embodiments, continue to refer to Figure 1 or Figure 8 A second thermally conductive layer 122 is provided between the second heat sink 302 and the second wiring layer 104. The second thermally conductive layer 122 can improve the heat transfer efficiency, thereby further improving the heat dissipation efficiency. In one example, the material of the second thermally conductive layer 122 is a thermally conductive metal (materials include Cu, Al, W, Ag, Au, Pt, Ni, Ti or Ta), or a combination of a thermally conductive metal and one of thermally conductive grease, thermally conductive gel, graphene or carbon nanotubes. For example, the second thermally conductive layer 122 can be a double-layer stacked structure of a thermally conductive metal layer and one of a thermally conductive grease layer, thermally conductive gel layer, graphene layer or carbon nanotube layer, wherein one side of the thermally conductive metal layer is in contact with the second wiring layer 104, the other side of the thermally conductive metal layer is in contact with one of the thermally conductive grease layer, thermally conductive gel layer, graphene layer or carbon nanotube layer, and the side of the thermally conductive grease layer, thermally conductive gel layer, graphene layer or carbon nanotube layer that is not in contact with the thermally conductive metal layer is in contact with the second heat sink 302. In one example, the material of the thermally conductive metal layer includes copper. On the one hand, copper has a high thermal conductivity, and on the other hand, the fabrication process of the thermally conductive metal layer (second thermally conductive layer 122) can be compatible with the fabrication process of the glass substrate 101.

[0088] In some embodiments, depending on the heat distribution of the chip and system requirements, the first heat sink 301 and the second heat sink 302 can be designed in non-traditional heat sink shapes, such as finned heat sinks or micro-needle heat sinks. These designs can increase the heat dissipation area and improve heat dissipation efficiency.

[0089] In some embodiments, the heat on the first heat sink 301 and the second heat sink 302 can be released by air cooling or liquid cooling. In some embodiments, the first heat sink 301 and the second heat sink 302 can also be dynamically controlled for heat dissipation. That is, the temperature of the first chip 201 is monitored in real time by a sensor, and the working state of the first heat sink 301 and the second heat sink 302 is dynamically adjusted according to the temperature change. For example, the rotation control of a micro fan or the speed control of a liquid cooling pump can be used to control the air speed of air cooling or the flow rate of the refrigerant in liquid cooling, so as to control the rate at which heat is released from the first heat sink 301 and the second heat sink 302, thereby achieving heat dissipation on demand.

[0090] Continue to refer to Figure 1 Multiple first chips 201 are mounted on the first wiring layer 103 of the glass substrate 101. In one example, the multiple first chips 201 are all soldered on the first wiring layer 103 of the glass substrate 101 by flip-chip process. The first chips 201 are interconnected through the first connection line 106 in the first wiring layer 103.

[0091] The plurality of first chips 201 include multiple chips with different functions. In some embodiments, the plurality of first chips 201 include one or a combination of a central processing unit (CPU die), a deep computing unit (DCU die), an input / output interface (IO die), a non-volatile memory (NAND Flash, or NAND SSD, or 3D NAND SSD), an integrated power controller (IVR), and a random access memory (RAM or 3D RAM). The number of CPU dies, deep computing unit dies, IVR chips, non-volatile memory chips, integrated power controllers, and random access memory chips can be one or more. In other embodiments, in addition to the aforementioned chips, the first chips 201 may also include chips with other functions, such as a graphics processing unit (GPU) or a field-programmable gate array (FPGA). In other embodiments, the first chips 201 may also include silicon interposer chips or interconnect layer chips.

[0092] In some embodiments, among the plurality of first chips 201, the central processing unit chip, the deep computing processor chip, and the input / output interface chip do not have a packaging substrate, while the first integrated power chip, the random access memory chip, and the optoelectronic co-packaged chip may or may not have a packaging substrate. That is, in this application, at least some of the first chips 201 are not soldered to the glass substrate 101 through a packaging substrate, but are directly soldered to the glass substrate 101, and interconnected through the first wiring layer 103 in the glass substrate 101. Therefore, in this application, the signal path from this portion of the first chips 201 to the glass substrate 101 will not have via connection structures located in the packaging substrate or ball grid arrays located on the surface of the packaging substrate, reducing impedance discontinuities in the signal path, avoiding a large number of reflections, thereby ensuring the integrity of the signal and power supply, and also reducing the length of the signal path, thereby reducing power consumption loss in the signal path.

[0093] In some embodiments, continue to refer to Figure 1 The integrated packaging structure also includes: a co-packaged optoelectronic device 204 and a connector 203 mounted on the first wiring layer 103 on the outside of the first heat sink 301, and the co-packaged optoelectronic device 204 and the connector 203 are electrically connected to the first wiring layer 103.

[0094] The optoelectronic co-packaged device 204 is used for optoelectronic signal conversion. The optoelectronic co-packaged device 204 has an interface for mounting an optical fiber 205, which enables signal transmission between the integrated package structure and the outside through the optical fiber 205.

[0095] Connector 203 is used for electrical connection with an external cable, through which power signals can be transmitted to connector 203.

[0096] In some embodiments, continue to refer to Figure 1 A second chip 202 is also mounted on the second wiring layer 104 outside the second heat sink 302, and the second chip 202 is electrically connected to the second wiring layer 104. In one example, the second chip 202 is soldered onto the second wiring layer 104 outside the second heat sink 302 using a flip-chip process. The second chip 202 includes one or a combination of an integrated power chip or a passive device, and the passive device includes one or more of a capacitor, an inductor, or a resistor.

[0097] This application also provides a computing system, including:

[0098] The aforementioned integrated packaging structure. The computing system comprises multiple first chips, including: a central processing unit chip, a deep learning processor chip, an input / output interface chip, an integrated power supply chip, a random access memory chip, and a non-volatile memory chip, or a combination thereof. The computing system of this application has good heat dissipation performance and reduces the risk of warpage.

[0099] In some embodiments, the computing system includes a server system.

[0100] This application also provides a method for fabricating an integrated packaging structure, which is described below in conjunction with the appendix in some embodiments. Figure 1 - Appendix Figure 8 The specific process of fabricating the integrated packaging structure is described in detail. It should be noted that the limitations or descriptions of the same or similar parts in this embodiment (fabrication method of integrated packaging structure) and the foregoing embodiments (integrated packaging structure) will not be repeated in this embodiment; please refer to the corresponding limitations or descriptions in the foregoing embodiments for details.

[0101] refer to Figure 1 The method for fabricating an integrated packaging structure includes:

[0102] A glass substrate 101 is provided, the glass substrate 101 includes a glass core layer 102 and a first wiring layer 103 and a second wiring layer 104 respectively located on a first surface and a second surface of the glass core layer 102, the first surface and the second surface being opposite to each other; the glass substrate 101 also has a plurality of heat-conducting pillar holes 110 and a plurality of heat sink mounting holes 112, which respectively penetrate the first wiring layer 103, the glass core layer 102 and the second wiring layer 104.

[0103] A plurality of first chips 201 are provided, and the plurality of first chips 201 are mounted on a first wiring layer 103, and the first chips 201 are interconnected through the first wiring layer 103.

[0104] Multiple heat-conducting pillars 111 are provided, and the multiple heat-conducting pillars 111 are respectively installed in the corresponding heat-conducting pillar holes 110. The opposite ends of the heat-conducting pillars 111 protrude from the surfaces of the first wiring layer 103 and the second wiring layer 104 away from the glass core layer 102.

[0105] A first heat sink 301, a second heat sink 302, and a plurality of fasteners 113 are provided. The fasteners 113 are passed through the corresponding heat sink mounting holes 112 to fix the first heat sink 301 to the surface of a plurality of first chips 201 away from the glass core layer 102, and fix the second heat sink 302 to the surface of the second wiring layer 104 away from the glass core layer 102. The two ends of the heat-conducting pillars 111 are in contact with the surfaces of the first heat sink 301 and the second heat sink 302 near the glass core layer 102, respectively.

[0106] In some embodiments, the method further includes: forming a first thermally conductive layer (not shown) between the first heat sink 301 and the contact interface between the first chip 201 and the thermally conductive pillar 111; and forming a second thermally conductive layer 122 between the second heat sink 302 and the second wiring layer 104. In one example, the material of the first thermally conductive layer is thermally conductive grease, thermally conductive gel, graphene, or carbon nanotubes; the material of the second thermally conductive layer 122 is a thermally conductive metal, or a combination of a thermally conductive metal and one of thermally conductive grease, thermally conductive gel, graphene, or carbon nanotubes.

[0107] In some embodiments, the glass core layer has a glass through-hole interconnect structure 109, which interconnects the first wiring layer 103 and the second wiring layer 104.

[0108] The first wiring layer 103 includes a first dielectric layer 105 and a first connection line 106 located in the first dielectric layer 105; the interconnection of the first chips 201 through the first wiring layer 103 includes: the first chips 201 interconnecting with each other through the first connection line 106.

[0109] The second wiring layer 104 includes a second dielectric layer 107 and a second connection line 108 located in the second dielectric layer 107; the glass via interconnect structure 109 interconnects the first wiring layer 103 and the second wiring layer 104, including: the glass via interconnect structure 109 interconnects the first connection line 106 and the second connection line 108.

[0110] In one embodiment, the first wiring layer 103 further includes a first ground line 120 located in the first dielectric layer 105, and the second wiring layer 104 further includes a second ground line 121 located in the second dielectric layer 107.

[0111] It also includes: forming a metal shielding layer 119 on the inner wall of the heat-conducting column hole 110 and the heat sink mounting hole 112, and the metal shielding layer 119 being electrically connected to the first ground wire 120 and the second ground wire 121.

[0112] The following embodiments, in conjunction with the appendix Figure 3 - Appendix Figure 8 The fabrication process of the aforementioned glass substrate 101 is described in detail.

[0113] The process of providing the aforementioned glass substrate 101 includes:

[0114] First, refer to Figure 3 The glass core layer 102 is provided, and the material of the glass core layer 102 is selected from glass materials with low coefficient of thermal expansion (≤5ppm / K) and high thermal conductivity (≥1 W / m·K), such as borosilicate glass or quartz glass.

[0115] Next, refer to Figure 4The glass core layer 102 is etched to form a glass through-hole 114, a first initial heat-conducting pillar hole 110a, and a first initial heat sink mounting hole 112a that penetrate the first and second surfaces in the glass core layer 102.

[0116] In some embodiments, before etching the glass core layer 102, a surface pretreatment is performed on the first and second surfaces of the glass core layer 102 that are opposite to each other to prepare for etching. The surface pretreatment includes ultraviolet light treatment or chemical solution immersion treatment, which generates a nanometer-thick metal oxide on the first and second surfaces of the glass core layer 102.

[0117] In some embodiments, the glass core layer 102 is etched by a combination of laser-induced and chemical etching. Specifically, a laser is first used to drill holes in the glass core layer 102, and then dry / wet etching is used to enlarge the hole size and eliminate microcracks.

[0118] The first initial heat-conducting orifice 110a serves as the heat-conducting orifice 110 (reference) Figure 8 As part of ), the first initial heatsink mounting hole 112a is the heatsink mounting hole 112 (reference). Figure 8 As part of the glass core layer 102, in some embodiments, a glass through-hole 114 and a first initial heat-conducting pillar hole 110a are formed in the middle region of the glass core layer 102, and a first initial heat sink mounting hole 112a is located in the edge region of the glass core layer 102, the edge region surrounding the middle region.

[0119] Next, refer to Figure 5 A first metal layer 115 is formed on the inner wall surface of the glass through-hole 114, the first initial heat-conducting pillar hole 110a and the first initial heat sink mounting hole 112a, as well as on the first surface and the second surface; an isolation layer 116 is formed to cover the inner wall of the glass through-hole 114 and fill the glass through-hole 114; a second metal layer 117 is formed on the surface of the first metal layer 115 and the surface of the isolation layer.

[0120] The first metal layer 115 on the inner wall surface of the glass through-hole 114 is used to form a glass through-hole interconnect structure. The first metal layer 115 and the second metal layer 117 on the inner wall surface of the first initial heat-conducting pillar hole 110a and the first initial heat sink mounting hole 112a are used as part of the metal shielding layer.

[0121] In some embodiments, the materials of the first metal layer 115 and the second metal layer 117 include one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN, and the process of forming the first metal layer 115 and the second metal layer 117 includes electroplating.

[0122] In some embodiments, the material of the insulating layer 116 includes resin.

[0123] Next, refer to Figure 6 The second metal layer 117 and the first metal layer 115 on the first and second surfaces are patterned, and a plurality of connecting pads 118 are formed on the first and second surfaces. The remaining first metal layer on the inner wall surface of the glass via 114 serves as a glass via interconnect structure 109. At least part of the connecting pads 118 are electrically connected to the corresponding glass via interconnect structure 109. The remaining first metal layer 115 and the second metal layer 117 on the inner wall surface of the first initial heat-conducting pillar hole 110a and the first initial heat sink mounting hole 112a serve as a first metal shielding layer. The first metal shielding layer is a part of the metal shielding layer 119.

[0124] The graphics are created using an etching process.

[0125] Next, refer to Figure 7 and Figure 8 A first wiring layer 103 is formed on the first surface, and a first connection line 106 in the first wiring layer 103 is electrically connected to a connection pad 118 on the first surface; a second wiring layer 104 is formed on the second surface, and a second connection line 108 in the second wiring layer 104 is electrically connected to a connection pad 118 on the second surface.

[0126] In some embodiments, the formation process of the first wiring layer 103 includes: sequentially forming at least one first dielectric layer 105 on a first surface; after forming each first dielectric layer 105, forming a first via in the corresponding first dielectric layer 105; and forming a first connection line 106 in the first via and on the surface of the first dielectric layer 105 away from the glass core layer 102. In some embodiments, the material of the first dielectric layer 105 is a resin film, specifically including an epoxy resin film (such as an ABF (Ajinomoto Build-up Film) resin film), a polyimide resin film, a benzocyclobutene resin film, or a polybenzoxazole resin film; the first dielectric layer 105 is formed by a film lamination process, and the first via is formed in the first dielectric layer 105 by a laser etching process. The material of the first connection line 106 may include one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN; the first connection line 106 is formed by an electroplating process. It should be noted that... Figure 8 In this example, the first dielectric layer 105 has three layers and the corresponding first connection line 106 has three layers. In other embodiments, the first dielectric layer 105 and the first connection line 106 can be other numbers of layers.

[0127] In some embodiments, the formation process of the second wiring layer 104 includes: sequentially forming at least one second dielectric layer 107 on the second surface; after forming each second dielectric layer 107, forming a second via in the corresponding second dielectric layer 107; and forming a second connection line 108 in the second via and on the surface of the second dielectric layer 107 away from the glass core layer 102. In some embodiments, the material of the second dielectric layer 107 is a resin film, specifically including an epoxy resin film (such as an ABF (Ajinomoto Build-up Film) resin film), a polyimide resin film, a benzocyclobutene resin film, or a polybenzoxazole resin film; the second dielectric layer 107 is formed by a film lamination process, and the second via is formed in the second dielectric layer 107 by a laser etching process. The material of the second connection line 108 may include one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN; the second connection line 108 is formed by an electroplating process. It should be noted that... Figure 8 In this example, the second dielectric layer 107 has three layers and the corresponding second connection line 108 has three layers. In other embodiments, the second dielectric layer 107 and the second connection line 108 can have other numbers of layers.

[0128] In some embodiments, continue to refer to Figure 7 and Figure 8 When the first via is formed in the first dielectric layer 105, a second initial heat-conducting pillar hole (not shown in the figure) and a second initial heat sink mounting hole (not shown in the figure) are simultaneously formed in the first dielectric layer 105. The second initial heat-conducting pillar hole is connected to the first initial heat-conducting pillar hole 110a in a manner perpendicular to the first surface, and the second initial heat sink mounting hole is connected to the first initial heat sink mounting hole 112a in a manner perpendicular to the first surface.

[0129] While forming the first connection line 106, a first ground line 120 is formed on the surface of the first dielectric layer 105 away from the glass core layer 102. A second metal shielding layer is formed on the sidewall of the second initial heat conduction pillar hole 110 and the second initial heat sink mounting hole 112. The second metal shielding layer is electrically connected to the first ground line 120. The second metal shielding layer is part of the metal shielding layer 119.

[0130] When the second via is formed in the second dielectric layer 107, a third initial heat-conducting pillar hole (not shown in the figure) and a third initial heat sink mounting hole (not shown in the figure) are simultaneously formed in the second dielectric layer 107. The third initial heat-conducting pillar hole is connected to the first initial heat-conducting pillar hole 110a in a manner perpendicular to the second surface, and the third initial heat sink mounting hole is connected to the first initial heat sink mounting hole 112a in a manner perpendicular to the second surface. The first initial heat-conducting pillar hole 110a, the second initial heat-conducting pillar hole, and the third initial heat-conducting pillar hole constitute the heat-conducting pillar hole 110 (see reference). Figure 8 The first initial radiator mounting hole 112a, the second initial radiator mounting hole, and the second initial radiator mounting hole constitute the radiator mounting hole 112 (reference). Figure 8 );

[0131] While forming the second connection line 108, a second ground line 121 is formed on the surface of the second dielectric layer 107 away from the glass core layer 102. A third metal shielding layer is formed on the sidewall of the third initial heat conduction pillar hole and the third initial heat sink mounting hole. The third metal shielding layer is electrically connected to the second ground line 121. The first metal shielding layer, the second metal shielding layer and the third metal shielding layer constitute a metal shielding layer 119.

[0132] In some embodiments, the method further includes mounting a second chip 202 on the second wiring layer 104, the second chip 202 being located outside the second heat sink 302, and the second chip 202 being electrically connected to the second wiring layer 104.

[0133] In some embodiments, the method further includes mounting an optoelectronic co-packaged device 204 and a connector 203 on the first wiring layer 103, wherein the optoelectronic co-packaged device 204 and the connector 203 are located on the outside of the first heat sink 301 and are electrically connected to the first wiring layer 103.

[0134] In some embodiments, continue to refer to Figure 8 It also includes: forming a second thermally conductive layer 122 on the surface of the second wiring layer 104 away from the glass core layer 102, wherein the material of the second thermally conductive layer 122 is a thermally conductive metal, such as copper, and the process for forming the second thermally conductive layer is electroplating.

[0135] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0136] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0137] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An integrated packaging structure, characterized in that, include: A glass substrate, the glass substrate comprising a glass core layer and a first wiring layer and a second wiring layer respectively located on a first surface and a second surface of the glass core layer, the first surface and the second surface being opposite to each other; Multiple heat-conducting pillar holes and multiple heat sink mounting holes respectively penetrate the first wiring layer, the glass core layer and the second wiring layer; Multiple first chips are mounted on the first wiring layer, and the first chips are interconnected through the first wiring layer; Multiple heat-conducting pillars are disposed in corresponding heat-conducting pillar holes, and the opposite ends of the heat-conducting pillars protrude from the surfaces of the first wiring layer and the second wiring layer away from the glass core layer, respectively. The device comprises a first heat sink, a second heat sink, and a plurality of fasteners. The fasteners pass through corresponding heat sink mounting holes to fix the first heat sink to the surface of the plurality of first chips away from the glass core layer, and fix the second heat sink to the surface of the second wiring layer away from the glass core layer. The two ends of the heat-conducting pillars are respectively in contact with the surfaces of the first heat sink and the second heat sink near the glass core layer.

2. The integrated packaging structure according to claim 1, characterized in that, The thermal conductivity of the heat-conducting column is greater than that of the glass core layer.

3. The integrated packaging structure according to claim 2, characterized in that, The heat-conducting column is made of metal or diamond.

4. The integrated packaging structure according to claim 1, characterized in that, The plurality of the first chips includes a high-power chip, and a portion of the heat-conducting pillars are located on one side or around the high-power chip.

5. The integrated packaging structure according to claim 1, characterized in that, The fastener includes a bolt, or a bolt and a nut.

6. The integrated packaging structure according to claim 5, characterized in that, The first radiator has a first mounting hole that penetrates two opposing surfaces of the first radiator, and the second radiator has a first threaded hole. The bolt passes through the first mounting hole and the radiator mounting hole and is screwed into the corresponding first threaded hole to fix the first radiator and the second radiator.

7. The integrated packaging structure according to claim 5, characterized in that, The second radiator has a second mounting hole that penetrates two opposing surfaces of the first radiator. The first radiator has a second threaded hole. The bolt passes through the second mounting hole and the radiator mounting hole and is screwed into the corresponding second threaded hole to fix the first radiator and the second radiator.

8. The integrated packaging structure according to claim 5, characterized in that, The first radiator has a first mounting hole that penetrates two opposing surfaces of the first radiator, and the second radiator has a second mounting hole that penetrates two opposing surfaces of the first radiator. The bolt passes through the first mounting hole, the radiator mounting hole and the second mounting hole, and is screwed into the corresponding nut to fix the first radiator and the second radiator.

9. The integrated packaging structure according to claim 1, characterized in that, The contact interface between the first heat sink and the first chip and the heat-conducting pillar has a first thermally conductive layer.

10. The integrated packaging structure according to claim 9, characterized in that, The material of the first thermal conductive layer is thermally conductive silicone grease, thermally conductive gel, graphene, or carbon nanotubes.

11. The integrated packaging structure according to claim 1, characterized in that, A second thermally conductive layer is provided between the second heat sink and the second wiring layer.

12. The integrated packaging structure according to claim 11, characterized in that, The material of the second thermally conductive layer is a thermally conductive metal, or a combination of a thermally conductive metal and one of thermally conductive silicone grease, thermally conductive gel, graphene, or carbon nanotubes.

13. The integrated packaging structure according to claim 1, characterized in that, The glass core layer has a glass through-hole interconnect structure, which interconnects the first wiring layer and the second wiring layer. The first wiring layer includes a first dielectric layer and a first connection line located in the first dielectric layer; The interconnection between the first chips via the first wiring layer includes: the interconnection between the first chips via the first connection line; The second wiring layer includes a second dielectric layer and a second connection line located in the second dielectric layer; the glass via interconnect structure interconnects the first wiring layer and the second wiring layer by: the glass via interconnect structure interconnects the first connection line and the second connection line.

14. The integrated packaging structure according to claim 13, characterized in that, The first wiring layer further includes a first ground line located in the first dielectric layer, and the second wiring layer further includes a second ground line located in the second dielectric layer; The inner walls of the heat-conducting column holes and the radiator mounting holes are also provided with a metal shielding layer, which is electrically connected to the first ground wire and the second ground wire.

15. The integrated packaging structure according to claim 1, characterized in that, At least a portion of the first chips do not have a packaging substrate.

16. The integrated packaging structure according to claim 11, characterized in that, The plurality of the first chips include: a central processing unit chip, a deep computing processor chip, an input / output interface chip, an integrated power supply chip, a random access memory chip, and a non-volatile memory chip, or a combination thereof; Furthermore, the central processing unit chip, the deep computing processor chip, and the input / output interface chip do not have a packaging substrate.

17. The integrated packaging structure according to claim 1, characterized in that, A second chip is also mounted on the second wiring layer on the outside of the second heat sink, and the second chip is electrically connected to the second wiring layer; the second chip includes one or a combination of an integrated power chip or a passive device.

18. The integrated packaging structure according to claim 1, characterized in that, Also includes: The optoelectronic co-encapsulated device and connector are mounted on the first wiring layer outside the first heat sink, and the optoelectronic co-encapsulated device and connector are electrically connected to the first wiring layer.

19. A computing system, characterized in that, include: The integrated packaging structure according to any one of claims 1-18.

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