A burn-in board for a multi-level SiP circuit

Abstract

The utility model discloses a kind of old board of multilevel SiP circuit, and SiP circuit corresponding level is SiP circuit old module;SiP circuit includes four DSP micro components, and multiple resistors connected with DSP micro component, multiple SiP power supply chips, SiP clock, multiple SiP JTAG connectors;Every DSP micro component includes two storage micro components and a bare core;Four DSP micro components are mutually electrically connected between.Between the utility model uses a kind of old board can complete multilevel SiP circuit from micro component, micro component to SiP circuit's complete set of old, reduce the hardware and design cost of old test, improve the reliability of each level circuit, for the old test of multilevel SiP circuit has very strong universality.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit technology, and in particular relates to a refining board for a multi-level SiP circuit. Background Technology

[0002] According to GJB 548C method 1051.1, aging tests can screen out and identify devices with potential risks. Without aging tests, these defective devices will experience early fatal failure or early life failure under operating conditions.

[0003] Multi-level SiP circuits include bare dies, micro-components, micro-devices, and SiP circuits. They are characterized by complex internal designs, a large number of external pins, and high packaging difficulty. The design, packaging, and testing costs of this type of circuit are very high, the development cycle and iterative upgrade cycle are very long, and the circuits are not repairable. To improve the reliability of the circuits, aging tests are essential.

[0004] Traditional aging tests are difficult to achieve comprehensive aging of micro-components, micro-parts, and SiP circuits. If only SiP circuits are aged without reliability testing of the internal micro-components and micro-parts, defective micro-components and micro-parts cannot be screened out in the early stages. This not only leads to a decrease in the packaging yield and reliability of multi-level SiP circuits, but also increases R&D costs. Utility Model Content

[0005] The purpose of this invention is to solve the problem of difficulty in removing defective micro-components and micro-parts in multi-level SiP circuits, and to propose a new type of multi-level SiP circuit board.

[0006] To achieve the purpose of this utility model, this utility model provides a multi-level SiP circuit aging board, including SiP circuits; the SiP circuits correspond to a SiP circuit aging module; the SiP circuits include four DSP micro-components, and multiple resistors, multiple SiP power chips, a SiP clock, and multiple SiP JTAG connectors connected to the DSP micro-components; the DSP micro-components are DSP micro-component 1, DSP micro-component 2, DSP micro-component 3, and DSP micro-component 4; each DSP micro-component includes two memory micro-components and one bare die; the four DSP micro-components are electrically connected to each other.

[0007] Specifically, DSP micro-component 1 includes storage micro-component 1, storage micro-component 2, and bare die 1; DSP micro-component 2 includes storage micro-component 3, storage micro-component 4, and bare die 2; DSP micro-component 3 includes storage micro-component 5, storage micro-component 6, and bare die 3; DSP micro-component 4 includes storage micro-component 7, storage micro-component 8, and bare die 4.

[0008] Among them, resistors 1 to 2020 are connected to the signal and reset interface of the SiP circuit at one end and to the output terminal of power supply 1 at the other end; SiP power chip 1 to SiP power chip 20 are connected to the power input terminal of the SiP circuit at one end and to the output terminal of power supply 2 at the other end; SiP clock is connected to the clock input terminal of the SiP circuit at one end and to the output terminal of power supply 2 at the other end; SiP JTAG connector 1 to SiP JTAG connector 4 are connected to the JTAG pin of the SiP circuit at one end and to the external JTAG adapter at the other end.

[0009] The corresponding level for the DSP micro-components is the micro-component aging module; the internal structures of the four DSP micro-components are identical, and the numbers of the micro-components, resistors, capacitors, micro-component power chips, micro-component clocks, and micro-component JTAG connectors in the micro-component aging module increase sequentially according to the serial number of the micro-component aging module.

[0010] Resistors 2021 to 2525 in DSP micro-component 1 are connected sequentially at one end to the micro-component signal and reset interfaces, and at the other end to the output of power supply 1. Power chips 1 to 5 are connected at one end to the power input of DSP micro-component 1 and at the other end to the output of power supply 2. Clock 1 is connected at one end to the clock input of DSP micro-component 1 and at the other end to the output of power supply 2. JTAG connector 1 is connected at one end to the JTAG pin of DSP micro-component 1 and at the other end to the external JTAG adapter. Capacitor 32 is connected at one end to high-speed signal 1 of DSP micro-component 1 and at the other end to high-speed signal 64 of DSP micro-component 1. Capacitor 31 is connected at one end to high-speed signal 2 of DSP micro-component 1 and at the other end to high-speed signal 63 of DSP micro-component 1. The remaining 30 capacitors are connected sequentially.

[0011] The micro-component aging module 4, i.e., the DSP micro-component 4, has resistors 3536 to 4040 connected at one end to the DSP micro-component 4 signal and reset interface, and at the other end to the output of power supply 1. Micro-component power chips 16 to 20 are connected at one end to the power input of the DSP micro-component 4, and at the other end to the output of power supply 2. Micro-component clock 4 is connected at one end to the clock input of the DSP micro-component 4, and at the other end to the output of power supply 2. JTAG connector 4 is connected at one end to the JTAG pin of the DSP micro-component 4, and at the other end to the external JTAG adapter. Capacitor 128 is connected at one end to the DSP micro-component 4 high-speed signal 1, and at the other end to the DSP micro-component 4 high-speed signal 64. Capacitor 127 is connected at one end to the DSP micro-component 4 high-speed signal 2, and at the other end to the DSP micro-component 4 high-speed signal 63. The remaining 30 capacitors are connected in sequence.

[0012] The storage micro-component corresponds to the micro-component aging module; the internal structure of the micro-component aging modules is the same; the numbers of the stored micro-components, DSP chips, micro-component power chips, and micro-component clocks in the micro-component aging module increase sequentially according to the serial number of the micro-component aging module;

[0013] In the micro-component aging module 1, one end of the power chip 1 is connected to the power input terminal of the DSP chip 1, and the other end is connected to the output terminal of the power supply 2. One end of the micro-component clock 1 is connected to the clock input terminal of the DSP chip 1, and the other end is connected to the output terminal of the power supply 2. One end of the DSP JTAG connector 1 is connected to the DSP chip 1, and the other end is connected to the output terminal of the power supply 2. One end of the storage micro-component 1 is connected to the DSP chip 1, and the other end is connected to the power supply 2. One end of the storage micro-component 2 is connected to the DSP chip 1, and the other end is connected to the power supply 2.

[0014] In the micro-component aging module 4, one end of the power chip 4 is connected to the power input terminal of the DSP chip 4, and the other end is connected to the output terminal of the power supply 2. One end of the micro-component clock 4 is connected to the clock input terminal of the DSP chip 4, and the other end is connected to the output terminal of the power supply 2. One end of the DSP JTAG connector 4 is connected to the DSP chip 4, and the other end is connected to the output terminal of the power supply 2. One end of the storage micro-component 7 is connected to the DSP chip 4, and the other end is connected to the power supply 2. One end of the storage micro-component 8 is connected to the DSP chip 4, and the other end is connected to the power supply 2.

[0015] Furthermore, the resistance values ​​of resistors 1 to 2020 in the SiP circuit aging module and resistors 2021 to 4040 in the micro-component aging module are all 4.7K, and the resistor package is a 0402 package.

[0016] Furthermore, the power chip model of SiP power chips 1 to 20 in the SiP circuit aging module, micro-component power chips 1 to 20 in the micro-component aging module, and micro-component power chips 1 to 4 in the micro-component aging module is LTM4644.

[0017] Furthermore, the clock models of the SiP clock in the SiP circuit aging module, micro-component clocks 1 to 4 in the micro-component aging module, and micro-component group clocks 1 to 4 in the micro-assembly aging module are all Au5411AQMT.

[0018] Furthermore, the connector model of SiP JTAG connectors 1 to 4 in the SiP circuit aging module, micro-component JTAG connectors 1 to 4 in the micro-component aging module, and DSP JTAG connectors 1 to 4 in the micro-assembly aging module is FT-EMU.

[0019] Furthermore, in the micro-component aging module, capacitors 1 to 128 all have a capacitance of 0.1uF, a voltage rating of 6.3V, and a 0402 package.

[0020] Furthermore, the input voltage of power supply 1 and power supply 2 is 220V, and the output voltage is 12V.

[0021] Compared with the prior art, the beneficial effects of the aging board for multi-level SiP circuits of this utility model are: using one aging board can complete the entire aging process of multi-level SiP circuits from micro-components and micro-parts to SiP circuits, reducing the hardware and design costs of aging tests, improving the reliability of circuits at each level, and having strong versatility for aging tests of multi-level SiP circuits.

[0022] To more clearly illustrate the functional characteristics and structural parameters of this utility model, the following description is provided in conjunction with the accompanying drawings and specific embodiments. Attached Figure Description

[0023] Figure 1 is a schematic diagram of the structure of this utility model; wherein, (a) is a schematic diagram of the SiP circuit curing module; (b) is a schematic diagram of the micro-component curing module 1; (c) is a schematic diagram of the micro-component curing module 4; (d) is a schematic diagram of the micro-assembly curing module 1; and (e) is a schematic diagram of the micro-assembly curing module 4.

[0024] Figure 2 This is a schematic diagram of a SiP circuit structure;

[0025] Figure 3 Schematic diagram of the pin distribution of a 1-bit SiP circuit;

[0026] Figure 4 Here are schematic diagrams of the structures of micro-component 1, micro-component 2, micro-component 3, and micro-component 4;

[0027] Figure 5 This is a schematic diagram showing the pin distribution of micro-component 1, micro-component 2, micro-component 3, and micro-component 4.

[0028] Figure 6 This is a schematic diagram of the structure of storage micro-component 1, storage micro-component 3, storage micro-component 5, and storage micro-component 7;

[0029] Figure 7 This is a schematic diagram of the structure of storage micro-component 2, storage micro-component 4, storage micro-component 6, and storage micro-component 8. Detailed Implementation

[0030] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the protection scope of the present utility model.

[0031] As shown in Figure 1, Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 As shown, a multi-level SiP circuit aging board has a hierarchical relationship from largest to smallest as follows: SiP circuit aging module, four identical micro-component aging module and four identical micro-assembly aging module.

[0032] The SiP circuit aging module includes DSP micro-component 1, DSP micro-component 2, DSP micro-component 3, and DSP micro-component 4.

[0033] Micro-component 1 includes storage micro-component 1, storage micro-component 2 and bare die 1; micro-component 2 includes storage micro-component 3, storage micro-component 4 and bare die 2; micro-component 3 includes storage micro-component 5, storage micro-component 6 and bare die 3; micro-component 4 includes storage micro-component 7, storage micro-component 7 and bare die 4.

[0034] SiP signal interfaces 1 to 2000 and SiP reset interfaces 1 to 20 are connected to resistors 1 to 2020 in sequence. The other end of resistors 1 to 2020 is connected to the output terminal of power supply 1.

[0035] The power input terminal of the SiP circuit is connected to SiP power chip 1 to SiP power chip 20, and the other end of SiP power chip 1 to SiP power chip 20 is connected to the output terminal of power supply 2.

[0036] The clock input terminal of the SiP circuit is connected to the SiP clock, and the other end of the SiP clock is connected to the output terminal of power supply 2.

[0037] The JTAG pins of the SiP circuit are connected to SiP JTAG connector 1 to SiP JTAG connector 4, and the other end of SiP JTAG connector 1 to SiP JTAG connector 4 is connected to an external JTAG adapter.

[0038] Signal interfaces 1 to 500 and reset interfaces 1 to 5 of DSP microcomponent 1 are connected to resistors 2021 to 2525 in sequence. The other ends of resistors 2021 to 2525 are connected to the output terminals of power supply 1.

[0039] The power input terminal of DSP micro-component 1 is connected to power chips 1 to 5 of micro-component power chips, and the other end of power chips 1 to 5 of micro-component power chips is connected to the output terminal of power supply 2.

[0040] The clock input terminal of DSP micro-component 1 is connected to micro-component clock 1, and the other end of micro-component clock 1 is connected to the output terminal of power supply 2.

[0041] The JTAG pin of DSP micro-component 1 is connected to JTAG connector 1, and the other end of JTAG connector 1 is connected to an external JTAG adapter.

[0042] DSP micro-component 1 high-speed signal 1 is connected to capacitor 32, and the other end of capacitor 32 is connected to micro-component 1 high-speed signal 64. Micro-component 1 high-speed signal 2 is connected to capacitor 31, and the other end of capacitor 31 is connected to micro-component 1 high-speed signal 63. The remaining 30 capacitors are connected in sequence.

[0043] The four micro-component aging modules have the same design method, and the micro-components, resistors, capacitors, micro-component power chips, micro-component clocks, and micro-component JTAG connectors within the modules are numbered sequentially.

[0044] Signal interfaces 1501 to 2000 and reset interfaces 16 to 20 of DSP micropart 4 are connected to resistors 3536 to 4040 in sequence. The other end of resistors 3536 to 4040 is connected to the output terminal of power supply 1.

[0045] The power input terminal of DSP micro-component 4 is connected to the power supply chips 16 to 20 of micro-component power supply chips, and the other end of the power supply chips 16 to 20 of micro-component power supply chips is connected to the output terminal of power supply 2.

[0046] The clock input terminal of DSP micro-component 4 is connected to micro-component clock 4, and the other end of micro-component clock 4 is connected to the output terminal of power supply 2.

[0047] The JTAG pin of micro-component 4 is connected to JTAG connector 4, and the other end of JTAG connector 4 is connected to an external JTAG adapter.

[0048] The high-speed signal 255 of DSP micro-component 4 is connected to capacitor 128. The other end of capacitor 128 is connected to high-speed signal 512 of micro-component 4. The high-speed signal 256 of micro-component 4 is connected to capacitor 127. The other end of capacitor 127 is connected to high-speed signal 511 of micro-component 4. The remaining 30 capacitors are connected in sequence.

[0049] The power input terminal of DSP chip 1 is connected to micro-component power chip 1, and the other end of micro-component power chip 1 is connected to the output terminal of power supply 2.

[0050] The clock input terminal of DSP chip 1 is connected to micro-component clock 1, and the other end of micro-component clock 1 is connected to the output terminal of power supply 2.

[0051] The JTAG interface 1 of DSP chip 1 is connected to DSP JTAG connector 1, and the other end of DSP JTAG connector 1 is connected to the output of power supply 2.

[0052] One end of the storage micro-component 1 is connected to the DSP chip 1, and the other end is connected to the power supply 2.

[0053] One end of the storage micro-component 2 is connected to the DSP chip 1, and the other end is connected to the power supply 2.

[0054] The four micro-component aging modules are designed in the same way, and the micro-components, DSP chips, micro-component power chips and micro-component clocks stored in the modules are numbered sequentially.

[0055] The power input terminal of DSP chip 4 is connected to micro-component power chip 4, and the other end of micro-component power chip 4 is connected to the output terminal of power supply 2.

[0056] The clock input terminal of DSP chip 4 is connected to micro-component clock 4, and the other end of micro-component clock 4 is connected to the output terminal of power supply 2.

[0057] The JTAG interface 4 of DSP chip 4 is connected to DSP JTAG connector 4, and the other end of DSP JTAG connector 4 is connected to the output of power supply 2.

[0058] One end of the storage micro-component 7 is connected to the DSP chip 4, and the other end is connected to the power supply 2.

[0059] One end of the storage micro-component 8 is connected to the DSP chip 4, and the other end is connected to the power supply 2.

[0060] All resistors from resistor 1 to resistor 4040 have a resistance value of 4.7K and are packaged in a 0402 package. The power chip models for SiP power chips 1 to 20, micro-component power chips 1 to 20, and micro-assembly power chips 1 to 4 are all LTM4644. The clock models for the SiP clock, micro-component clocks 1 to 4, and micro-assembly clocks 1 to 4 are all Au5411AQMT. The connector models for SiP JTAG connectors 1 to 4 and micro-component JTAG connectors 1 to 4 are all FT-EMU. All capacitors from capacitor 1 to 128 have a capacitance value of 0.1uF, a voltage rating of 6.3V, and are packaged in a 0402 package. Power supplies 1 and 2 have an input voltage of 220V and an output voltage of 12V, provided by an external DC regulated power supply.

[0061] The SiP circuit dynamic aging test program is loaded into the SiP circuit through SiP JTAG connectors 1 to 4. The micro-component dynamic aging program is loaded into the micro-component through micro-component JTAG connectors 1 to 4. The micro-component dynamic aging program is loaded into the DSP chip through DSP JTAG connectors 1 to 4.

[0062] like Figure 3 As shown, the SiP circuit is packaged in CCGA2209. The SiP signal interface pins are A1 to BC26, the SiP reset interface pins are BC27 to BC46, the SiP JTAG1 pins are BC47 to BD4, the SiP JTAG2 pins are BD5 to BD9, the SiP JTAG3 pins are BD10 to BD14, the SiP JTAG4 pins are BD15 to BD19, the SiP clock pins are BD20 to BD34, the SiP power supply 1 to SiP power supply 20 pins are BD35 to BF10, and the remaining pins are grounded.

[0063] like Figure 5 As shown, the micro-component package is PBGA682. The SiP signal interface pins are distributed as A1 to U4, the micro-component reset interface pins are distributed as U5 to U10, the micro-component JTAG pins are distributed as U11 to U15, the micro-component clock pins are distributed as U16 to U20, the micro-component high-speed signal pins are distributed as U21 to W11, the micro-component power supply pins are distributed as W11 to AA5, and the remaining pins are grounded.

[0064] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present utility model shall still fall within the protection scope of the present utility model.

[0065] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A refining board for a multi-level SiP circuit, characterized in that, Including old SiP circuit boards; The corresponding level for SiP circuits is the SiP circuit aging module. The SiP circuit includes four DSP micro-components, as well as multiple resistors, multiple SiP power chips, a SiP clock, and multiple SiP JTAG connectors connected to the DSP micro-components. The DSP micro-components are DSP micro-component 1, DSP micro-component 2, DSP micro-component 3, and DSP micro-component 4; Each DSP micro-part includes two memory micro-assemblies and one bare die; the four DSP micro-parts are electrically interconnected.

2. The aged refining plate according to claim 1, characterized in that, in, Resistors 1 to 2020 are connected at one end to the SiP circuit signal and reset interface, and at the other end to the output of power supply 1. SiP power chips 1 to 20 are connected at one end to the power input of the SiP circuit, and at the other end to the output of power supply 2. SiP clock is connected at one end to the clock input of the SiP circuit, and at the other end to the output of power supply 2. SiP JTAG connectors 1 to 4 are connected at one end to the JTAG pin of the SiP circuit, and at the other end to the external JTAG adapter.

3. The aged refining plate according to claim 2, characterized in that, The corresponding level for the DSP micro-components is the micro-component aging module; the internal structures of the four DSP micro-components are identical, and the numbers of the micro-components, resistors, capacitors, micro-component power chips, micro-component clocks, and micro-component JTAG connectors in the micro-component aging module increase sequentially according to the serial number of the micro-component aging module. Resistors 2021 to 2525 in DSP micro-component 1 are connected sequentially at one end to the micro-component signal and reset interfaces, and at the other end to the output of power supply 1. Power chips 1 to 5 are connected at one end to the power input of DSP micro-component 1 and at the other end to the output of power supply 2. Clock 1 is connected at one end to the clock input of DSP micro-component 1 and at the other end to the output of power supply 2. JTAG connector 1 is connected at one end to the JTAG pin of DSP micro-component 1 and at the other end to the external JTAG adapter. Capacitor 32 is connected at one end to high-speed signal 1 of DSP micro-component 1 and at the other end to high-speed signal 64 of DSP micro-component 1. Capacitor 31 is connected at one end to high-speed signal 2 of DSP micro-component 1 and at the other end to high-speed signal 63 of DSP micro-component 1. The remaining 30 capacitors are connected sequentially. The micro-component aging module 4, i.e., the DSP micro-component 4, has resistors 3536 to 4040 connected at one end to the DSP micro-component 4 signal and reset interface, and at the other end to the output of power supply 1. Micro-component power chips 16 to 20 are connected at one end to the power input of the DSP micro-component 4, and at the other end to the output of power supply 2. Micro-component clock 4 is connected at one end to the clock input of the DSP micro-component 4, and at the other end to the output of power supply 2. JTAG connector 4 is connected at one end to the JTAG pin of the DSP micro-component 4, and at the other end to the external JTAG adapter. Capacitor 128 is connected at one end to the DSP micro-component 4 high-speed signal 1, and at the other end to the DSP micro-component 4 high-speed signal 64. Capacitor 127 is connected at one end to the DSP micro-component 4 high-speed signal 2, and at the other end to the DSP micro-component 4 high-speed signal 63. The remaining 30 capacitors are connected sequentially.

4. The aged steel plate according to claim 3, characterized in that, The storage micro-component corresponds to the micro-component aging module; the internal structure of the micro-component aging modules is the same; the numbers of the stored micro-components, DSP chips, micro-component power chips, and micro-component clocks in the micro-component aging module increase sequentially according to the serial number of the micro-component aging module; In the micro-component aging module 1, one end of the power chip 1 is connected to the power input terminal of the DSP chip 1, and the other end is connected to the output terminal of the power supply 2. One end of the micro-component clock 1 is connected to the clock input terminal of the DSP chip 1, and the other end is connected to the output terminal of the power supply 2. One end of the DSP JTAG connector 1 is connected to the DSP chip 1, and the other end is connected to the output terminal of the power supply 2. One end of the storage micro-component 1 is connected to the DSP chip 1, and the other end is connected to the power supply 2. One end of the storage micro-component 2 is connected to the DSP chip 1, and the other end is connected to the power supply 2. In the micro-component aging module 4, one end of the power chip 4 is connected to the power input terminal of the DSP chip 4, and the other end is connected to the output terminal of the power supply 2. One end of the micro-component clock 4 is connected to the clock input terminal of the DSP chip 4, and the other end is connected to the output terminal of the power supply 2. One end of the DSP JTAG connector 4 is connected to the DSP chip 4, and the other end is connected to the output terminal of the power supply 2. One end of the storage micro-component 7 is connected to the DSP chip 4, and the other end is connected to the power supply 2. One end of the storage micro-component 8 is connected to the DSP chip 4, and the other end is connected to the power supply 2.

5. The aged steel plate according to claim 4, characterized in that, The resistors 1 to 2020 in the SiP circuit aging module and the resistors 2021 to 4040 in the micro-component aging module all have a resistance value of 4.7K and are packaged in a 0402 package.

6. The aged refining plate according to claim 5, characterized in that, The power chip model of SiP power chips 1 to SiP power chips 20 in the SiP circuit aging module, micro-component power chips 1 to micro-component power chips 20 in the micro-component aging module, and micro-component power chips 1 to micro-component power chips 4 in the micro-component aging module is LTM4644.

7. The aged steel plate according to claim 6, characterized in that, The clock model for the SiP clock in the SiP circuit aging module, the micro-component clocks 1 to 4 in the micro-component aging module, and the micro-assembly group clocks 1 to 4 in the micro-assembly group aging module is Au5411AQMT.

8. The aged steel plate according to claim 7, characterized in that, The connector model for SiP JTAG connectors 1 to 4 in the SiP circuit aging module, micro-component JTAG connectors 1 to 4 in the micro-component aging module, and DSP JTAG connectors 1 to 4 in the micro-assembly aging module is FT-EMU.

9. The aged refining plate according to claim 8, characterized in that, In the micro-component aging module, capacitors 1 to 128 all have a capacitance of 0.1uF, a voltage rating of 6.3V, and are packaged in a 0402 package.

10. The aged steel plate according to claim 9, characterized in that, The input voltage of power supply 1 and power supply 2 is 220V, and the output voltage is 12V.

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