Power supply detection circuit and apparatus

Abstract

The utility model discloses a kind of power supply detection circuit and equipment, it is related to electronic power technical field, including power supply detection circuit including power supply, comparator, load power supply circuit and switching circuit, power supply includes load output end and reference voltage end;Reference voltage end connects the reference end of comparator, load output end connects the comparison end of load power supply circuit and comparator, the output end of comparator connects the input end of switching circuit, the output end of switching circuit connects load power supply circuit;In the case where the voltage received at the comparison end of comparator is greater than the voltage received at reference end, switching circuit is cut off, to make load power supply circuit cut off.The utility model solves the technical problem that load is easily damaged due to power supply voltage overshoot.

Description

Technical Field

[0001] This utility model relates to the field of electronic power technology, and in particular to a power supply detection circuit and device. Background Technology

[0002] EOS (Electrical Over Stress) typically refers to the current or voltage stress that a device experiences exceeding its maximum permissible range. For example, EOS problems can easily occur the instant a load is powered on. Since loads usually contain large voltage regulator capacitors, the initial charging current of these capacitors is large at the moment of power-on. If the power supply cannot provide sufficient current in time or the current supply speed is insufficient, the voltage is momentarily pulled down. The power supply's subsequent full-power output may then overcompensate, causing the voltage overshoot to exceed the load's maximum permissible voltage, triggering an EOS problem and leading to irreversible damage or even destruction of the device or chip. Therefore, there is currently a problem of load damage caused by power supply voltage overshoot.

[0003] The above content is only used to help understand the technical solutions of the embodiments of this application, and does not represent an admission that the above content is prior art. Utility Model Content

[0004] The main purpose of this utility model is to provide a power detection circuit and device, which aims to solve the technical problem of easy damage to the load caused by power supply voltage overshoot.

[0005] To achieve the above objectives, this utility model proposes a power supply detection circuit, which includes a power supply, a comparator, a load power supply circuit, and a switching circuit. The power supply includes a load output terminal and a reference voltage terminal.

[0006] The reference voltage terminal is connected to the reference terminal of the comparator, the load output terminal is connected to the load power supply circuit and the comparison terminal of the comparator, the output terminal of the comparator is connected to the input terminal of the switching circuit, and the output terminal of the switching circuit is connected to the load power supply circuit.

[0007] When the voltage received at the comparator's comparison terminal is greater than the voltage received at the reference terminal, the switching circuit is turned off, thereby turning off the load power supply circuit.

[0008] In one embodiment, the switching circuit includes a latch unit and a first switching transistor. The output terminal of the comparator is connected to the input terminal of the latch unit, the output terminal of the latch unit is connected to the first terminal of the first switching transistor, and the second terminal of the first switching transistor is connected to the load power supply circuit.

[0009] In one embodiment, the latch unit includes a first NAND gate and a second NAND gate, the input terminal of the latch unit is the first input terminal of the first NAND gate, and the output terminal of the latch unit is the output terminal of the second NAND gate;

[0010] The first input terminal of the first NAND gate is connected to the output terminal of the comparator, the second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate, the output terminal of the first NAND gate is connected to the first input terminal of the second NAND gate, the second input terminal of the second NAND gate is connected to the reference voltage terminal, and the output terminal of the second NAND gate is connected to the first terminal of the first switching transistor.

[0011] In one embodiment, the power detection circuit further includes a prompting module, which is connected to the output of the first NAND gate.

[0012] In one embodiment, the prompting module is an indicator light and / or a buzzer;

[0013] If the voltage received at the comparator's comparison terminal is greater than the voltage received at the reference terminal, the indicator light illuminates and / or the buzzer sounds an alarm.

[0014] When the voltage received at the comparator's comparison terminal is equal to the voltage received at the reference terminal, the indicator light is off and / or the buzzer is muted.

[0015] In one embodiment, the power detection circuit further includes a reset module, which includes a reset switch and a reset resistor;

[0016] The first end of the reset resistor is grounded, the second end of the reset resistor is connected to the first end of the reset switch, and the second end of the reset switch is connected to the second input end of the second NAND gate.

[0017] In one embodiment, the load power supply circuit includes a second switching transistor, a first terminal of which is connected to a second terminal of a first switching transistor, the second terminal of which is connected to the load output terminal, and a third terminal of which is connected to the load.

[0018] In one embodiment, when the reset switch is pressed, the first switch in the switch circuit is turned on, and the second switch in the load power supply circuit is turned on.

[0019] In one embodiment, a pull-up resistor is provided between the output terminal and the reference terminal of the comparator.

[0020] To achieve the above objectives, the present invention also provides a power supply detection device, which includes the power supply detection circuit described above.

[0021] This invention provides a power supply detection circuit, comprising: a power supply, a comparator, a load power supply circuit, and a switching circuit. The power supply includes a load output terminal and a reference voltage terminal. The reference voltage terminal is connected to the reference terminal of the comparator. The load output terminal is connected to the load power supply circuit and the comparison terminal of the comparator. The output terminal of the comparator is connected to the input terminal of the switching circuit, and the output terminal of the switching circuit is connected to the load power supply circuit. This facilitates the detection of abnormalities at the load output terminal of the power supply, such as voltage overshoot. Specifically, if the voltage received at the comparison terminal of the comparator is greater than the voltage received at the reference terminal, the switching circuit is turned off, thereby cutting off the load power supply circuit. This enables the detection of voltage overshoot and, upon detection, the cutting off of the load power supply circuit prevents the overshoot voltage at the load output terminal from being input to the load, thus avoiding damage to the load due to voltage overshoot and solving the problem of load damage caused by power supply voltage overshoot. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the connection of a power detection circuit module provided in an embodiment of the present invention;

[0024] Figure 2 A schematic diagram of the circuit connection of the switching circuit, including a latch unit and a first switching transistor, in the power detection circuit provided by this utility model;

[0025] Figure 3 The circuit connection diagram of the latch unit in the power detection circuit provided by this utility model includes a first NAND gate and a second NAND gate;

[0026] Figure 4 A circuit connection diagram of the power detection circuit including the prompt module provided by this utility model;

[0027] Figure 5 A schematic diagram of the circuit connection of the indicator module, including the indicator light, in the power detection circuit provided by this utility model;

[0028] Figure 6 A circuit connection diagram showing the buzzer included in the prompting module of the power detection circuit provided by this utility model;

[0029] Figure 7 A circuit connection diagram of the power detection circuit provided by this utility model, including a reset module;

[0030] Figure 8 A schematic diagram of the circuit connection of the load power supply circuit in the power detection circuit provided by this utility model, including the second switching transistor;

[0031] Figure 9 A schematic diagram of the circuit connection in the power detection circuit provided by this utility model, in which a pull-up resistor is provided between the output terminal and the reference terminal of the comparator.

[0032] Figure 10 A schematic diagram of the output waveform of the load output terminal and the second switching transistor in the power detection circuit provided by this utility model.

[0033] The purpose, features, and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0034] Explanation of icon numbers:

[0035] 100. Power supply; Chancellor 1. Load output terminal; Chancellor 2. Reference voltage terminal; 200. Comparator; 300. Switching circuit; 400. Load power supply circuit; D1. Comparator terminal; D2. Reference terminal; 310. Latch unit; Q1. First switching transistor; U1. First NAND gate; U2. Second NAND gate; R1~R2. First resistor~Second resistor; 500. Indicator module; LED, indicator light; 510. Buzzer; 600. Reset module; SW. Reset switch; R3. Reset resistor; Q2. Second switching transistor; R4. Third resistor; R5. Pull-up resistor; 700. Load. Detailed Implementation

[0036] It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0037] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0038] It should be noted that the descriptions involving "first," "second," etc., in this utility model are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope claimed by this utility model.

[0039] Overcurrent stress (EOS), commonly known as "excessive electrical stress," refers to the current or voltage stress that a device experiences exceeding its maximum permissible range. In the integrated circuit field, EOS accounts for approximately 37% of device failures, primarily manifesting as sudden complete failure or potential damage. EOS has various causes, the most common being:

[0040] 1. Power supply interference or insufficient power supply stability. For example, a DC power supply may contain a strong AC component, which can easily cause EOS.

[0041] 2. When the power is suddenly switched on, the load needs to transition from a zero state (no current, no voltage) to a steady state (operating current, stable voltage). This step change contains a rich variety of frequency components. The LC loop formed by the parasitic inductance (L) and the equivalent load capacitance / filter capacitance (C) in the circuit will produce a resonant response to the step excitation. This resonant response manifests as the voltage initially surging before reaching the target value, then falling back down, and gradually stabilizing after multiple damped oscillations.

[0042] 3. Because loads typically contain large voltage regulator capacitors, the initial charging current of these capacitors is very large at the moment the load is powered on. If the power supply cannot immediately provide such a large current, or if the current supply speed cannot keep up with the capacitor's charging needs, the voltage will be momentarily pulled down. When the power supply "reacts" and begins to output at full power, it may overcompensate, leading to voltage overshoot.

[0043] When voltage overshoot exceeds the absolute voltage of a device or chip, it can trigger an EOS (Effective Voltage Occurrence), causing irreversible damage or even complete destruction of the device or chip. This is especially true in electronic device / module manufacturing scenarios where fixture testing is required during the testing phase. For example, clamping the fixture after power-on, or clamping the fixture before powering on. At the moment of power-on, the voltage is highly likely to fluctuate violently. When the voltage exceeds the absolute voltage of the chip, it may trigger an EOS. Although voltage overshoot can be avoided by replacing with a high-stability, high-dynamic-response power supply or optimizing the power system design, high-stability, high-dynamic-response power supplies are too expensive, and using such power supplies would greatly increase manufacturing costs. Alternatively, delaying power-on can also help avoid overshoot, but this cannot eliminate the risk of interference signals in the power supply, and there is also the risk of timing deviations. Another method is to reduce the number or capacitance of voltage regulator capacitors at the device end to avoid voltage overshoot, but this may not meet the requirements of the PDN (Power Delivery Network), leading to device or chip malfunctions.

[0044] Based on this, the present invention provides a power detection circuit. In one embodiment of the present invention, please refer to... Figure 1 The power supply 100 detection circuit includes a power supply 100, a comparator 200, a load power supply circuit 400, and a switching circuit 300. The power supply 100 includes a load output terminal Channe1 and a reference voltage terminal Channe2.

[0045] The reference voltage terminal Channe2 is connected to the reference terminal D2 of the comparator 200, the load output terminal Channe1 is connected to the load power supply circuit 400 and the comparison terminal D1 of the comparator 200, the output terminal of the comparator 200 is connected to the input terminal of the switching circuit 300, and the output terminal of the switching circuit 300 is connected to the load power supply circuit 400.

[0046] When the voltage received at the comparison terminal D1 of the comparator 200 is greater than the voltage received at the reference terminal D2, the switching circuit 300 is turned off, thereby turning off the load power supply circuit 400.

[0047] It should be noted that power supply 100 can be a DC power supply 100. The load output terminal Channe1 of power supply 100 is used to provide voltage and current to the load. The voltage of the reference voltage terminal Channe2 of power supply 100 remains unchanged. When power supply 100 is not abnormal (power supply 100 has no abnormal pulses, overshoot, etc.), the voltage output by the load output terminal Channe1 of power supply 100 and the voltage output by the reference voltage terminal Channe2 can be the same or different. The specific settings can be based on the actual situation. This embodiment does not make specific limitations on this. However, when power supply 100 is not abnormal, the voltages received by the comparison terminal D1 and the reference terminal D2 of comparator 200 need to be the same. For example, when the voltage of the initially configured reference voltage terminal Channe2 is different from the voltage output by the load output terminal Channe1, a voltage divider unit can be set at the reference voltage terminal Channe2 so that when power supply 100 has no abnormal pulses and no overshoot, the voltages input to the comparison terminal D1 and the reference terminal D2 of comparator 200 are the same, so that comparator 200 can detect the abnormal pulse output by the load output terminal Channe1 of power supply 100.

[0048] If the voltage received at the comparison terminal D1 is greater than the voltage received at the reference terminal D2, it indicates that the power supply 100 is overshooting. When the voltage received at the comparison terminal D1 is greater than the voltage received at the reference terminal D2, the output level of the comparator 200 will flip. For example, when the voltage at the comparison terminal D1 is equal to the voltage at the reference terminal D2, the output of the comparator 200 can be high, and when the voltage at the comparison terminal D1 is greater than the voltage at the reference terminal D2, the output of the comparator 200 can flip to low. The output of the comparator 200 can be directly connected to the input of the switching circuit 300.

[0049] In other embodiments, when the voltage at the comparison terminal D1 is equal to the voltage at the reference terminal D2, the output level of the comparator 200 can be low. When the voltage at the comparison terminal D1 is greater than the voltage at the reference terminal D2, the output of the comparator 200 can flip to a high level. When the voltage at the comparison terminal D1 is greater than the voltage at the reference terminal D2 and the output of the comparator 200 flips to a high level, the output of the comparator 200 is connected to the input of an inverter, and the output of the inverter is connected to the input of a switching circuit 300. This ensures that when the voltage received at the comparison terminal D1 of the comparator 200 is greater than the voltage received at the reference terminal D2, the switching circuit 300 receives a low level, allowing the switching circuit 300 to be turned off. This enables the load power supply circuit 400 to be interrupted in time, preventing damage to the load connected to the load power supply circuit 400 due to voltage overshoot.

[0050] The power supply 100 detection circuit includes: a power supply 100, a comparator 200, a load power supply circuit 400, and a switching circuit 300. The power supply 100 includes a load output terminal Channe1 and a reference voltage terminal Channe2. The reference voltage terminal Channe2 is connected to the reference terminal D2 of the comparator 200. The load output terminal Channe1 is connected to the load power supply circuit 400 and the comparison terminal D1 of the comparator 200. The output terminal of the comparator 200 is connected to the input terminal of the switching circuit 300, and the output terminal of the switching circuit 300 is connected to the load power supply circuit 400. This facilitates detection by the comparator 200. The test checks for abnormalities at the load output terminal Channe1 of power supply 100, such as voltage overshoot. Specifically, if the voltage received at the comparison terminal D1 of comparator 200 is greater than the voltage received at the reference terminal D2, the switching circuit 300 is turned off, thereby turning off the load power supply circuit 400. This enables the detection of voltage overshoot and, upon detection, the load power supply circuit 400 is turned off to prevent the overshoot voltage at the load output terminal Channe1 from being input to the load, thus avoiding damage to the load due to voltage overshoot. This solves the problem of easy load damage caused by voltage overshoot of power supply 100.

[0051] In one feasible embodiment, please refer to Figure 2 The switching circuit 300 includes a latch unit 310 and a first switching transistor Q1. The output terminal of the comparator 200 is connected to the input terminal of the latch unit 310, the output terminal of the latch unit 310 is connected to the first terminal of the first switching transistor Q1, and the second terminal of the first switching transistor Q1 is connected to the load power supply circuit 400.

[0052] It should be noted that the first switching transistor Q1 is an NMOS, and the output terminal of the latch unit 310 can be connected to the first terminal of the first switching transistor Q1. The first terminal of the first switching transistor Q1 is the gate, the second terminal of the first switching transistor Q1 is the drain, and the third terminal of the first switching transistor Q1 is the source. The latch unit 310 can be composed of two NAND gates.

[0053] Since the switching circuit 300 is equipped with a first switching transistor Q1, the switching circuit 300 can be controlled to turn on and / or turn off by turning on and / or turning off the first switching transistor Q1, so as to turn off the load switching circuit 300 in a timely manner.

[0054] In one feasible embodiment, please refer to Figure 3 The latch unit 310 includes a first NAND gate U1 and a second NAND gate U2. The input terminal of the latch unit 310 is the first input terminal of the first NAND gate U1, and the output terminal of the latch unit 310 is the output terminal of the second NAND gate U2.

[0055] The first input terminal of the first NAND gate U1 is connected to the output terminal of the comparator 200, the second input terminal of the first NAND gate U1 is connected to the output terminal of the second NAND gate U2, the output terminal of the first NAND gate U1 is connected to the first input terminal of the second NAND gate U2, the second input terminal of the second NAND gate U2 is connected to the reference voltage terminal Channe2, and the output terminal of the second NAND gate U2 is connected to the first terminal of the first switching transistor Q1.

[0056] It should be noted that the switching circuit 300 can also be connected to the reference voltage terminal Channe2. For example, the second input terminal of the second NAND gate U2 in the switching circuit 300 can be connected to the reference voltage terminal Channe2. A first resistor R1 can be set between the reference voltage terminal Channe2 and the second input terminal of the second NAND gate U2. This allows the reference voltage terminal Channe2 and the first resistor R1 to provide a high level to the second input terminal of the second NAND gate U2. The value of the first resistor can be set based on actual conditions; this embodiment does not impose specific limitations on this. The logic of both the first NAND gate U1 and the second NAND gate U2 is: 0 for input, 1 for output; all inputs are 1 for output, 0 indicates a low level, and 1 indicates a high level.

[0057] When the voltage received at the comparison terminal D1 of the comparator 200 is greater than the voltage received at the reference terminal D2, the first input terminal of the first NAND gate U1 is low, the output terminal of the first NAND gate U1 is high, the output terminal of the second NAND gate U2 is low, the second input terminal of the first NAND gate U1 is low, the first input terminal of the second NAND gate U2 is low, and the input of the second input terminal of the second NAND gate U2 is always high. When the second NAND gate U2 outputs a low level, the first switch Q1 is off; when the second NAND gate U2 outputs a high level, the first switch Q1 is on.

[0058] The first NAND gate U1 and the second NAND gate U2 together constitute the latch unit 310. When a high level is input to the first input terminal of the first NAND gate U1, the output of the first NAND gate U1 is locked. Even if a low level is input to the first input terminal of the first NAND gate U1, the output of the first NAND gate U1 will not change because the output terminal of the first NAND gate U1 is connected to the first input terminal of the second NAND gate U2. A NAND gate will output 1 if its input is 0 and will output 0 if its input is all 1. This ensures that the output of the first NAND gate U1 is always 1 and the output of the second NAND gate U2 is always 0. This can protect the load and prevent it from being damaged due to voltage overshoot.

[0059] In one feasible embodiment, please refer to Figure 4 The power supply 100 detection circuit also includes a prompting module 500, which is connected to the output terminal of the first NAND gate U1.

[0060] It should be noted that the prompt module 500 can be used to indicate the risk of overshoot in the power supply 100. The input terminal of the prompt module 500 is connected to the output terminal of the first NAND gate U1, and the output terminal of the prompt module 500 can be grounded. When the voltage received at the comparison terminal D1 of the comparator 200 is greater than the voltage received at the reference terminal D2, the output terminal of the first NAND gate U1 is at a high level, and the prompt module 500 can output an overshoot warning. When the output terminal of the first NAND gate U1 is at a low level, the prompt module 500 will not output a warning.

[0061] In one feasible embodiment, please refer to Figure 5 and Figure 6 The prompting module 500 is an indicator LED and / or a buzzer 510;

[0062] If the voltage received at the comparison terminal D1 of the comparator 200 is greater than the voltage received at the reference terminal D2, the indicator LED will light up and / or the buzzer 510 will sound an alarm.

[0063] When the voltage received at the comparison terminal D1 of the comparator 200 is equal to the voltage received at the reference terminal D2, the indicator LED is off and / or the buzzer 510 is in a silent state.

[0064] It should be noted that the prompt module 500 can be an indicator LED and / or a buzzer 510, for example, refer to Figure 5 , Figure 5 The first terminal of the indicator LED can be connected to the output terminal of the first NAND gate U1. A second resistor R2 can be provided between the first terminal of the indicator LED and the output terminal of the first NAND gate U1, for example, referring to... Figure 6 , Figure 6 The first terminal of the buzzer 510 can be connected to the output terminal of the first NAND gate U1, and the second terminal of the buzzer 510 can be grounded.

[0065] When the voltage received at the comparison terminal D1 of the comparator 200 is greater than the voltage received at the reference terminal D2, the output of the first NAND gate U1 is high, thus driving the indicator LED to light up and / or the buzzer 510 to sound an alarm. When the voltage received at the comparison terminal D1 of the comparator 200 is equal to the voltage received at the reference terminal D2, the output of the first NAND gate U1 is low, thus not driving the indicator LED to light up, and the buzzer 510 will also be in a silent state. When the prompt module 500 includes an indicator LED and a buzzer 510, the first terminal of both the indicator LED and the first terminal of the buzzer 510 are connected to the output of the first NAND gate U1. The indicator LED and the buzzer 510 can be connected in parallel, as not shown in the figure.

[0066] In one feasible embodiment, please refer to Figure 7 The power supply 100 detection circuit also includes a reset module 600, which includes a reset switch SW and a reset resistor R3.

[0067] The first end of the reset resistor R3 is grounded, the second end of the reset resistor R3 is connected to the first end of the reset switch SW, and the second end of the reset switch SW is connected to the second input end of the second NAND gate U2.

[0068] It should be noted that the reset switch SW can be a push-button switch. When the reset switch SW is pressed, the first input terminal of the second NAND gate U2 receives a low level, which causes the output terminal of the second NAND gate U2 to output a high level, so that the first switch Q1 is turned on.

[0069] After the first switch Q1 is turned off, if it is necessary to restore power supply to the load power supply circuit 400, the reset switch SW needs to be used to turn on the first switch Q1, thereby turning on the load power supply circuit 400. This allows the load power supply circuit 400 to supply power to the load, enabling a retest of the power supply 100 for any abnormal overshoot or other issues. If the reset switch SW remains open after the first switch Q1 is turned off, the first switch Q1 will remain off, and the load power supply circuit 400 will also remain off, thus protecting the load.

[0070] Therefore, after the reset switch SW is reset, or before the power supply 100 outputs an abnormal pulse, if the voltage received by the comparison terminal D1 of the comparator 200 is less than or equal to the voltage received by the reference terminal D2, the first input terminal of the first NAND gate U1 is at a high level, the output terminal of the first NAND gate U1 is at a low level, the first input terminal of the second NAND gate U2 is at a low level, the output terminal of the second NAND gate U2 is at a high level, and the first switch Q1 is turned on.

[0071] In one feasible embodiment, please refer to Figure 8 The load power supply circuit 400 includes a second switch Q2, the first end of the second switch Q2 is connected to the second end of the first switch Q1, the second end of the second switch Q2 is connected to the load output terminal Channe1, and the third end of the second switch Q2 is connected to the load 700.

[0072] It should be noted that the load power supply circuit 400 includes a second switching transistor Q2. When the second switching transistor Q2 is off, the load power supply circuit 400 is off; when the second switching transistor Q2 is on, the load power supply circuit 400 is on. When the first switching transistor Q1 is off, the second switching transistor Q2 will also be off; when the first switching transistor Q1 is on, the second switching transistor Q2 will be on.

[0073] The second switch Q2 is a PMOS transistor. The first terminal of Q2 is the gate, the second terminal is the source, and the third terminal is the drain. For example, refer to... Figure 7 A third resistor R4 can also be placed between the drain of the first switching transistor Q1 and the source of the second switching transistor Q2.

[0074] In this embodiment, by setting a second switch Q2, the load power supply circuit 400 can be controlled to be turned on or off, thereby facilitating the protection of the load 700 and preventing damage to the load 700 due to overshoot of the power supply 100.

[0075] In one feasible embodiment, when the reset switch SW is pressed, the first switch Q1 in the switch circuit 300 is turned on, and the second switch Q2 in the load power supply circuit 400 is turned on.

[0076] It should be noted that when the reset switch SW is pressed, the second input terminal of the second NAND gate U2 in the switching circuit 300 is low, and the output of the second NAND gate U2 is high, which in turn turns on the first switch Q1. The first switch Q1 turns on, which in turn turns on the second switch Q2. If there is still a voltage overshoot after the reset switch SW is pressed, the first switch Q1 will turn off, which in turn turns on the second switch Q2, so as to protect the load connected to the load power supply circuit 400.

[0077] In one feasible embodiment, please refer to Figure 9 A pull-up resistor R5 is provided between the output terminal of the comparator 200 and the reference terminal D2.

[0078] It should be noted that the reference terminal D2 of comparator 200 is the positive terminal, and the comparison terminal D1 is the negative terminal. A pull-up resistor is set between the output terminal of comparator 200 and the reference terminal D2 to pull the output terminal of comparator 200 high by default, preventing the output of comparator 200 from being unstable. The default condition means that there are no abnormal pulses or overshoots in power supply 100. If there is an abnormal pulse at the load output terminal Chane1 of power supply 100, the output terminal of comparator 200 will flip to a low level. This embodiment uses a pull-up resistor to ensure the output stability of comparator 200 by default, thereby improving the accuracy of the power supply 100 detection circuit.

[0079] To better understand this embodiment, you can also refer to Figure 10 , Figure 10The diagram shows the waveforms of the output at the load output terminal Channe1 and the output of the second switch Q2. The voltage at the reference terminal D2 of comparator 200 can be configured to 3.3V. The maximum overshoot voltage of power supply 100 is 6.6V. When power supply 100 overshoots, the output at the load output terminal Channe1 will output 6.6V, which may damage the load. Therefore, when the load output terminal Channe1 outputs 6.6V, the output of the second switch Q2 is 0, meaning the second switch Q2 is cut off to protect the load. When the second switch Q2 is cut off, the indicator LED lights up to visually indicate that power supply 100 is malfunctioning and there is a risk of damage to the load. After checking and troubleshooting, the reset switch SW should be pressed to turn on the first switch Q1 and the second switch Q2. For example, the time period t1 to t2 can be the stage for developers to check and troubleshoot. For example, the fault may be a mismatch between power supply 100 and the load, so power supply 100 is at risk of overshoot. After troubleshooting, the reset switch SW can be pressed. For example, t2 can be the moment the reset switch SW is pressed. After troubleshooting and the reset switch SW is pressed, the output of the load terminal Channe1 can output a normal voltage of 3.3V, and the second switching transistor Q2 can also output a normal voltage of 3.3V, ensuring that the load can operate normally and preventing load damage due to overshoot of power supply 100. After pressing the reset switch SW, the indicator LED will also turn off, and power supply 100 will output normally until an abnormal voltage higher than 3.3V reappears, at which point power supply 100 will be shut off again. This achieves load protection, reduces the probability of load damage, and lowers testing costs.

[0080] This utility model also provides a power supply detection device, which includes the power supply detection circuit described above.

[0081] The above are merely preferred embodiments of this utility model and do not limit the patent scope of this utility model. Any equivalent structural or procedural transformations made based on the description and drawings of this utility model, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. A power supply detection circuit, characterized in that, The power supply detection circuit includes a power supply, a comparator, a load power supply circuit, and a switching circuit. The power supply includes a load output terminal and a reference voltage terminal. The reference voltage terminal is connected to the reference terminal of the comparator, the load output terminal is connected to the load power supply circuit and the comparison terminal of the comparator, the output terminal of the comparator is connected to the input terminal of the switching circuit, and the output terminal of the switching circuit is connected to the load power supply circuit. When the voltage received at the comparator's comparison terminal is greater than the voltage received at the reference terminal, the switching circuit is turned off, thereby turning off the load power supply circuit.

2. The power detection circuit as described in claim 1, characterized in that, The switching circuit includes a latch unit and a first switching transistor. The output terminal of the comparator is connected to the input terminal of the latch unit, the output terminal of the latch unit is connected to the first terminal of the first switching transistor, and the second terminal of the first switching transistor is connected to the load power supply circuit.

3. The power detection circuit as described in claim 2, characterized in that, The latch unit includes a first NAND gate and a second NAND gate. The input terminal of the latch unit is the first input terminal of the first NAND gate, and the output terminal of the latch unit is the output terminal of the second NAND gate. The first input terminal of the first NAND gate is connected to the output terminal of the comparator, the second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate, the output terminal of the first NAND gate is connected to the first input terminal of the second NAND gate, the second input terminal of the second NAND gate is connected to the reference voltage terminal, and the output terminal of the second NAND gate is connected to the first terminal of the first switching transistor.

4. The power detection circuit as described in claim 3, characterized in that, The power detection circuit also includes a prompting module, which is connected to the output of the first NAND gate.

5. The power detection circuit as described in claim 4, characterized in that, The prompting module is an indicator light and / or a buzzer; If the voltage received at the comparator's comparison terminal is greater than the voltage received at the reference terminal, the indicator light illuminates and / or the buzzer sounds an alarm. When the voltage received at the comparator's comparison terminal is equal to the voltage received at the reference terminal, the indicator light is off and / or the buzzer is muted.

6. The power detection circuit as described in claim 3, characterized in that, The power detection circuit further includes a reset module, which includes a reset switch and a reset resistor. The first end of the reset resistor is grounded, the second end of the reset resistor is connected to the first end of the reset switch, and the second end of the reset switch is connected to the second input end of the second NAND gate.

7. The power detection circuit as described in claim 2, characterized in that, The load power supply circuit includes a second switching transistor, the first end of which is connected to the second end of the first switching transistor, the second end of which is connected to the load output terminal, and the third end of which is connected to the load.

8. The power detection circuit as described in any one of claims 1-7, characterized in that, When the reset switch is pressed, the first switch in the switching circuit is turned on, and the second switch in the load power supply circuit is turned on.

9. The power detection circuit as described in claim 1, characterized in that, A pull-up resistor is provided between the output terminal and the reference terminal of the comparator.

10. A power supply detection device, characterized in that, The power detection device includes the power detection circuit as described in any one of claims 1-9.

Images