A ceramic heat sink and CPO silicon light engine

Abstract

The utility model relates to a kind of ceramic heat sink, first gold plating layer and second gold plating layer are distributed side by side along its length direction on the upper surface of substrate at predetermined interval, the upper surface of first gold plating layer is equipped with the solder layer of width smaller than DFB chip width along its length direction in partial area, the two sides of solder layer along its length direction are wavy curved surface, DFB chip is soldered on substrate by solder layer eutectic welding.A kind of CPO silicon light engine, comprising: the above-mentioned ceramic heat sink.Affirmative effect is: because the width of solder layer is smaller than the width of DFB chip, and the two sides of solder layer along its length direction are wavy curved surface, so after eutectic, even if solder melts, when DFB chip middle part solder melting state is extruded, the two sides of solder layer along its length direction appearance is still wavy curved surface, so that DFB chip side wall solder accumulation height is low, and DFB chip short-circuit proportion is reduced.

Description

Technical Field

[0001] This utility model relates to the field of optical engine technology, specifically to a ceramic heat sink and a CPO silicon photonic engine. Background Technology

[0002] The ceramic heat sinks used in CPO silicon photonics engines generally require CW DFB optical power greater than 200mW, and some even require greater than 500mW. Currently, these DFB chips generally use the method of lengthening the chip to achieve high power. The reason is that if the cavity length is too short, the optical density will be too high, which will easily lead to chip burnout. The length of DFB chips is generally ≥2mm. For example, if the width of the DFB chip is 0.25mm, the length is 2mm, and the height is 0.1mm, then the substrate design is 2.5mm. If the substrate is too long, it will lead to a larger package size. The substrate material is generally ceramic. On the upper surface of the substrate, there are a first gold plating layer and a second gold plating layer arranged side by side at a predetermined interval along its length. The first gold plating layer and the second gold plating layer have bonding areas at the ends of their upper surfaces. Gold wires are bonded to the bonding areas of the first gold plating layer and the second gold plating layer. A solder layer is provided in some areas along the length of the upper surface of the first gold plating layer. The solder layer is generally a gold-tin solder layer. The current design of the solder layer is rectangular. Figure 1 As shown, the width of the solder layer is larger than the width of the DFB chip. The DFB chip is eutectic bonded to the substrate via the solder layer. The DFB chip is typically centered relative to the solder layer. After eutectic bonding, the solder melts and flows onto the first gold plating layer, easily contaminating the bonding area. Furthermore, because the DFB chip is so long, when the molten solder in the middle part of the DFB chip is compressed, solder buildup heights exceeding 0.1mm can easily occur on the sidewalls of the DFB chip, leading to short circuits between the top and bottom surfaces of the DFB chip. Figure 2 As shown. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide a ceramic heat sink and a CPO silicon photonics engine to overcome the shortcomings of the prior art.

[0004] The technical solution of this utility model to solve the above-mentioned technical problems is as follows: A ceramic heat sink includes a substrate and a DFB chip. The upper surface of the substrate is provided with a first gold plating layer and a second gold plating layer arranged side by side at a predetermined interval along its length direction. A solder layer with a width smaller than the width of the DFB chip is provided in a certain area along its length direction on the upper surface of the first gold plating layer. The two sides of the solder layer along its length direction are wavy curved surfaces. The DFB chip is eutectic soldered to the substrate through the solder layer.

[0005] The beneficial effects of this invention are as follows: Since the width of the solder layer is smaller than the width of the DFB chip, and the two sides of the solder layer along its length are wavy curved surfaces, even if the solder melts after eutectic bonding, when the solder in the middle part of the DFB chip is squeezed in a molten state, the appearance of the two sides of the solder layer along its length is still a wavy curved surface, thereby making the solder accumulation height on the side wall of the DFB chip low and reducing the short circuit ratio of the DFB chip.

[0006] Based on the above technical solution, the present invention can be further improved as follows.

[0007] Furthermore, the width of the solder layer is 40μm to 60μm smaller than the width of the DFB chip.

[0008] Furthermore, the wave length period on the curve is equal to the width of the DFB chip, and the wave depression depth on the curve is 40μm~60μm.

[0009] Furthermore, a solder resist layer that does not stick to the solder and blocks the solder is provided on the upper surface of the first gold plating layer between the bonding area and the solder layer.

[0010] The further beneficial effect of adopting the above is that the solder resist layer acts like a barrier, which can prevent solder from flowing to the bonding area of ​​the first gold plating layer, so as to avoid contaminating the bonding area of ​​the first gold plating layer.

[0011] Furthermore, the solder resist layer is an insulating oxide layer, and the thickness of the solder resist layer is greater than 1μm.

[0012] Furthermore, gold wires are bonded in the bonding region on the first gold plating layer, and gold wires are bonded in the bonding region on the second gold plating layer.

[0013] Furthermore, the solder layer is a gold-tin solder layer.

[0014] Furthermore, the substrate is made of ceramic.

[0015] Furthermore, the optical power of the DFB chip is greater than 200mW or 500mW, and the length of the DFB chip is greater than or equal to 2mm.

[0016] Based on the above technical solution, this utility model also provides a CPO silicon photonics engine, including: the above-mentioned ceramic heat sink.

[0017] The further beneficial effect of adopting the above method is that it can effectively ensure the yield rate. Attached Figure Description

[0018] Figure 1 This is a structural diagram of a non-eutectic DFB chip on a ceramic heat sink in the prior art; Figure 2 This is a structural diagram of a eutectic DFB chip on a ceramic heat sink in the prior art; Figure 3 This is a structural diagram of the non-eutectic DFB chip on the ceramic heat sink in this utility model; Figure 4 This is a structural diagram of the ceramic heat sink after the DFB chip is placed on the solder layer. Figure 5 This is a structural diagram of the ceramic heat sink in this utility model.

[0019] The attached diagram lists the components represented by each number as follows: 1. Substrate; 2. First gold plating layer; 3. Second gold plating layer; 4. Solder layer; 5. DFB chip; 6. Solder resist layer; 7. Gold wire. Detailed Implementation

[0020] The principles and features of this utility model are described below with reference to the accompanying drawings. The examples given are only for explaining this utility model and are not intended to limit the scope of this utility model.

[0021] Example 1 like Figure 3 , Figure 4 , Figure 5 As shown, a ceramic heat sink includes: The substrate 1 and the DFB chip 5 are provided. A first gold plating layer 2 and a second gold plating layer 3 are provided on the upper surface of the substrate 1. The first gold plating layer 2 and the second gold plating layer 3 are arranged side-by-side at a predetermined interval along the length direction of the substrate 1, i.e., the length direction of the first gold plating layer 2 is in the same direction as the length direction of the substrate 1, and the length direction of the second gold plating layer 3 is in the same direction as the length direction of the substrate 1. A solder layer 4 with a width smaller than the width of the DFB chip 5 is provided in a portion of the upper surface of the first gold plating layer 2 along its length direction. The length direction of the solder layer 4 is in the same direction as the length direction of the first gold plating layer 2. The two sides of the solder layer 4 along its length direction are wavy curved surfaces. The DFB chip 5 is eutectic bonded to the substrate 1 via the solder layer 4. DFB chip 5 is typically centered relative to solder layer 4. Since the width of solder layer 4 is smaller than the width of DFB chip 5, and the two sides of solder layer 4 along its length are wavy curved surfaces, even after eutectic bonding, when the solder melts and is squeezed in the middle part of DFB chip 5, the appearance of the two sides of solder layer 4 along its length is still wavy curved surfaces. This results in a low solder buildup height on the sidewalls of DFB chip 5 and a reduced short-circuit ratio in DFB chip 5.

[0022] Example 2 like Figure 3 , Figure 4 , Figure 5 As shown, this embodiment is a further improvement on embodiment 1, as detailed below: The width of solder layer 4 is 40μm to 60μm smaller than the width of DFB chip 5. The wave length period on the curve surface is equal to the width of DFB chip 5, and the wave depression depth on the curve surface is 40μm to 60μm.

[0023] Example 3 like Figure 3 , Figure 4 , Figure 5 As shown, this embodiment is a further improvement on embodiment 1 or 2, specifically as follows: On the upper surface of the first gold plating layer 2, a solder resist layer 6 is provided between the bonding area and the solder layer 4. The solder resist layer 6 does not stick to the solder and blocks the solder. The function of the solder resist layer 6 is similar to an isolation wall, which can prevent the solder from flowing to the bonding area of ​​the first gold plating layer 2, so as to avoid contaminating the bonding area of ​​the first gold plating layer 2.

[0024] Furthermore, the solder resist layer 6 is preferably an insulating oxide layer, and the thickness of the solder resist layer 6 is greater than 1 μm.

[0025] Example 4 like Figure 5 As shown, this embodiment is a further improvement on embodiment 1, 2, or 3, as detailed below: Gold wires 7 are bonded in the bonding area on the first gold plating layer 2, and gold wires 7 are bonded in the bonding area on the second gold plating layer 3.

[0026] Solder layer 4 is preferably a gold-tin solder layer, which is consistent with the existing technology, and the substrate 1 is preferably made of ceramic, which is consistent with the existing technology.

[0027] Example 5 like Figure 4 , Figure 5 As shown, this embodiment is a further improvement on embodiment 1, 2, 3, or 4, as detailed below: The optical power of DFB chip 5 is greater than 200mW, or greater than 500mW. The length of DFB chip 5 is greater than or equal to 2mm. For example, the length of DFB chip 5 is 2mm and the length of substrate 1 is 2.5mm. If substrate 1 is too long, it will result in a larger package size. The width of DFB chip 5 is 0.25mm, the length is 2mm, and the height is 0.1mm.

[0028] Example 6 A CPO silicon photonics engine includes a ceramic heat sink as described in any of Examples 1 to 5.

[0029] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A ceramic heat sink, characterized in that, include: The substrate (1) and the DFB chip (5) are provided with a first gold plating layer (2) and a second gold plating layer (3) arranged side by side at a predetermined interval along the length direction on the upper surface of the substrate (1). A solder layer (4) with a width smaller than that of the DFB chip (5) is provided in a certain area along the length direction on the upper surface of the first gold plating layer (2). The two sides of the solder layer (4) along the length direction are wavy curved surfaces. The DFB chip (5) is eutectic welded to the substrate (1) through the solder layer (4).

2. The ceramic heat sink according to claim 1, characterized in that, The width of the solder layer (4) is 40 μm to 60 μm smaller than the width of the DFB chip (5).

3. A ceramic heat sink according to claim 1, characterized in that, The wave length period on the curve surface is equal to the width of the DFB chip (5), and the wave depression depth on the curve surface is 40μm~60μm.

4. A ceramic heat sink according to claim 1, characterized in that, On the upper surface of the first gold plating layer (2), a solder resist layer (6) is provided between the bonding area and the solder layer (4) to prevent the solder from sticking and to block the solder.

5. A ceramic heat sink according to claim 4, characterized in that, The solder resist layer (6) is an insulating oxide layer, and the thickness of the solder resist layer (6) is greater than 1 μm.

6. A ceramic heat sink according to claim 1, characterized in that, Gold wires (7) are bonded in the bonding region on the first gold plating layer (2), and gold wires (7) are bonded in the bonding region on the second gold plating layer (3).

7. A ceramic heat sink according to claim 1, characterized in that, The solder layer (4) is a gold-tin solder layer.

8. A ceramic heat sink according to claim 1, characterized in that, The substrate (1) is made of ceramic.

9. A ceramic heat sink according to claim 1, characterized in that, The optical power of the DFB chip (5) is greater than 200mW or 500mW, and the length of the DFB chip (5) is greater than or equal to 2mm.

10. A CPO silicon photonics engine, characterized in that, include: The ceramic heat sink as described in any one of claims 1 to 9.

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