Capacitive isolated simulation device
Patent Information
- Application Number
- CN202521993222.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-16
- Publication Date
- 2026-09-04
- Estimated Expiration
- 2035-09-16
AI Technical Summary
[0003]1安全隐患：目标板与调试设备(计算机、仿真器)间可能形成地环路或存在电势差
[0015]采用了上述技术方案后，本实用新型的有益效果是：1.通过设置数字隔离芯片，并将隔离板上的目标板侧与仿真器侧完全电气隔离，实现调试设备(仿真器侧)与高压目标板侧之间的电气隔离(如隔离电压1000V DC或更高)，有效防止高压、浪涌、地环路电流对人员和昂贵调试设备的危害，这使得被测板与仿真器或者电脑之间不会形成“地环路”，从而避免了引入噪声和干扰导致调试信号不稳定、程序下载失败甚至目标MCU运行异常的问题发生，通过全差分隔离电容技术，将仿真器侧与目标板侧隔离，即在仿真器侧和目标板侧之间建立一个高阻抗屏障，阻止电流直接通过，但允许信号(数据、时钟)通过，同时抑制共模噪声，极大地增强了在嘈杂的电力电子环境中的可靠性，同时，差分信号的辐射也更小。
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Figure CN224720468U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of simulation device technology, and specifically relates to a capacitive isolation simulation device. Background Technology
[0002] When developing embedded systems using Renesas MCUs, emulators E1 or E2 are often used to connect to the target board for debugging. However, when debugging systems such as motor drives, digital power supplies, and inverters that are powered by high voltage (e.g., AC 220V or DC 310V) and share a common ground with the mains power, the following significant risks and problems exist:
[0003] 1. Safety Hazard: A ground loop or potential difference may exist between the target board and the debugging equipment (computer, emulator). If a power device "explodes" during debugging (such as MOSFET breakdown), high voltage may surge into the USB port, easily burning out the computer's USB controller and emulator, and even endangering the personal safety of debugging personnel.
[0004] 2. Signal interference: High-power switching devices (such as MOSFETs and IGBTs) generate strong electromagnetic noise when they are working, which leads to the deterioration of the quality of SWD / JTAG debugging signals (especially high-speed data streams such as SWO and RTT), communication interruption, simulator crash, and affects debugging efficiency.
[0005] Existing solutions are inadequate: Although isolation solutions exist (such as high-speed optocouplers), they often support incomplete signals, have low speeds (prone to disconnection), and suffer from device aging and degradation issues, resulting in a poor user experience. The isolation boards provided by the original manufacturers are expensive, inconvenient to purchase, and have long delivery times. Therefore, we hope to design a ground-penetrating radar system with a novel structure to solve this problem. Utility Model Content
[0006] In view of the shortcomings of the existing technology, the purpose of this utility model is to provide a capacitive isolation simulation device to solve the problems mentioned in the background technology.
[0007] This utility model is achieved through the following technical solution: a capacitive isolation simulation device, comprising: a housing, wherein a PCB board is installed inside the housing for setting an isolation plate, and an isolation plate for setting a target board side and a simulator side is provided on the PCB board, wherein the isolation plate includes a target board side and a simulator side;
[0008] The target board side is located on one side of the PCB board. A buffer circuit is provided on the target board side to increase robustness and accommodate multiple reset signal sources. The emulator side is located on the other side of the PCB board, and the target board side and emulator side are completely electrically isolated. A digital isolator chip for capacitive isolation is mounted on the isolation board. The digital isolator chip internally encapsulates an isolation capacitor. The digital isolator chip is connected to the target board side and the emulator side via pins. In practical applications, a high-performance digital isolator chip similar to CA-IS3760 can be used. Compared to traditional optocouplers, it has advantages such as anti-interference, high speed, low power consumption, and long lifespan.
[0009] In a preferred embodiment, a plastic stud is provided at each of the four corners of the top of the housing, which penetrates the PCB board and is fixed by a plastic nut. A bottom cover is fixed to the bottom of the housing by the stud and the plastic nut. A USB interface is provided on the front of the housing for electrical connection with an external calculator.
[0010] In a preferred embodiment, the isolation capacitor includes an upper plate and a lower plate. Both the upper plate and the lower plate are connected to the internal circuit of the chip through interconnect pillars to achieve signal transmission. A dielectric layer is disposed between the upper plate and the lower plate to form an electrical isolation barrier. The dielectric layer is a silicon dioxide filling layer.
[0011] As a preferred embodiment, both sides of the isolation board need to be powered independently. The emulator side draws power from the 8-pin of the 14-pin interface or the 1-pin of the 20-pin interface, while the target board side draws power from the target board's debug interface Pin 8 (VCC) or is powered by an external independent power supply (selected via a reserved interface or jumper). In actual use, the isolation board adopts a board-to-board structure. The isolation board is physically divided into the emulator side and the target board side, and the two sides are completely electrically isolated. The board usually contains a 14-pin standard interface, and the emulator side is compatible with the E2 20-pin interface.
[0012] In a preferred embodiment, the digital isolation chip provides unidirectional or bidirectional isolation for the LPDCLK, LPDO, LPDI, LPDCLK0, and RESET signals, wherein LPDCLK is only provided with bidirectional signal isolation.
[0013] As a preferred embodiment, the PCB board also integrates LED indicator lights to display the power supply of the simulator side, the power supply of the target board side, and the RESET status for easy observation of the debugging status.
[0014] As a preferred embodiment, the target board side is provided with an interface board, which is a type of anti-reverse insertion horn terminal. It uses an asymmetrical pin definition to prevent reverse insertion from causing a direct short circuit between VCC and GND, thereby damaging the isolation.
[0015] After adopting the above technical solution, the beneficial effects of this utility model are as follows: 1. By setting a digital isolation chip and completely electrically isolating the target board side and the simulator side on the isolation board, electrical isolation between the debugging equipment (simulator side) and the high-voltage target board side is achieved (such as isolation voltage of 1000V DC or higher), effectively preventing the harm of high voltage, surge, and ground loop current to personnel and expensive debugging equipment. This prevents the formation of a "ground loop" between the board under test and the simulator or computer, thereby avoiding the introduction of noise and interference that leads to unstable debugging signals, program download failure, or even abnormal operation of the target MCU. Through the fully differential isolation capacitor technology, the simulator side and the target board side are isolated, that is, a high impedance barrier is established between the simulator side and the target board side to prevent current from passing directly, but to allow signals (data, clock) to pass through, while suppressing common-mode noise, greatly enhancing reliability in noisy power electronic environments. At the same time, the radiation of differential signals is also smaller.
[0016] 2. By setting up the target board side interface, the unique target board side interface pin definition design (asymmetrical arrangement) can effectively prevent the target board MCU from burning out due to reverse connection of the interface. This gives the entire device a reverse connection protection function, making it plug-and-play and simplifying the debugging process. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of the overall structure of the isolation plate of the capacitive isolation simulation device of this utility model.
[0019] Figure 2 This is a schematic diagram of the core components and signal flow of the isolation board of the capacitive isolation simulation device of this utility model.
[0020] Figure 3 This is a schematic diagram of the principle circuit of the capacitive isolation simulation device of this utility model.
[0021] Figure 4 This is a schematic diagram of the isolation plate structure of the capacitive isolation simulation device of this utility model.
[0022] In the diagram, 100 is the outer casing, 110 is the USB interface, 120 is the isolation board, 130 is the target board side, 140 is the emulator side, 150 is the digital isolation chip, and 160 is the isolation board. Detailed Implementation
[0023] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0024] As the first embodiment of this utility model:
[0025] Please see Figures 1 to 4 A capacitive isolation simulation device includes: a housing 100, a PCB board 120 installed inside the housing 100 for setting an isolation plate 160, and an isolation plate 160 for setting a target board side 130 and a simulator side 140 on the PCB board 120. The isolation plate 160 includes a target board side 130 and a simulator side 140.
[0026] The target board side 130 is located on one side of the PCB board 120. The target board side 130 is equipped with a buffer circuit to increase robustness and accommodate multiple sources of the reset signal. The emulator side 140 is located on the other side of the PCB board 120, and the target board side 130 and the emulator side 140 are completely electrically isolated. A digital isolator chip for capacitive isolation is mounted on the isolation board 160. The digital isolator chip 150 has an internally packaged isolation capacitor. The digital isolator chip 150 is connected to the target board side 130 and the emulator side 140 through pins. In actual use, the digital isolator chip 150 can be a high-performance digital isolator chip like CA-IS3760. Compared with traditional optocouplers, it has the advantages of anti-interference, high speed, low power consumption, and long life.
[0027] A plastic stud is provided at each of the four corners of the top of the outer casing 100, which passes through the PCB board 120 and is fixed by a plastic nut. The bottom cover of the outer casing 100 is fixed by the stud and the plastic nut. A USB interface 110 is provided on the front of the outer casing 100 for electrical connection with an external calculator.
[0028] An isolation capacitor includes an upper plate and a lower plate. Both the upper and lower plates are connected to the internal circuitry of the chip via interconnect pillars to achieve signal transmission. A dielectric layer is provided between the upper and lower plates to form an electrical isolation barrier. The dielectric layer is a silicon dioxide filling layer.
[0029] Both sides of the isolation board 160 require independent power supply. The emulator side 140 draws power from the 8-pin of the 14-pin interface or the 1-pin of the 20-pin interface, while the target board side 130 draws power from the target board's debug interface pin 8 (VCC) or is powered by an external independent power supply (selected via a reserved interface or jumper). In actual use, the isolation board 160 adopts a board-to-board structure. The isolation board 160 is physically divided into the emulator side 140 and the target board side 130, with complete electrical isolation between the two sides. The board usually contains a 14-pin standard interface, and the emulator side 140 is compatible with the E2's 20-pin interface.
[0030] The digital isolation chip 150 provides unidirectional or bidirectional isolation for the LPDCLK, LPDO, LPDI, LPDCLK0, and RESET signals, with LPDCLK only providing bidirectional signal isolation.
[0031] The PCB board 120 also integrates LED indicators to display the power supply of the simulator side 140, the power supply of the target board side 130, and the RESET status for easy observation of the debugging status.
[0032] Specifically, by setting up a digital isolation chip 150, the target board side 130 on the isolation board 160 is completely electrically isolated from the simulator side 140. In actual use, the simulator side 140 is connected to the computer via a USB interface 110. Since the isolation capacitor includes an upper plate and a lower plate, both the upper and lower plates are connected to the internal circuitry of the chip through interconnect pillars to achieve signal transmission. A dielectric layer is provided between the upper and lower plates to form an electrical isolation barrier. The dielectric layer is a silicon dioxide filling layer, which achieves electrical isolation between the debugging equipment (simulator side 140) and the high-voltage target board side 130 (e.g., isolation voltage 1000V). DC or higher) effectively prevents the harm of high voltage, surge, and ground loop current to personnel and expensive debugging equipment. This ensures that a "ground loop" will not be formed between the board under test and the simulator or computer, thus avoiding the introduction of noise and interference that could lead to unstable debugging signals, program download failures, or even abnormal operation of the target MCU. Through fully differential isolation capacitor technology, the simulator side 140 is isolated from the target board side 130, that is, a high impedance barrier is established between the simulator side 140 and the target board side 130 to prevent current from passing directly, but to allow signals (data, clock) to pass through. At the same time, it suppresses common-mode noise, which greatly enhances reliability in noisy power electronic environments. Meanwhile, the radiation of differential signals is also less.
[0033] As a second embodiment of this utility model:
[0034] Please see Figures 1 to 4An interface board is provided on the target board side 130. This interface board is a type of anti-reverse insertion horn terminal. It uses asymmetrical pin definitions to prevent reverse insertion and will not cause a direct short circuit between VCC and GND, thus damaging the isolation.
[0035] Based on the first embodiment described above, further, by setting the target board side 130 interface, in actual use, since the interface board is a type of anti-reverse insertion horn terminal, it adopts an asymmetrical pin definition to achieve anti-reverse insertion. The unique target board side 130 interface pin definition design (asymmetrical arrangement) can effectively prevent the target board MCU from burning out due to reverse connection of the interface. This makes the entire device have anti-reverse connection protection function, plug and play, and thus simplify the debugging process.
[0036] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.
Claims
1. A capacitive isolation simulation device, comprising: The housing (100) is characterized in that a PCB board (120) is installed inside the housing (100) for setting an isolation plate (160), and the PCB board (120) is provided with an isolation plate (160) for setting a target board side (130) and a simulator side (140), and the isolation plate (160) includes a target board side (130) and a simulator side (140); The target board side (130) is located on one side of the PCB board (120). The target board side (130) is provided with a buffer circuit to increase robustness and to accommodate multiple sources of the reset signal. The emulator side (140) is located on the other side of the PCB board (120). The target board side (130) and the emulator side (140) are completely electrically isolated. A digital isolation chip for capacitive isolation is installed on the isolation board (160). The digital isolation chip (150) contains an isolation capacitor. The digital isolation chip (150) is connected to the target board side (130) and the emulator side (140) through pins.
2. The capacitive isolation simulation device as described in claim 1, characterized in that: The top four corners of the outer casing (100) are each provided with a plastic stud, which penetrates the PCB board (120) and is fixed by a plastic nut. The bottom of the outer casing (100) is fixed with a bottom cover by studs and plastic nuts. The front side of the outer casing (100) is provided with a USB interface (110) for electrical connection with an external calculator.
3. The capacitive isolation simulation device as described in claim 1, characterized in that: The isolation capacitor includes an upper plate and a lower plate. Both the upper plate and the lower plate are connected to the internal circuit of the chip through interconnect pillars to realize signal transmission. A dielectric layer is provided between the upper plate and the lower plate to form an electrical isolation barrier. The dielectric layer is a silicon dioxide filling layer.
4. The capacitive isolation simulation device as described in claim 1, characterized in that: Both sides of the isolation board (160) need to be powered independently. The simulator side (140) draws power from the 8-pin of the 14-pin interface or the 1-pin of the 20-pin interface, while the target board side (130) draws power from the Pin8 of the target board's debugging interface or is powered by an external independent power supply.
5. The capacitive isolation simulation device as described in claim 1, characterized in that: The digital isolation chip (150) provides unidirectional or bidirectional isolation for the LPDCLK, LPDO, LPDI, LPDCLK0, and RESET signals, with LPDCLK being isolated only bidirectionally.
6. The capacitive isolation simulation device as described in claim 1, characterized in that: The PCB board (120) also integrates LED indicator lights to display the power supply of the simulator side (140), the power supply of the target board side (130), and the RESET status for easy observation of the debugging status.
7. The capacitive isolation simulation device as described in claim 1, characterized in that: The target board side (130) is provided with an interface board, which is a type of anti-reverse insertion horn terminal. It adopts an asymmetrical pin definition to prevent reverse insertion and will not cause a direct short circuit between VCC and GND, thereby damaging the isolation.