Intelligent power control system

Abstract

The application discloses an intelligent power supply control system, and relates to the field of intelligent power supply management equipment.The system comprises an LCD display module and a power supply management MCU chip, wherein the power supply management MCU chip is internally integrated with a nonvolatile memory, a CPU module, a PMU module, an LCD controller and a bandwidth arbitrator; the bandwidth arbitrator is connected with the nonvolatile memory, the CPU module and the LCD controller; the CPU module is connected with the PMU module and the LCD controller; the output end of the LCD controller is in communication connection with the LCD display module; the nonvolatile memory internally stores color screen display memory data and instruction codes to be executed by the CPU module; and the bandwidth arbitrator configures the priority and bandwidth of the nonvolatile memory in responding to an access request when an access conflict occurs.The application simplifies the hardware circuit.

Description

Technical Field

[0001] This application relates to the field of intelligent power management equipment, and in particular to an intelligent power control system. Background Technology

[0002] TFT (Thin-Film Transistor Liquid Crystal Display) screens utilize thin-film transistor-based liquid crystal display technology, offering advantages such as high resolution, fine image detail, and rich, vibrant colors, making them widely used in various electronic devices. Currently, there is a growing demand for color screen displays in intelligent power management devices such as power banks, power adapters, and outdoor power supplies. These displays are used to accurately show various information, including battery percentage, charging / discharging status parameters, estimated usage time, real-time temperature, and fault codes, and even support simple user interface controls.

[0003] The structure of a traditional intelligent power control system for color screen displays is as follows: Figure 1 As shown, the system mainly includes a general-purpose MCU (Microcontroller Unit) chip (such as STM32), a video memory storage chip (NVM2), a power management chip, and an LCD display module. The video memory storage chip stores a large amount of color screen display data. The general-purpose MCU chip is a microcontroller unit that integrates a CPU, non-volatile memory (NVM1), an LCD controller, and various peripheral interfaces onto a single chip. The general-purpose MCU chip controls the LCD display module for color screen display. The power management chip is used for intelligent management of the power management device, including communication and power negotiation between the intelligent power management device and external devices. It not only supports multi-protocol charging but also integrates buck-boost control, battery management, and multi-port charging / discharging functions. Some color screen display power control systems with higher levels of intelligent control integrate an MCU module (i.e., with a CPU and non-volatile memory) within their power management chip, such as... Figure 2As shown in the diagram. It can be seen that in existing solutions, regardless of whether the power management chip includes an MCU module, the LCD controller is integrated into a general-purpose MCU. The color screen display control is implemented by this general-purpose MCU chip. Since the storage capacity of commonly available general-purpose MCU chips supporting color screen displays is usually below 256KB, and a typical 240*320 resolution small-sized color screen with a common RGB565 color depth configuration has a single full-screen data volume of 150KB, the storage capacity within the general-purpose MCU chip is clearly insufficient to meet the large data storage requirements of color screen displays. Furthermore, relying on the CPU to move the color screen display data stored in the on-chip memory NVM1 makes it difficult to meet the timely access requirements of the LCD display module to the video memory data. Therefore, video memory data is stored through an external video memory data storage chip (NVM2). However, the inventors of this application have discovered the following problems with the existing solutions: The general-purpose MCU chip in the existing system needs to be connected to the external NVM2 through a communication interface, and also needs to be connected to the power management chip / power management MCU chip through a communication interface, which results in a lot of hardware circuits, high software and hardware design complexity, material risks and high material costs. Summary of the Invention

[0004] The purpose of this application is to provide an intelligent power control system and chip, which can simplify the hardware circuit of the intelligent power control system, thereby reducing the complexity of software and hardware design, material risks and material costs.

[0005] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides an intelligent power control system, including an LCD display module and a power management MCU chip. The power management MCU chip integrates non-volatile memory, a CPU module, a PMU module, an LCD controller, and a bandwidth arbiter, wherein: The bandwidth arbiter is connected to the non-volatile memory, the CPU module, and the LCD controller. The CPU module is connected to the PMU module and the LCD controller. The LCD controller is communicatively connected to the LCD display module. The non-volatile memory stores color screen display memory data and instruction code to be executed by the CPU module. The bandwidth arbiter configures the priority and bandwidth of access requests when an access conflict occurs.

[0006] Optionally, the bandwidth arbitrator includes an arbitration controller, which includes a request arbitration module, an address selector, and a data distributor, wherein: The input terminal of the arbitration request module is connected to the first access request output terminal, the second access request output terminal, the arbitration scheme selection signal output terminal, the emergency signal output terminal, the busy read process flag output terminal, and the read completion flag output terminal; the access request output terminal of the arbitration request module is connected to the access request input terminal of the non-volatile memory; the arbitration request module configures the priority and bandwidth of the access request when an access conflict occurs. The input terminal of the address selector is connected to the instruction code storage address output terminal of the CPU module, the display memory data storage address output terminal of the LCD controller, and the device selection signal output terminal of the request arbitration module; the output terminal of the address selector is connected to the access address input terminal of the non-volatile memory; the device selection signal includes a valid LCD response signal sel_lcd_req or a valid CPU response signal sel_cpu_req; wherein, the address selector configures the access address when an access conflict occurs; The input terminal of the data distributor is connected to the device selection signal output terminal, the data output terminal of the non-volatile memory, and the read completion flag output terminal. The data output terminal of the data distributor is connected to the instruction code input terminal and the video memory data input terminal. The read signal output terminal of the data distributor is connected to the read signal input terminal of the CPU module and the read signal input terminal of the LCD controller. The data distributor allocates the data to be read by the selected device when an access conflict occurs.

[0007] Optionally, the arbitration request module includes a signal processor, an arbitrator, a first NOT gate, a first AND gate, and a first OR gate, wherein: The input terminal of the signal processor is connected to the arbitration scheme selection signal output terminal, the first access request output terminal, the second access request output terminal, the emergency signal output terminal, the busy read process flag output terminal, and the read completion flag output terminal. The output terminal of the signal processor is connected to the input terminal of the request arbitrator. The input terminal of the first NOT gate is connected to the CPU response signal output terminal of the request arbitrator. The input terminal of the first AND gate is connected to the output terminal of the first NOT gate and the LCD access signal output terminal of the signal processor. The input terminal of the first OR gate is connected to the output terminal of the first AND gate and the CPU response signal output terminal. The output terminal of the first OR gate is connected to the access request input terminal of the non-volatile memory. The signal processor latches the access request, the arbitration scheme selection signal, and the emergency signal when the non-volatile memory is idle. The request arbitrator configures the priority and bandwidth of the access request when an access conflict occurs and the non-volatile memory is idle.

[0008] Optionally, the data distributor includes a second NOT gate, a second AND gate, and a third AND gate, wherein: The input of the second NOT gate is connected to the CPU response signal output, the first input of the second AND gate and the first input of the third AND gate are connected to the read completion flag output of the non-volatile memory, the second input of the second AND gate is connected to the CPU response signal output, and the second input of the third AND gate is connected to the output of the second NOT gate; or, the input of the second NOT gate is connected to the LCD response signal output, the first input of the second AND gate and the first input of the third AND gate are connected to the read completion flag output of the non-volatile memory, the second input of the third AND gate is connected to the LCD response signal output, and the second input of the second AND gate is connected to the output of the second NOT gate; The output of the second AND gate is connected to the second read signal input of the CPU module, and the output of the third AND gate is connected to the first read signal input of the LCD controller.

[0009] Optionally, the signal processor includes a fourth AND gate, a third NOT gate, a second OR gate, a clock gate, a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop, wherein: The input of the fourth AND gate is connected to the output of the read completion flag and the read process busy flag; the input of the third NOT gate is connected to the output of the read process busy flag; the input of the second OR gate is connected to the output of the fourth AND gate and the output of the third NOT gate; the input of the clock gating is connected to the output of the second OR gate and the first clock signal clk; the clock inputs of the first, second, third, and fourth flip-flops are connected to the output of the clock gating; the D terminal of the first flip-flop is connected to the second access request; the D terminal of the second flip-flop is connected to the first access request; the D terminal of the third flip-flop is connected to the emergency signal; and the input of the fourth flip-flop is connected to the arbitration scheme selection signal.

[0010] Optionally, the request arbitrator includes a fifth AND gate, a third OR gate, a fourth NOT gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, and a fourth OR gate, wherein: The input terminals of the fifth AND gate are the Q terminals of the first and second flip-flops. The input terminal of the third OR gate is connected to the Q terminals of the third and fourth flip-flops. The input terminal of the fourth NOT gate is connected to the output terminal of the fifth AND gate. The input terminal of the sixth AND gate is connected to the output terminal of the fourth NOT gate and the Q terminal of the second flip-flop. The input terminal of the seventh AND gate is connected to the output terminal of the third OR gate and the Q terminal of the second flip-flop. The input terminal of the eighth AND gate is connected to the output terminals of the fifth and seventh AND gates. The input terminal of the fourth OR gate is connected to the output terminals of the sixth and eighth AND gates.

[0011] Optionally, the fourth flip-flop is a 2-bit flip-flop, where the low-order D-terminal of the fourth flip-flop is connected to represent the low-order bit of the binary code of the arbitration scheme selection signal, and the high-order D-terminal of the fourth flip-flop is connected to represent the high-order bit of the binary code of the arbitration scheme selection signal.

[0012] Optionally, the request arbitrator includes a first control module and a second control module, wherein: The input terminal of the first control module is connected to the Q terminals of the first flip-flop, the second flip-flop, the third flip-flop, the fourth flip-flop, and the read completion flag output terminal; the input terminal of the second control module is connected to the output terminal of the first control module and the Q terminals of the first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop, and the output terminal of the second control module is connected to the input terminal of the first NOT gate.

[0013] Optionally, the second control module includes a first comparator, a ninth AND gate, a fifth NOT gate, a tenth AND gate, an eleventh AND gate, a twelfth AND gate, a thirteenth AND gate, a fourteenth AND gate, a fifteenth AND gate, a fifth NOT gate, a sixth NOT gate, a fifth OR gate, a sixth OR gate, and a seventh OR gate, wherein: The input of the ninth AND gate is connected to the Q terminals of the first and second flip-flops. The input of the fifth NOT gate is connected to the output of the ninth AND gate. The input of the tenth AND gate is connected to the output of the fifth NOT gate and the CPU access signal output. The input of the fourteenth AND gate is connected to the CPU access signal output and the second output of the first comparator. The input of the fifteenth AND gate is connected to the output of the first control module and the first output of the first comparator. The input of the first comparator is connected to the Q terminal of the fourth flip-flop. The input of the seventh OR gate is connected to the output of the fourteenth AND gate and the fifteenth AND gate. The output of the gate, the input of the sixth NOT gate is connected to the Q terminal of the third flip-flop, the input of the thirteenth AND gate is connected to the output of the seventh OR gate and the output of the sixth NOT gate, the input of the twelfth AND gate is connected to the CPU access signal output and the Q terminal of the third flip-flop, the input of the sixth OR gate is connected to the output of the twelfth AND gate and the output of the thirteenth AND gate, the input of the eleventh AND gate is connected to the output of the ninth AND gate and the output of the sixth OR gate, the input of the fifth OR gate is connected to the output of the tenth AND gate and the eleventh AND gate, and the output of the fifth OR gate is connected to the input of the first NOT gate.

[0014] Optionally, the data distributor includes a 30th AND gate and a 31st AND gate, wherein: The first input of the 30th AND gate and the first input of the 31st AND gate are connected to the read completion flag output of the non-volatile memory. The second input of the 30th AND gate is connected to the CPU response signal output. The second input of the 31st AND gate is connected to the LCD response signal output. The output of the 30th AND gate is connected to the second read signal output of the CPU module. The output of the 12th AND gate is connected to the first read signal output of the LCD controller.

[0015] According to the specific embodiments provided in this application, the following technical effects are disclosed: This application provides an intelligent power control system. By integrating non-volatile memory, a CPU module, a PMU module, and an LCD controller within a power management MCU chip, the non-volatile memory can simultaneously store color screen display memory data and instruction codes to be executed by the CPU module. This achieves the storage of display memory data through the non-volatile memory integrated within the power management MCU chip, eliminating the need for an external display memory data storage chip. By integrating a bandwidth arbitrator within the power management MCU chip, when an access conflict occurs (the CPU module and the LCD controller simultaneously access the non-volatile memory), the priority and bandwidth allocation of the non-volatile memory in response to the first and second access requests are configured to handle the access conflict. The CPU module connects to the PMU module and the LCD controller, enabling the power management MCU chip to control the LCD display module, thereby avoiding the use of an external general-purpose MCU chip to control the LCD display module.

[0016] In summary, compared with existing technologies, this application does not require a general-purpose MCU chip or an external video memory data storage chip, thus avoiding the connection between the general-purpose MCU chip and the external video memory data storage chip, as well as the connection between the general-purpose MCU chip and the power management chip / power management MCU chip. This simplifies the hardware circuitry of the intelligent power control system, thereby reducing the design complexity of the intelligent power control system's hardware and software, reducing the number of chips in the system and the number of communication interfaces between chips, and thus reducing the material risks and costs of the intelligent power control system's hardware and software. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of an existing intelligent power control system. Figure 2 This is a schematic diagram of another existing intelligent power control system. Figure 3 This is a schematic diagram of the structure of an intelligent power control system provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a bandwidth arbiter provided in one embodiment of this application; Figure 5 This is a schematic diagram of the structure of an arbitration controller provided in one embodiment of this application; Figure 6A schematic diagram of the structure of a signal processor provided in an embodiment of this application. Figure 7 A schematic diagram of the circuit principle of a request arbitrator provided in an embodiment of this application; Figure 8 This is a schematic diagram of the circuit principle of a bandwidth arbitrator provided in one embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] In one exemplary embodiment, such as Figure 3 As shown, an intelligent power control system is provided, including an LCD display module 101 and a power management MCU chip 102. The power management MCU chip 102 integrates a non-volatile memory (NVM) 201, a CPU module 202, a PMU module 203, an LCD controller 204, and a bandwidth arbitrator 205. Wherein: The output of the non-volatile memory 201 is connected to the bandwidth arbiter 205 via a universal access bus. The bandwidth arbiter 205 is connected to the CPU module 202 and the LCD controller 204 via a universal access bus. The CPU module 202 is connected to the PMU module 203 via a universal access bus. The CPU module 202 is connected to the LCD controller 204 via a universal access bus. The output of the LCD controller 204 is connected to the LCD display module 101 via a serial communication interface (such as SPI).

[0022] The non-volatile memory 201 is used to store color screen display memory data and instruction codes to be executed by the CPU module. The CPU module 202 is used to read instruction codes from the non-volatile memory 201 and receive target information sent by the PMU module 203, and control the PMU module 203 and LCD controller 204 to work.

[0023] PMU module 203 is used to manage the power of intelligent power management devices according to the second control command sent by CPU module 202.

[0024] The LCD controller 204 is used to: control the LCD display module 101 to initialize according to the first control instruction sent by the CPU module 202; or, read the color screen display memory data at the corresponding location in the non-volatile memory 201 according to the display memory data storage address sent by the CPU module 202, and send the read color screen display memory data and the position parameters updated and sent by the CPU module 202 to the initialized LCD display module 101 according to the interface protocol of the LCD display module 101, so that the LCD display module 101 displays the target information in the corresponding position area according to the received position parameters and color screen display memory data.

[0025] The bandwidth arbiter 205 is used to configure the priority and bandwidth for responding to access requests when an access conflict occurs.

[0026] In this embodiment, since both the CPU module 202 and the LCD controller 204 read data from the non-volatile memory 201, access conflicts may occur. An access conflict occurs when both the CPU module 202 and the LCD controller 204 simultaneously request access to the non-volatile memory 201. To resolve this issue, a bandwidth arbitrator 205 is provided. When an access conflict occurs, the bandwidth arbitrator 205 configures the priority and bandwidth for responding to the access request, thus handling the access conflict and fully satisfying the timeliness requirement of the CPU module 202's access. Compared to existing technologies, the LCD controller 204 reads data directly from the non-volatile memory 201 without needing to indirectly read data from the non-volatile memory 201 through the CPU module 202, fully satisfying the real-time requirement of the LCD controller 204 accessing large amounts of data in a short period.

[0027] Intelligent power management devices include, but are not limited to, power banks, power adapters, or outdoor power supplies. Target information includes, but is not limited to, at least one of the following: battery percentage, charging status parameters, discharging status parameters, power parameters, estimated usage time, real-time temperature, cause of abnormality, and fault code.

[0028] The general-purpose access bus mainly includes access request signal lines, access address signal lines, and access data signal lines. The general-purpose access bus is a common communication bus used by the CPU module 202 to control other modules, such as AHB and APB buses.

[0029] PMU module 203 is used for power management functions such as power conversion and regulation, charge and discharge protocol control, dynamic power management, battery management, and protection mechanisms for intelligent power management devices, and is responsible for sending target information to CPU module 202.

[0030] The non-volatile memory 201 may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc.

[0031] Compared to existing intelligent power control systems, this application embodiment integrates a non-volatile memory 201, a CPU module 202, a PMU module 203, and an LCD controller 204 within the power management MCU chip 102. This allows the non-volatile memory 201 to simultaneously store color screen display memory data and the instruction code to be executed by the CPU module 202. This achieves storage of display memory data through the integrated non-volatile memory 201 within the power management MCU chip 101, eliminating the need for an external display memory data storage chip. Furthermore, by integrating a bandwidth arbitrator within the power management MCU chip, in the event of an access conflict (between the CPU module and the LCD controller), the system can prevent the display memory from being accessed. When the controller simultaneously accesses non-volatile memory, it configures the priority and bandwidth of the non-volatile memory to respond to access requests, thereby handling access conflicts. The CPU module reads instruction codes from the non-volatile memory and receives target information sent by the PMU module, controlling the PMU module 203 and the LCD controller 204 to operate. This allows the PMU module 203 to manage the power of the intelligent power management device according to the second control instruction sent by the CPU module 202, while the LCD controller 204 controls the LCD display module 101 to initialize according to the first control instruction sent by the CPU module 202. Alternatively... The CPU module 202 reads the color screen display memory data at the corresponding location in the non-volatile memory 201 according to the display memory data storage address. Following the interface protocol of the LCD display module 101, the read color screen display memory data and the position parameters updated and sent by the CPU module 202 are sent to the initialized LCD display module 101. This allows the initialized LCD display module 101 to display the target information in the corresponding position area based on the received position parameters and color screen display memory data. This achieves control of the LCD display module 101 to display target information using the power management MCU chip 102, thus avoiding the need for an external general-purpose MCU chip. In summary, compared to existing technologies, this application does not require a general-purpose MCU chip or an external display memory data storage chip. It avoids the connection between the general-purpose MCU chip and the external display memory data storage chip, as well as the connection between the general-purpose MCU chip and the power management chip / power management MCU chip. This simplifies the hardware circuitry of the intelligent power control system, thereby reducing the design complexity of the intelligent power control system's hardware and software, reducing the number of chips in the system and the number of communication interfaces between chips, and thus reducing the material risks and costs associated with the intelligent power control system's hardware and software.

[0032] In another exemplary embodiment of this application, such as Figure 4 As shown, the bandwidth arbiter 205 described above includes: Arbitration controller 301 is used to configure the priority and bandwidth of responding to the first access request cpu_req and the second access request lcd_req according to a preset arbitration scheme when an access conflict occurs. The first access request is from the CPU module 202, and the second access request is from the LCD controller 204. Specifically: If the non-volatile memory 201 is free, the priority of responding to the first access request cpu_req and the second access request lcd_req will be configured immediately according to the preset arbitration scheme.

[0033] If the non-volatile memory 201 is busy (responding to the first access request cpu_req or the second access request lcd_req), then after the non-volatile memory 201 has finished responding to the reading of the current data, the priority and bandwidth of responding to the first access request cpu_req and the second access request lcd_req will be configured according to the preset arbitration scheme.

[0034] The embodiments of this application ensure the operational stability of the non-volatile memory 201 and enable accurate reading of data from the non-volatile memory 201.

[0035] In another exemplary embodiment of this application, in order to address the requirements for handling access conflicts in different application scenarios, different arbitration schemes can be set for different scenarios.

[0036] Specifically, for scenarios requiring a low-level response to access requests from CPU module 202, the arbitration scheme adopts the first scheme: First respond to the second access request lcd_req until the access conflict disappears, and then respond to the first access request cpu_req after the access conflict disappears.

[0037] For scenarios requiring a high-level response to access requests from CPU module 202, the arbitration scheme adopts the second option: First, respond to the first access request cpu_req until the access conflict disappears. After the access conflict disappears, respond to the second access request lcd_req.

[0038] For scenarios where the bandwidth required by the LCD controller 204 is similar to that of the non-volatile memory 201 (the difference is within a preset range), or for scenarios where there are no requirements on the level of responding to access requests from the CPU module 202 and the LCD controller 204, the arbitration scheme includes a third scheme: The system periodically and alternately responds to the first access request cpu_req and the second access request lcd_req until the access conflict ends.

[0039] In this embodiment, the first solution can be used in scenarios where a low-level response to the CPU module 202's access request cpu_req is required, such as when an LCD needs to urgently display an important interface. The second solution can be used in scenarios where a high-level response to the CPU module 202's access request cpu_req is required, such as when the CPU needs to quickly complete transaction processing within a short period of time.

[0040] For scenarios where the bandwidth required by the LCD controller 204 is similar to that of the non-volatile memory 201 (the difference is within a preset range), to avoid continuously responding to the second access request lcd_req when an access conflict occurs, or for scenarios where there are no requirements on the level of responding to access requests from the CPU module and the LCD controller 204, to avoid continuously responding to either the first access request cpu_req or the second access request lcd_req when an access conflict occurs, a third arbitration scheme can be adopted. The third scheme can also be used for other general responsiveness requirements.

[0041] In another exemplary embodiment of this application, the above-mentioned periodic alternating response to access requests cpu_req and lcd_req until the access conflict ends specifically includes: Each time an access conflict occurs, the output control signal acc_toggle is toggled. If the level of the control signal acc_toggle is in the first state, the first response process is looped until the access conflict ends. Otherwise, the second response process is looped until the access conflict ends. Here, the first state refers to a low level or a high level.

[0042] In this embodiment of the application, the control signal acc_toggle is not reversed during both periods of access conflict and periods without access conflict.

[0043] If the first state is low, when an access conflict occurs, if the control signal acc_toggle is low, the first response process is looped until the access conflict ends; if the control signal acc_toggle is high, the second response process is looped until the access conflict ends.

[0044] Specifically, the aforementioned first response process includes: First, respond to the second access request lcd_req m times consecutively, causing the LCD controller 204 to read m data from the non-volatile memory 201. Then, respond to the first access request cpu_req n times consecutively, causing the CPU module 202 to read n data from the non-volatile memory 201.

[0045] The second response process mentioned above includes: First, respond to the first access request cpu_req n times consecutively, causing the CPU module 202 to read n data from the non-volatile memory 201. Then, respond to the second access request lcd_req m times consecutively, causing the LCD controller 204 to read m data from the non-volatile memory 201.

[0046] In this embodiment, n and m represent the bandwidth allocation of the non-volatile memory 201 controlled by the arbitration controller 301 in response to the first access request cpu_req and the second access request lcd_req according to a preset arbitration scheme. Bandwidth allocation is implemented when access conflicts occur by setting the values ​​of m and n.

[0047] In another exemplary embodiment of this application, when an access conflict occurs, the arbitration controller 301 is further configured to: If only a valid first signal is received, the second access request lcd_req is responded to according to the first scheme configuration until the access conflict disappears. After the access conflict disappears, the first access request cpu_req is responded to.

[0048] If only a valid second signal or a valid emergency signal (scene_urgent) is received, the first access request cpu_req is responded to according to the second scheme configuration until the access conflict disappears, and the second access request lcd_req is responded to after the access conflict disappears.

[0049] If only a valid third signal is received, the system will periodically and alternately respond to the first access request cpu_req and the second access request lcd_req according to the third scheme configuration until the access conflict ends.

[0050] In this embodiment, a valid emergency signal (scene_urgent) is sent by the PUM module 203. The emergency signal may include an emergency interruption signal or an abnormal emergency handling signal. Receiving a valid emergency signal (scene_urgent) includes receiving only a valid emergency signal (scene_urgent), and simultaneously receiving a valid emergency signal (scene_urgent) along with any one of the first, second, and third signals. In this case, if an access conflict occurs, the first access request (cpu_req) is responded to according to the second scheme configuration.

[0051] If the PUM module 203 experiences an emergency requiring immediate response, such as overcurrent, overvoltage, or overtemperature, it will issue an emergency signal `scene_urgent`, prompting the CPU module 202 to handle the emergency. If an access conflict occurs at this time, the arbitration controller 301, based on the emergency signal `scene_urgent`, will control the non-volatile memory 201 to first respond to the first access request `cpu_req`, causing the CPU module 202 to handle the overcurrent, overvoltage, or overtemperature emergency from the PUM module 203. After the emergency from the PUM module 203 is resolved, the access conflict is eliminated, and the second access request `lcd_req` can be responded to. After the emergency response is completed, the emergency signal `scene_urgent` received by the arbitration controller 301 is invalid. At this point, the arbitration scheme used by the arbitration controller 301 to handle the access conflict is determined based on the first, second, or third signal it receives.

[0052] In another exemplary embodiment of this application, the first signal, the second signal, and the third signal are all binary codes configured by the internal bus configuration register of the CPU module 202. Any three of the binary values ​​00, 01, 10, and 11 can be selected as the first, second, and third signals configured within the register of the CPU module 202 for managing and controlling bus operations. For example, the first signal can be set to 00 or 11, the second signal to 10, and the third signal to 01.

[0053] In another exemplary embodiment of this application, to ensure that the arbitration controller 301 can accurately control the priority and bandwidth allocation of the non-volatile memory 201 in response to the first access request cpu_req and the second access request lcd_req according to the third scheme, such as Figure 4 As shown, the bandwidth arbiter 205 also includes: The counting module 302 is used to count the number of consecutive responses to the first access request cpu_req and the number of consecutive responses to the second access request lcd_req during the cyclic first response process or the second response process when an access conflict occurs.

[0054] In this embodiment of the application, when the counting module 302 counts the number of consecutive responses to the first access request cpu_req or the second access request lcd_req, the counting module 302 starts from 0. Every time the LCD controller 204 or the CPU module 202 reads a piece of data from the non-volatile memory 201, the count of the counting module 302 is incremented by 1.

[0055] Accordingly, the arbitration controller 301 described above is also used for: During each loop of the first response process, the counting module 302 is controlled to count the number of consecutive responses to the second access request lcd_req starting from zero. If the count value of the counting module 302 reaches m, the response to the second access request lcd_req is stopped, and the response to the first access request cpu_req is started. The counting module 302 is controlled to count the number of consecutive responses to the first access request cpu_req starting from zero. When the count value of the counting module 302 reaches n, the response to the first access request cpu_req is stopped.

[0056] During each loop of the second response process, the counting module 302 is first controlled to count the number of consecutive responses to the first access request cpu_req starting from zero. If the count value of the counting module 302 reaches n, the response to the first access request cpu_req is stopped, and the response to the second access request lcd_req is started. The counting module 302 is then controlled to count the number of consecutive responses to the second access request lcd_req starting from zero. When the count value of the counting module 302 reaches m, the response to the access request lcd_req is stopped.

[0057] In another exemplary embodiment of this application, to achieve accurate counting, the counting module 302 includes: The first counter is used to count the number of consecutive responses to the first access request cpu_req during the loop of the first response process or the second response process when an access conflict occurs. The second counter is used to count the number of consecutive responses to the second access request lcd_req during the loop of the first response process or the second response process when an access conflict occurs.

[0058] In this embodiment, when there is no conflict, the first counter and the second counter are reset to 0. When the first counter counts, the second counter is reset to 0. When the second counter counts, the first counter is reset to 0.

[0059] Accordingly, the arbitration controller 301 described above is also used for: During each loop of the first response process, the second counter is controlled to start counting the number of consecutive responses to the second access request lcd_req from zero. If the count value of the second counter reaches m, the response to the second access request lcd_req is stopped, and the response to the first access request cpu_req is started. The first counter is controlled to start counting the number of consecutive responses to the first access request cpu_req from zero. When the count value of the first counter reaches n, the response to the first access request cpu_req is stopped.

[0060] During each loop of the second response process, the first counter is controlled to start counting the number of consecutive responses to the first access request cpu_req from zero. If the count value of the first counter reaches n, the response to the first access request cpu_req stops, and the response to the second access request lcd_req begins. The second counter is then controlled to start counting the number of consecutive responses to the second access request lcd_req from zero. The response to the second access request lcd_req stops when the count value of the second counter reaches m.

[0061] In one exemplary embodiment of this application, the internal structure of the arbitration controller 301 is as follows: Figure 5 As shown, it includes an arbitration request module 501, an address selector 502, and a data distributor 503. Wherein: The input terminal of the arbitration request module 501 is connected to the first access request output terminal, the second access request output terminal, the arbitration scheme selection signal output terminal, the emergency signal output terminal, the busy reading process flag output terminal, and the reading completion flag output terminal. The access request output terminal of the arbitration request module 501 is connected to the input terminal of the non-volatile memory 201.

[0062] The arbitration request module 501 is used to configure the priority and bandwidth of access requests when an access conflict occurs. Specifically, when the non-volatile memory 201 is idle (the busy flag acc_busy and the read completion flag req_ack are both valid, or the busy flag acc_busy is invalid), it latches the first access request, the second access request, the arbitration scheme selection signal, and the urgent signal. Based on the latched output CPU access signal m_cpu_req, LCD access signal m_lcd_req, urgent flag signal m_scene_urgent, and scheme selection signal m_cpu_pri, it determines the access conflict status and the module that will obtain the arbitration response. The scheme selection signal m_cpu_pri includes a first scheme selection signal, a second scheme selection signal, or a third scheme selection signal. If both the CPU access signal m_cpu_req and the LCD access signal m_lcd_req are valid, an access conflict occurs. In this case: If the emergency flag signal m_urgent is valid or only the second scheme selection signal m_cpu_pr2 is valid, output a valid CPU response signal sel_cpu_req. If only the first scheme selection signal m_cpu_pr0 / m_cpu_pr3 is valid, output a valid LCD response signal sel_lcd_req; If only the third scheme selection signal m_cpu_pr1 is valid, the valid CPU response signal sel_cpu_req and the valid LCD response signal sel_lcd_req are output alternately. If the CPU response signal sel_cpu_req or the LCD response signal sel_lcd_req is valid, a third access request is generated and sent to the non-volatile memory 201.

[0063] The input of address selector 502 is connected to the output of the first access request address (cpu_addr), the output of the second access request address (lcd_addr), and the output of the device selection signal. The first access request address is the address of the non-volatile memory 201 requested by the CPU module 202, and the second access request address is the address of the non-volatile memory 201 requested by the LCD controller 204. The output of address selector 502 is connected to the access address input of the non-volatile memory 201.

[0064] Address selector 502 is used for: Upon receiving a valid LCD response signal sel_lcd_req, the second access request address lcd_addr is selected as the final access address req_addr and sent to the access address input terminal of the non-volatile memory 201. Upon receiving a valid CPU response signal sel_cpu_req, the first access request address cpu_addr is selected as the final access address req_addr and sent to the access address input terminal of the non-volatile memory 201, so that the non-volatile memory 201 reads and outputs the data stored in the final access address.

[0065] In this embodiment, the first access request address cpu_addr is the access request address of the CPU module 202, and the second access request address lcd_addr is the access request address of the LCD controller 204. The non-volatile memory 201 reads the data req_data stored in the final access address req_addr according to the received third access request nvm_req and the final access address req_addr. During the reading of the data req_data stored in the final access address req_addr, the non-volatile memory 201 sends a busy read flag acc_busy, and after reading the data req_data stored in the final access address req_addr, it sends a complete read flag req_ack. The acc_busy signal is pulled low when the req_ack signal appears (the acc_busy signal is invalid).

[0066] The input terminal of the data distributor 503 is connected to the device selection signal output terminal, the data output terminal of the non-volatile memory 201, and the read completion flag output terminal. The data output terminal of the data distributor 503 is connected to the instruction code input terminal of the CPU module 202 and the display memory data input terminal of the LCD controller 204. The read signal output terminal of the data distributor 503 is connected to the read signal input terminal of the CPU module 202 and the read signal input terminal of the LCD controller 204.

[0067] The data distributor 503 is configured to: upon receiving a valid read completion flag req_ack and a valid LCD response signal sel_lcd_req, generate a valid first read signal lcd_ack and send it to the LCD controller 204, so that the LCD controller 204 reads the data req_data extracted from the non-volatile memory 201; and upon receiving a valid read completion flag req_ack and a valid CPU response signal sel_cpu_req, generate a valid second read signal cpu_ack and send it to the CPU module 202, so that the CPU module 202 reads the data req_data extracted from the non-volatile memory 201.

[0068] In one exemplary embodiment of this application, such as Figure 5 As shown, the address selector 502 described above uses a MUX selector.

[0069] In one exemplary embodiment of this application, such as Figure 5 As shown, the above-mentioned arbitration request module 501 includes a signal processor 601, an arbitrator 602, a first NOT gate N2, a first AND gate A3, and a first OR gate O2, wherein: The input terminals of signal processor 601 are connected to the arbitration scheme selection signal output terminal, the first access request output terminal, the second access request output terminal, the emergency signal output terminal, the busy read process flag output terminal, and the read completion flag output terminal. The output terminal of signal processor 601 is connected to the input terminal of request arbitrator 602. The input terminal of the first NOT gate N2 is connected to the CPU response signal output terminal of request arbitrator 602. The input terminal of the first AND gate A3 is connected to the output terminal of the first NOT gate N2 and the LCD access signal (m_lcd_req) output terminal of signal processor 601. The first input terminal of the first OR gate O2 is connected to the output terminal of the first AND gate A3. The second input terminal of the first OR gate O2 is connected to the CPU response signal output terminal of request arbitrator 602. The output terminal of the first OR gate O2 is connected to the access request input terminal of non-volatile memory 201.

[0070] In this embodiment, the signal processor 601 is used to latch access requests, arbitration scheme selection signals, and emergency signals when the non-volatile memory 201 is idle, and outputs the latched CPU access signal m_cpu_req, LCD access signal m_lcd_req, emergency flag signal m_scene_urgent, and scheme selection signal m_cpu_pri. When the non-volatile memory 201 is busy (the busy flag acc_busy is valid during the read process, and the read completion flag req_ack is invalid), the original signal output state is retained. Specifically: When the non-volatile memory 201 is idle (the busy read flag acc_busy is valid, and the read completion flag req_ack is invalid): If the first access request cpu_req is valid, output a valid CPU access signal m_cpu_req; otherwise, output an invalid CPU access signal m_cpu_req. If the second access request lcd_req is valid, output a valid LCD access signal m_lcd_req; otherwise, output an invalid LCD access signal m_lcd_req. If the emergency signal scene_urgent is valid, output a valid emergency flag signal m_urgent; otherwise, output an invalid emergency flag signal m_urgent. If the arbitration scheme selection signal cpu_pri is valid, output a corresponding valid scheme selection signal m_cpu_pri; otherwise, output an invalid scheme selection signal m_cpu_pri.

[0071] In this embodiment of the application, if the arbitration scheme selection signal cpu_pri is valid, the corresponding valid scheme selection signal m_cpu_pri is output, specifically including: If the first signal cpu_pr0 / cpu_pr3 is valid, output the valid first scheme selection signal m_cpu_pr0 / m_cpu_pr3; if the second signal cpu_pr2 is valid, output the valid second scheme selection signal m_cpu_pr2; if the third signal cpu_pr1 is valid, output the valid third scheme selection signal m_cpu_pr1.

[0072] Arbitrator 602 is used for: If both the CPU access signal m_cpu_req and the LCD access signal m_lcd_req are valid: If the emergency flag signal m_urgent is valid or only the second scheme selection signal m_cpu_pr2 is valid, output a valid CPU response signal sel_cpu_req. If only the first scheme selection signal m_cpu_pr0 / m_cpu_pr3 is valid, the invalid CPU response signal sel_cpu_req is output. If only the third scheme selection signal m_cpu_pr1 is valid, the valid CPU response signal sel_cpu_req and the invalid CPU response signal sel_cpu_req are output alternately.

[0073] In this embodiment, after the CPU response signal sel_cpu_req becomes invalid, the first NOT gate N2 outputs a high-level signal. Since the LCD access signal m_lcd_req is valid, the first AND gate A3 outputs a high-level signal, thus generating the LCD response signal sel_lcd_req. At this time, the first OR gate O2 outputs the third access request nvm_req to the non-volatile memory 201. The address selector 502 selects lcd_addr as the final access address and sends it to the non-volatile memory 201. After the non-volatile memory 201 reads the data req_data according to the third access request nvm_req and lcd_addr, the data distributor 503 generates the lcd_ack signal and distributes the data req_data to the LCD controller 204.

[0074] After the CPU response signal sel_cpu_req is valid, the first NOT gate N2 outputs a low-level signal, therefore the first AND gate A3 outputs a low-level signal, meaning that no LCD response signal sel_cpu_req is generated. At this time, the first OR gate O2 outputs the third access request nvm_req to the non-volatile memory 201. The address selector 502 selects cpu_addr as the final access address and sends it to the non-volatile memory 201. After the non-volatile memory 201 reads the data req_data according to the third access request nvm_req and cpu_addr, the data allocator 503 generates the cpu_ack signal and allocates the data req_data to the CPU module 202.

[0075] In one exemplary embodiment of this application, such as Figure 5 As shown, the data distributor 503 includes a second NOT gate 5031, a second AND gate 5032, and a third AND gate 5033. The input of the second NOT gate 5031 is connected to the CPU response signal output. The first inputs of the second AND gate 5032 and the third AND gate 5033 are connected to the read completion flag (req_ack) output of the non-volatile memory 201. The second input of the second AND gate 5032 is connected to the CPU response signal output. The second input of the third AND gate 5033 is connected to the output of the second NOT gate 5031. The output of the second AND gate 5032 is connected to the second read signal input of the CPU module 202. The output of the third AND gate 5033 is connected to the first read signal input of the LCD controller 204.

[0076] In this embodiment, if the second AND gate 5032 outputs a high-level signal, indicating that the data distributor 503 outputs a second read signal cpu_ack, then the CPU module 202, upon receiving the second read signal cpu_ack, retrieves the data req_data output by the non-volatile memory 201. If the third AND gate 5033 outputs a high-level signal, indicating that the data distributor 503 outputs a first read signal lcd_ack, then the LCD controller 204, upon receiving the first read signal lcd_ack, retrieves the data req_data output by the non-volatile memory 201.

[0077] In an exemplary embodiment of this application, the data distributor 503 includes a second NOT gate 5031, a second AND gate 5032, and a third AND gate 5033. The input of the second NOT gate 5031 is connected to the LCD response signal output. The first inputs of the second AND gate 5032 and the third AND gate 5033 are connected to the read completion flag (req_ack) output of the non-volatile memory 201. The second input of the second AND gate 5032 is connected to the output of the second NOT gate 5031. The second input of the third AND gate 5033 is connected to the LCD response signal output. The output of the second AND gate 5032 is connected to the second read signal input of the CPU module 202. The output of the third AND gate 5033 is connected to the first read signal input of the LCD controller 204.

[0078] In this embodiment, if the second AND gate 5032 outputs a high-level signal, indicating that the data distributor 503 outputs a second read signal cpu_ack, then the CPU module 202, upon receiving the second read signal cpu_ack, retrieves the data req_data output by the non-volatile memory 201. If the third AND gate 5033 outputs a high-level signal, indicating that the data distributor 503 outputs a first read signal lcd_ack, then the LCD controller 204, upon receiving the first read signal lcd_ack, retrieves the data req_data output by the non-volatile memory 201.

[0079] In one exemplary embodiment of this application, the signal processor 601 is structured as follows: Figure 6As shown, the system includes a fourth AND gate 6011, a third NOT gate 6012, a second OR gate 6013, a clock gate G1, a first flip-flop 6014, a second flip-flop 6015, a third flip-flop 6016, and a fourth flip-flop 6017. The input of the fourth AND gate 6011 is connected to the output of the read completion flag and the read process busy flag; the input of the third NOT gate 6012 is connected to the read process busy flag output; the input of the second OR gate 6013 is connected to the outputs of the fourth AND gate 6011 and the third NOT gate 6012; and the input of the clock gate G1 is connected to the output of the second OR gate 6013 and the first clock signal clk. The clock inputs of the first flip-flop 6014, the second flip-flop 6015, the third flip-flop 6016, and the fourth flip-flop 6017 are connected to the output of the clock gate G1. The D terminal of the first flip-flop 6014 is connected to the second access request lcd_req, the D terminal of the second flip-flop 6015 is connected to the first access request cpu_req, the D terminal of the third flip-flop 6016 is connected to the emergency signal scene_urgent, and the input of the fourth flip-flop 6017 is connected to the arbitration scheme selection signal cpu_pri.

[0080] Clock gate G1 outputs a valid second clock signal m_clk when the output of the second OR gate 6013 is high. When the second clock signal m_clk is valid: if the second access request lcd_req is valid, the Q output of the first flip-flop 6014 outputs a high level, i.e., a valid LCD access signal m_lcd_req; otherwise, the Q output of the first flip-flop 6014 outputs a low level, i.e., an invalid LCD access signal m_lcd_req. If the first access request cpu_req is valid, the Q output of the second flip-flop 6015 outputs a high level, i.e., a valid CPU access signal m_cpu_req; otherwise, the Q output of the second flip-flop 6015 outputs a low level, i.e., an invalid CPU access signal m_cpu_req. `_cpu_req`; If the emergency signal `scene_urgent` is valid, the Q output of the third flip-flop 6016 is high, indicating a valid emergency flag signal `m_urgent`; otherwise, the Q output of the third flip-flop 6016 is low, indicating an invalid emergency flag signal `m_urgent`. If the arbitration scheme selection signal `cpu_pri` is valid, the Q output of the fourth flip-flop 6017 is high, indicating a valid scheme selection signal `m_cpu_pri`; otherwise, the Q output of the fourth flip-flop 6017 is low, indicating an invalid scheme selection signal `m_cpu_pri`. When the second clock signal `m_clk` is invalid, the first flip-flop 6014, the second flip-flop 6015, the third flip-flop 6016, and the fourth flip-flop 6017 retain their original signal output states.

[0081] In an exemplary embodiment of this application, the arbitration scheme selection signal cpu_pri includes a first signal cpu_pr0 / cpu_pr3 and a second signal cpu_pr2. The valid first signal cpu_pr0 / cpu_pr3 is a low-level signal, and the valid second signal cpu_pr2 is a high-level signal.

[0082] At this time, the scheme selection signal m_cpu_pri includes the first scheme selection signal (m_cpu_pr0 / m_cpu_pr3) and the second scheme selection signal m_cpu_pr2. If the first signal cpu_pr0 / cpu_pr3 is valid, that is, the D terminal of the fourth flip-flop 6017 is low, then the Q terminal of the fourth flip-flop 6017 outputs a low level, i.e., the valid first scheme selection signal m_cpu_pr0 / m_cpu_pr3. If the second signal cpu_pr2 is valid, that is, the D terminal of the fourth flip-flop 6017 is high, then the Q terminal of the fourth flip-flop 6017 outputs a high level, i.e., the valid second scheme selection signal m_cpu_pr2.

[0083] In an exemplary embodiment of this application, the arbitration scheme selection signal cpu_pri includes a first signal cpu_pr0 / cpu_pr3, a second signal cpu_pr2, and a third signal cpu_pr1. In this case, the fourth flip-flop 6017 of the signal processor 601 is a 2-bit flip-flop. The low-order D terminal of the fourth flip-flop 6017 is connected to the low-order bit of the binary code of the arbitration scheme selection signal, and the high-order D terminal of the fourth flip-flop 6017 is connected to the high-order bit of the binary code of the arbitration scheme selection signal.

[0084] The first valid signal cpu_pr0 / cpu_pr3 is 00 or 11, which means two high-level signals or two low-level signals. The second valid signal cpu_pr2 is 10, where 0 represents low level and 1 represents high level, that is, the high-level signal is high-level signal and the low-level signal is low-level signal. The third valid signal is 01, that is, the high-level signal is low-level signal and the low-level signal is high-level signal.

[0085] When the second clock signal m_clk is valid: If the two D terminals of the fourth flip-flop 6017 input 00 / 11, then its Q terminal outputs 00 / 11. That is, if the first signals cpu_pr0 / cpu_pr3 are valid, meaning both D terminals of the fourth flip-flop 6017 input a low or high level, then both Q terminals of the fourth flip-flop 6017 output a low or high level, i.e., the valid first scheme selection signal (m_cpu_pr0 / m_cpu_pr3). If the D terminal of the fourth flip-flop 6017 inputs 01, then its Q terminal outputs 01. That is, if the third signal cpu_pr1 is valid, i.e., the fourth flip-flop... If the lower bit of the two D terminals of the fourth flip-flop 6017 is high and the higher bit is low, then the lower bit of the two Q terminals of the fourth flip-flop 6017 will output a high level and the higher bit will output a low level, which is the valid third scheme selection signal m_cpu_pr1. If the D terminal of the fourth flip-flop 6017 is 10, then its Q terminal will output 10. If the second signal cpu_pr2 is valid, that is, if the lower bit of the two D terminals of the fourth flip-flop 6017 is low and the higher bit is high, then the lower bit of the fourth flip-flop 6017 will output a low level and the higher bit will output a high level, which is the valid second scheme selection signal m_cpu_pr2.

[0086] In an exemplary embodiment of this application, the scheme selection signal m_cpu_pri includes a first scheme selection signal (m_cpu_pr0 / m_cpu_pr3) and a second scheme selection signal m_cpu_pr2. The valid first scheme selection signal is a low-level signal, and the valid second scheme selection signal is a high-level signal.

[0087] The structure of the aforementioned request arbitrator 602 is as follows: Figure 7As shown, the array includes a fifth AND gate 6021, a third OR gate 6022, a fourth NOT gate 6023, a sixth AND gate 6024, a seventh AND gate 6025, an eighth AND gate 6026, and a fourth OR gate 6027. The input of the fifth AND gate 6021 is connected to the LCD access signal output (Q terminal of the first flip-flop 6014) and the CPU access signal output (Q terminal of the second flip-flop 6015) of the signal processor 601. The input of the third OR gate 6022 is connected to the emergency flag signal output (Q terminal of the third flip-flop 6016) and the scheme selection signal output (Q terminal of the fourth flip-flop 6017) of the signal processor 601. The input of the fourth NOT gate 6023 is connected to the output of the fifth AND gate 6021, and the input of the sixth AND gate 6024 is connected to... The output of the fourth NOT gate 6023 is connected to the CPU access signal output of the signal processor 601 (Q terminal of the second flip-flop 6015). The input of the seventh AND gate 6025 is connected to the output of the third OR gate 6022 and the CPU access signal output of the signal processor 601 (Q terminal of the second flip-flop 6015). The input of the eighth AND gate 6026 is connected to the output of the fifth AND gate 6021 and the output of the seventh AND gate 6025. The input of the fourth OR gate 6027 is connected to the output of the sixth AND gate 6024 and the output of the eighth AND gate 6026.

[0088] In this embodiment, if both the LCD access signal m_lcd_req and the CPU access signal m_cpu_req are valid, the fifth AND gate 6021 outputs a high level and the sixth AND gate 6024 outputs a low level. If the emergency flag signal m_urgent or the scheme selection signal m_cpu_pri is valid (i.e., the scheme selection signal m_cpu_pri is in a high-level state), the eighth AND gate 6026 outputs a high-level signal, and subsequently, the fourth OR gate 6027 outputs a high-level signal, which is the valid CPU response signal sel_cpu_req. If both the emergency flag signal m_urgent and the scheme selection signal m_cpu_pri are invalid (i.e., the scheme selection signal m_cpu_pri is in a low-level state), the eighth AND gate 6026 outputs a low-level signal, and subsequently, the fourth OR gate 6027 outputs a low-level signal, which is the invalid CPU response signal sel_cpu_req.

[0089] If the CPU access signal m_cpu_req is valid and the LCD access signal m_lcd_req is invalid, then the sixth AND gate 6024 outputs a high-level signal, which in turn outputs a high-level signal from the fourth OR gate 6027, resulting in a valid CPU response signal sel_cpu_req. If the CPU access signal m_cpu_req is invalid but the LCD access signal m_lcd_req is valid, then the sixth AND gate 6024 outputs both a high and low-level signal, which in turn outputs a low-level signal from the fourth OR gate 6027, resulting in an invalid CPU response signal sel_cpu_req.

[0090] In one exemplary embodiment of this application, the scheme selection signal m_cpu_pri includes a first scheme selection signal (m_cpu_pr0 / m_cpu_pr3), a second scheme selection signal m_cpu_pr2, and a third scheme selection signal m_cpu_pr1.

[0091] At this time, the aforementioned request arbitrator 602 includes a first control module 701 and a second control module 702. The input terminal of the first control module 701 is connected to the CPU access signal output terminal (Q terminal of the second flip-flop 6015), the emergency flag signal output terminal (Q terminal of the third flip-flop 6016), the scheme selection signal output terminal (Q terminal of the fourth flip-flop 6017), and the read completion flag (req_ack) output terminal of the signal processor 601. The input terminal of the second control module 702 is connected to the output terminal of the first control module 701 (output terminal of OR gate O6) and the LCD access signal output terminal (Q terminal of the first flip-flop 6014), the CPU access signal output terminal (Q terminal of the second flip-flop 6015), the emergency flag signal output terminal (Q terminal of the third flip-flop 6016), and the scheme selection signal output terminal (Q terminal of the fourth flip-flop 6017) of the signal processor 601. The output terminal of the second control module 702 is connected to the input terminal of the first NOT gate N2.

[0092] In this embodiment of the application, the first control module 701 is used for: The control signal acc_toggl is toggled whenever the CPU access signal m_cpu_req and the LCD access signal m_lcd_req occur simultaneously. If only the CPU access signal m_cpu_req, the LCD access signal m_lcd_req, and the third scheme selection signal are valid: If the control signal acc_toggle is in the first state (low level), the third response process is executed: Output a valid first control signal and control the first counter to count the number of consecutive responses to the first access request cpu_req starting from zero. When the count value of the first counter reaches n, output an invalid first control signal and control the second counter to count the number of consecutive responses to the second access request lcd_req starting from zero. When the count value of the second counter reaches m, return to execute the output of the valid first control signal and subsequent steps until the access conflict is eliminated.

[0093] If the control signal acc_toggle is in the second state (high level), the fourth response process is executed: Output an invalid first control signal and control the second counter to count the number of consecutive responses to the second access request lcd_req starting from zero. When the count value of the second counter reaches m, output a valid first control signal and control the first counter to count the number of consecutive responses to the first access request cpu_req starting from zero. When the count value of the first counter reaches n, return to output an invalid first control signal and continue the subsequent steps until the access conflict is resolved.

[0094] The second control module 702 is used for: If both the CPU access signal m_cpu_req and the LCD access signal m_lcd_req are valid: If only the first scheme selects the signal as valid, or only the third scheme selects the signal as valid, output an invalid CPU response signal sel_cpu_req; If the emergency flag signal m_urgent is valid or only the second scheme selection signal is valid, output a valid CPU response signal sel_cpu_req; If only the first control signal and the third scheme selection signal are valid, output a valid CPU response signal sel_cpu_req.

[0095] This application provides an exemplary embodiment, such as... Figure 8As shown, the second control module 702 includes a first comparator U2, a ninth AND gate A4, a fifth NOT gate N4, a tenth AND gate A8, an eleventh AND gate A9, a twelfth AND gate A10, a thirteenth AND gate A11, a fourteenth AND gate A12, a fifteenth AND gate A13, a fifth NOT gate N4, a sixth NOT gate N5, a fifth OR gate O3, a sixth OR gate O4, and a seventh OR gate O5. Among them, the input of the ninth AND gate A4 is connected to the LCD access signal output (Q terminal of the first flip-flop 6014) and the CPU access signal output (Q terminal of the second flip-flop 6015) of the signal processor 601; the input of the fifth NOT gate N4 is connected to the output of the ninth AND gate A4; the input of the tenth AND gate A8 is connected to the output of the fifth NOT gate N4 and the CPU access signal output; the input of the fourteenth AND gate A12 is connected to the CPU access signal output and the second output of the first comparator U2 (outputting a high level when m_cpu_pri=2); the input of the fifteenth AND gate A13 is connected to the output of the first control module 701 and the first output of the first comparator U2 (outputting a high level when m_cpu_pri=1); and the input of the first comparator U2 is connected to the scheme selection signal output of the signal processor 601 (the... The input of the four flip-flops 6017 (Q terminal) is connected to the output of the fourteenth AND gate A12 and the fifteenth AND gate A13. The input of the sixth NOT gate N5 is connected to the emergency flag signal output of the signal processor 601. The input of the thirteenth AND gate A11 is connected to the output of the seventh OR gate O5 and the sixth NOT gate N5. The input of the twelfth AND gate A10 is connected to the CPU access signal output and the emergency flag signal output. The input of the sixth OR gate O4 is connected to the output of the twelfth AND gate A10 and the thirteenth AND gate A11. The input of the eleventh AND gate A9 is connected to the output of the ninth AND gate A4 and the sixth OR gate O4. The input of the fifth OR gate O3 is connected to the output of the tenth AND gate A8 and the eleventh AND gate A9. The output of the fifth OR gate O3 is connected to the input of the first NOT gate N2.

[0096] In this embodiment, the first comparator U2 is used to compare the low-order and high-order bits of the input binary signal. If the low-order and high-order bits of the binary signal are the same, both the first and second output terminals of the first comparator U2 output low-level signals. If the low-order bit value of the binary signal is greater than the high-order bit value (low-order bit outputs high-level, high-order bit outputs low-level), the first output terminal of the first comparator U2 outputs a high-level signal (m_cpu_pri=1). If the low-order bit value of the binary signal is less than the high-order bit value (low-order bit outputs low-level, high-order bit outputs high-level), the second output terminal of the first comparator U2 outputs a high-level signal (m_cpu_pri=2).

[0097] This application provides an exemplary embodiment, such as... Figure 8As shown, the first control module 701 includes a flip module U1, a sixteenth AND gate A14, a seventeenth AND gate A15, an eighteenth AND gate A16, a nineteenth AND gate A18, a twentieth AND gate A19, a twenty-first AND gate A20, a twenty-second AND gate A21, a twenty-third AND gate A22, a twenty-fourth AND gate A23, a twenty-fifth AND gate A24, a twenty-sixth AND gate A25, a twenty-seventh AND gate A26, a twenty-eighth AND gate A27, a twenty-ninth AND gate A28, an AND gate module A17, an eighth OR gate O6, a ninth OR gate O7, a tenth OR gate O8, an eleventh OR gate O9, a twelfth OR gate O10, a thirteenth OR gate O11, a fourteenth OR gate O12, a seventh NOT gate N7, an eighth NOT gate N8, a ninth NOT gate N9, a tenth NOT gate N10, a second comparator U3, and a third comparator U4. Specifically, the input of the sixteenth AND gate A14 is connected to the CPU request signal output of the signal processor 601 and the output of the third comparator U4; the input of the seventeenth AND gate A15 is connected to the output of the flip module U1 and the output of the sixteenth AND gate A14; the input of the flip module U1 is connected to the output of the ninth AND gate A4; the input of the eighth NOT gate N8 is connected to the output of the second comparator U3; the input of the nineteenth AND gate A18 is connected to the CPU request signal output of the signal processor 601 and the output of the eighth NOT gate N8; the input of the seventh NOT gate N7 is connected to the output of the flip module U1; the input of the eighteenth AND gate A16 is connected to the output of the seventh NOT gate N7 and the output of the nineteenth AND gate A18; the input of the eighth OR gate O6 is connected to the output of the seventeenth AND gate A15 and the eighteenth AND gate A16; and the output of the eighth OR gate O6 is connected to the input of the fifteenth AND gate A13.

[0098] The input of the twentieth AND gate A19 is connected to the output of the ninth NOT gate N9 and the output of the flip module U1. The input of the ninth NOT gate N9 is connected to the output of the third comparator U4. The input of the twenty-second AND gate A21 is connected to the output of the second comparator U3 and the output of the seventh NOT gate N7. The input of the tenth OR gate O8 is connected to the output of the twentieth AND gate A19 and the output of the twenty-second AND gate A21. The input of the twenty-sixth AND gate A25 is connected to the output of the tenth OR gate O8 and the output of the AND gate module A17. The input of the AND gate module A17 is connected to the output of the ninth AND gate A4, the output of the sixth NOT gate N5, the first scheme selection signal output of the signal processor 601 (the low-order Q of the fourth flip-flop 6017), and the read completion flag output of the non-volatile memory 201. The output of the 26th AND gate A25 is connected to the INC terminal of the second counter U5. The output of the second comparator U5 is connected to the input of the third comparator U4. The CLR terminal of the second comparator U5 is connected to the output of the 13th OR gate O11. The input of the 13th OR gate O11 is connected to the output of the fifth NOT gate N4 and the output of the 11th OR gate O9. The input of the 11th OR gate O9 is connected to the output of the 24th AND gate A23 and the output of the 25th AND gate A24. The input of the 24th AND gate A23 is connected to the output of the toggle module U1 and the output of the second comparator U3. The input of the 25th AND gate A24 is connected to the output of the seventh NOT gate N7 and the output of the third comparator U4.

[0099] In this embodiment, AND gate module A17 is used to perform AND operation on the input signal. If the read completion flag output terminal outputs a valid read completion flag (req_ack), the ninth AND gate A4 outputs a high level, the first output terminal of the first comparator U2 outputs a high level, and the emergency flag signal output terminal outputs an invalid emergency flag signal, AND gate module A17 outputs a high level signal; otherwise, AND gate module A17 outputs a low level signal.

[0100] When AND gate A25 outputs a high level, the count of the second counter U5 is incremented by 1. When OR gate O11 outputs a high level, the count of the second counter U5 is cleared. The third comparator U4 compares the count value m_counter(m_cnt) of the second counter U5 with the preset value m. If the count value of the second counter U5 reaches the second preset value m (m_cnt=m), the third comparator U4 outputs a high-level signal; otherwise, it outputs a low-level signal.

[0101] The input of the twenty-first AND gate A20 is connected to the output of the seventh NOT gate N7 and the tenth NOT gate N10. The input of the tenth NOT gate N10 is connected to the output of the second comparator U3. The input of the twenty-third AND gate A22 is connected to the output of the flip module U1 and the output of the third comparator U4. The input of the ninth OR gate O7 is connected to the output of the twenty-first AND gate A20 and the output of the twenty-third AND gate A22. The input of the twenty-seventh AND gate A26 is connected to the output of the ninth OR gate O7 and the output of the AND gate module A17. The output of AND gate A26 (27th AND gate) is connected to the INC terminal of the first counter U6. The output of the first counter U6 is connected to the input of the second comparator U3. The CLR terminal of the first counter U6 is connected to the output of the fourteenth OR gate O12. The input of the fourteenth OR gate O12 is connected to the output of the fifth NOT gate N4 and the output of the twelfth OR gate O10. The input of the twelfth OR gate O10 is connected to the output of AND gate A27 (28th AND gate) and the output of AND gate A28 (29th AND gate). The input of AND gate A27 (28th AND gate) is connected to the output of the seventh NOT gate N7 and the output of the third comparator U4. The input of AND gate A28 (29th AND gate) is connected to the output of the toggle module U1 and the output of the second comparator U3.

[0102] In this embodiment, when the twenty-seventh AND gate A26 outputs a high level, the count of the first counter U6 is incremented by 1. When the fourteenth OR gate O12 outputs a high level, the count of the first counter U6 is cleared to zero. The second comparator U3 compares the count value n_counter(n_cnt) of the first counter U6 with a preset value n. If the count value of the first counter U6 reaches the first preset value n (n_cnt=n), the second comparator U3 outputs a high-level signal; otherwise, it outputs a low-level signal.

[0103] The toggle module U1 controls the acc_toggle signal when the ninth AND gate A4 outputs a high level. Specifically, the acc_toggle control signal toggles once on the rising edge of the high-level signal output by the ninth AND gate A4. Specifically, when handling access conflicts using the third scheme, if the acc_toggle control signal is in the first state, the first counter U6 counts, responding to the first access request cpu_req, until the first comparator U3 outputs a high-level signal. If the acc_toggle control signal is in the second state, the second counter U5 counts, responding to the second access request lcd_req, until the second comparator U4 outputs a high-level signal. The toggle module U1 can be implemented using an inverter.

[0104] In one exemplary embodiment of this application, such as Figure 8As shown, the data distributor 503 includes a 30th AND gate A1 and a 31st AND gate A2. The first input of the 30th AND gate A1 and the first input of the 31st AND gate A2 are connected to the read completion flag (req_ack) output of the non-volatile memory 201. The second input of the 30th AND gate A1 is connected to the CPU response signal output. The second input of the 31st AND gate A2 is connected to the LCD response signal output. The output of the 30th AND gate A1 is connected to the second read signal output of the CPU module 202. The output of the 12th AND gate A2 is connected to the first read signal output of the LCD controller 204.

[0105] In this embodiment, if the 30th AND gate A1 outputs a high-level signal, indicating that the data distributor 503 outputs a second read signal cpu_ack, then the CPU module 202, upon receiving the cpu_ack signal, retrieves the data req_data output by the non-volatile memory 201. If the 31st AND gate A2 outputs a high-level signal, indicating that the data distributor 503 outputs a first read signal lcd_ack, then the LCD controller 204, upon receiving the lcd_ack signal, retrieves the data req_data output by the non-volatile memory 201.

[0106] In another exemplary embodiment of this application, the non-volatile memory 201 internally includes memory chips and an access controller. The access controller reads data within the memory chip based on the received access request nvm_req and address signal req_addrs, and issues a read completion flag req_ack and a read busy flag acc_busy. The access request nvm_req is output by the request arbitration module 501 of the arbitration controller 301, and the address signal req_addrs is output by the address selector 502 of the arbitration controller 301.

[0107] In another exemplary embodiment of this application, the non-volatile memory 201 uses a P25Q16SH NOR FLASH chip, which supports SPI interface communication 4-wire mode read access.

[0108] In another exemplary embodiment of this application, the LCD display module 101 is model N177-1216TBWPG26-H14, and includes a display driver chip and a TFT liquid crystal screen. The display driver chip is model ST7735P3, with a maximum resolution of 128*160, and supports SPI interface communication.

[0109] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0110] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An intelligent power supply control system, characterized in that, The intelligent power control system includes an LCD display module (101) and a power management MCU chip (102). The power management MCU chip (102) integrates a non-volatile memory (201), a CPU module (202), a PMU module (203), an LCD controller (204), and a bandwidth arbiter (205), wherein: The bandwidth arbiter (205) is connected to the non-volatile memory (201), the CPU module (202), and the LCD controller (204). The CPU module (202) is connected to the PMU module (203) and the LCD controller (204). The LCD controller (204) is communicatively connected to the LCD display module (101). The non-volatile memory (201) stores color screen display data and instruction code to be executed by the CPU module. The bandwidth arbiter (205) configures the priority and bandwidth of access requests when an access conflict occurs.

2. The intelligent power control system according to claim 1, characterized in that, The bandwidth arbitrator (205) includes an arbitration controller (301), which includes a request arbitration module (501), an address selector (502), and a data distributor (503), wherein: The input terminal of the request arbitration module (501) is connected to the first access request output terminal, the second access request output terminal, the arbitration scheme selection signal output terminal, the emergency signal output terminal, the busy reading process flag output terminal, and the reading completion flag output terminal; the access request output terminal of the request arbitration module (501) is connected to the access request input terminal of the non-volatile memory (201); the request arbitration module (501) configures the priority and bandwidth of the access request when an access conflict occurs; The input terminal of the address selector (502) is connected to the instruction code storage address output terminal of the CPU module (202), the display memory data storage address output terminal of the LCD controller (204), and the device selection signal output terminal of the request arbitration module (501); the output terminal of the address selector (502) is connected to the access address input terminal of the non-volatile memory (201); the address selector (502) configures the access address when an access conflict occurs; The input terminal of the data distributor (503) is connected to the device selection signal output terminal, the data output terminal of the non-volatile memory (201), and the read completion flag output terminal. The data output terminal of the data distributor (503) is connected to the instruction code input terminal and the video memory data input terminal. The read signal output terminal of the data distributor (503) is connected to the read signal input terminal of the CPU module (202) and the read signal input terminal of the LCD controller (204). The data distributor (503) allocates the data to be read by the selected device when an access conflict occurs.

3. The intelligent power control system according to claim 2, characterized in that, The arbitration request module (501) includes a signal processor (601), an arbitrator (602), a first NOT gate (N2), a first AND gate (A3), and a first OR gate (O2), wherein: The input terminal of the signal processor (601) is connected to the arbitration scheme selection signal output terminal, the first access request output terminal, the second access request output terminal, the emergency signal output terminal, the busy reading process flag output terminal, and the reading completion flag output terminal. The output terminal of the signal processor (601) is connected to the input terminal of the request arbitrator (602). The input terminal of the first NOT gate (N2) is connected to the CPU response signal output terminal of the request arbitrator (602). The input terminal of the first AND gate (A3) is connected to the output terminal of the first NOT gate (N2) and the signal processor (601). The LCD access signal output terminal of the first OR gate (O2) is connected to the output terminal of the first AND gate (A3) and the CPU response signal output terminal. The output terminal of the first OR gate (O2) is connected to the access request input terminal of the non-volatile memory (201). The signal processor (601) latches the access request, arbitration scheme selection signal and emergency signal when the non-volatile memory (201) is idle. The request arbitrator (602) configures the priority and bandwidth of the access request when an access conflict occurs and the non-volatile memory (201) is idle.

4. The intelligent power supply control system according to claim 2, characterized in that, The data distributor (503) includes a second NOT gate (5031), a second AND gate (5032), and a third AND gate (5033), wherein: The input of the second NOT gate (5031) is connected to the CPU response signal output, the first input of the second AND gate (5032) and the first input of the third AND gate (5033) are connected to the read completion flag output of the non-volatile memory (201), the second input of the second AND gate (5032) is connected to the CPU response signal output, and the second input of the third AND gate (5033) is connected to the output of the second NOT gate (5031); or, the input of the second NOT gate (5031) is connected to the LCD response signal output, the first input of the second AND gate (5032) and the first input of the third AND gate (5033) are connected to the read completion flag output of the non-volatile memory (201), the second input of the third AND gate (5033) is connected to the LCD response signal output, and the second input of the second AND gate (5032) is connected to the output of the second NOT gate (5031); The output of the second AND gate (5032) is connected to the second read signal input of the CPU module (202), and the output of the third AND gate (5033) is connected to the first read signal input of the LCD controller (204).

5. The intelligent power supply control system according to claim 3, characterized in that, The signal processor (601) includes a fourth AND gate (6011), a third NOT gate (6012), a second OR gate (6013), a clock gate (G1), a first flip-flop (6014), a second flip-flop (6015), a third flip-flop (6016), and a fourth flip-flop (6017), wherein: The input of the fourth AND gate (6011) is connected to the output of the read completion flag and the output of the read process busy flag. The input of the third NOT gate (6012) is connected to the output of the read process busy flag. The input of the second OR gate (6013) is connected to the output of the fourth AND gate (6011) and the output of the third NOT gate (6012). The input of the clock gate (G1) is connected to the output of the second OR gate (6013) and the first clock signal clk. The clock inputs of the first flip-flop (6014), the second flip-flop (6015), the third flip-flop (6016), and the fourth flip-flop (6017) are connected to the output of the clock gate (G1). The D terminal of the first flip-flop (6014) is connected to the second access request. The D terminal of the second flip-flop (6015) is connected to the first access request. The D terminal of the third flip-flop (6016) is connected to the emergency signal. The input of the fourth flip-flop (6017) is connected to the arbitration scheme selection signal.

6. The intelligent power control system according to claim 5, characterized in that, The request arbitrator (602) includes a fifth AND gate (6021), a third OR gate (6022), a fourth NOT gate (6023), a sixth AND gate (6024), a seventh AND gate (6025), an eighth AND gate (6026), and a fourth OR gate (6027), wherein: The input of the fifth AND gate (6021) is connected to the Q terminal of the first flip-flop (6014) and the Q terminal of the second flip-flop (6015). The input of the third OR gate (6022) is connected to the Q terminal of the third flip-flop (6016) and the Q terminal of the fourth flip-flop (6017). The input of the fourth NOT gate (6023) is connected to the output of the fifth AND gate (6021). The input of the sixth AND gate (6024) is connected to the output of the fourth NOT gate (6023) and the Q terminal of the second flip-flop (6015). The input of the seventh AND gate (6025) is connected to the output of the third OR gate (6022) and the Q terminal of the second flip-flop (6015). The input of the eighth AND gate (6026) is connected to the output of the fifth AND gate (6021) and the output of the seventh AND gate (6025). The input of the fourth OR gate (6027) is connected to the output of the sixth AND gate (6024) and the output of the eighth AND gate (6026).

7. The intelligent power control system according to claim 5, characterized in that, The fourth flip-flop (6017) is a 2-bit flip-flop. The low-order D terminal of the fourth flip-flop (6017) is connected to represent the low-order bit of the binary code of the arbitration scheme selection signal, and the high-order D terminal of the fourth flip-flop (6017) is connected to represent the high-order bit of the binary code of the arbitration scheme selection signal.

8. The intelligent power control system according to claim 7, characterized in that, The request arbitrator (602) includes a first control module (701) and a second control module (702), wherein: The input terminal of the first control module (701) is connected to the Q terminal of the first flip-flop (6014), the Q terminal of the second flip-flop (6015), the Q terminal of the third flip-flop (6016), the Q terminal of the fourth flip-flop (6017), and the output terminal of the read completion flag; the input terminal of the second control module (702) is connected to the output terminal of the first control module (701) and the Q terminals of the first flip-flop (6014), the second flip-flop (6015), the third flip-flop (6016), and the fourth flip-flop (6017); the output terminal of the second control module (702) is connected to the input terminal of the first NOT gate (N2).

9. The intelligent power control system according to claim 8, characterized in that, The second control module (702) includes a first comparator (U2), a ninth AND gate (A4), a fifth NOT gate (N4), a tenth AND gate (A8), an eleventh AND gate (A9), a twelfth AND gate (A10), a thirteenth AND gate (A11), a fourteenth AND gate (A12), a fifteenth AND gate (A13), a fifth NOT gate (N4), a sixth NOT gate (N5), a fifth OR gate (O3), a sixth OR gate (O4), and a seventh OR gate (O5), wherein: The input of the ninth AND gate (A4) is connected to the Q terminal of the first flip-flop (6014) and the Q terminal of the second flip-flop (6015). The input of the fifth NOT gate (N4) is connected to the output of the ninth AND gate (A4). The input of the tenth AND gate (A8) is connected to the output of the fifth NOT gate (N4) and the CPU access signal output. The input of the fourteenth AND gate (A12) is connected to the CPU access signal output and the second output of the first comparator (U2). The input of the fifteenth AND gate (A13) is connected to the output of the first control module (701) and the first output of the first comparator (U2). The input of the first comparator (U2) is connected to the Q terminal of the fourth flip-flop (6017). The input of the seventh OR gate (O5) is connected to the output of the fourteenth AND gate (A12) and the fifteenth AND gate (A13). The output of the sixth NOT gate (N5) is connected to the Q terminal of the third flip-flop (6016). The input of the thirteenth AND gate (A11) is connected to the output of the seventh OR gate (O5) and the output of the sixth NOT gate (N5). The input of the twelfth AND gate (A10) is connected to the CPU access signal output and the Q terminal of the third flip-flop (6016). The input of the sixth OR gate (O4) is connected to the output of the twelfth AND gate (A10) and the output of the thirteenth AND gate (A11). The input of the eleventh AND gate (A9) is connected to the output of the ninth AND gate (A4) and the output of the sixth OR gate (O4). The input of the fifth OR gate (O3) is connected to the output of the tenth AND gate (A8) and the output of the eleventh AND gate (A9). The output of the fifth OR gate (O3) is connected to the input of the first NOT gate (N2).

10. The intelligent power supply control system according to claim 2, characterized in that, The data distributor (503) includes a 30th AND gate (A1) and a 31st AND gate (A2), wherein: The first input of the 30th AND gate (A1) and the first input of the 31st AND gate (A2) are connected to the read completion flag output of the non-volatile memory (201). The second input of the 30th AND gate (A1) is connected to the CPU response signal output. The second input of the 31st AND gate (A2) is connected to the LCD response signal output. The output of the 12th AND gate (A2) is connected to the first read signal output of the LCD controller (204). The output of the 30th AND gate (A1) is connected to the second read signal output of the CPU module (202).

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