Driving circuit and display module

Abstract

The utility model discloses an embodiment of driving circuit and display module, this driving circuit includes power module and level conversion module, and power module is connected with level conversion module, still includes output control module, and output control module is connected with power module and level conversion module, and output control module responds the first voltage that level conversion module's output end output respectively outputs common voltage and power voltage. The scheme can realize only has in the first voltage reaches steady state, and common voltage and power voltage will output only, thereby makes the source electrode drive signal and common voltage will be input to the in -plane of display panel after driving transistor completely closes, avoids appearing the pressure difference between pixel electrode and common electrode when driving transistor is not completely closed, and then avoids appearing the problem of starting flash white, is favorable to improving display effect.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and in particular to a driving circuit and a display module. Background Technology

[0002] With the rapid development of display technology, liquid crystal displays (LCDs) have been widely used in various information, communication and consumer products due to their advantages such as small size, high image quality, no radiation and low driving voltage.

[0003] In existing display products, there is a white flickering phenomenon during the power-on process, which affects the display effect. Utility Model Content

[0004] This utility model provides a driving circuit and a display module to solve the flickering white problem that occurs during power-on and improve the display effect.

[0005] According to one aspect of the present invention, a driving circuit is provided, including a power supply module and a level conversion module, wherein the power supply module is connected to the level conversion module, and the circuit further includes an output control module, wherein the output control module is connected to the power supply module and the level conversion module, and the output control module outputs a common voltage and a power supply voltage respectively in response to a first voltage output by the output terminal of the level conversion module.

[0006] Optionally, the output control module includes a first input unit, a second input unit, a switch unit, and an output unit;

[0007] The input terminal of the first input unit is connected to the first voltage signal terminal, the output terminal of the first input unit is connected to the control terminal of the switch unit, the input terminal of the second input unit is connected to the second voltage signal terminal, the output terminal of the second input unit and the output terminal of the switch unit are connected to the first node, and the input terminal of the switch unit is connected to the output terminal of the level conversion module.

[0008] The control terminal of the output unit is connected to the first node, the first input terminal of the output unit is connected to the third voltage signal terminal, the second input terminal of the output unit is connected to the second voltage signal terminal, and the output unit responds to the voltage selection of the first node to output the common voltage from its first output terminal and output the first power supply voltage from its second output terminal.

[0009] Optionally, the absolute value of the difference between the second voltage output by the first input unit and the first voltage is greater than the threshold voltage of the switching unit.

[0010] Optionally, the first power supply voltage is greater than the common voltage;

[0011] The voltage output by the second input unit is the voltage that turns off the output unit.

[0012] Optionally, the switching unit includes a first transistor, the gate of the first transistor is connected to the output terminal of the first input unit, the first electrode of the first transistor is connected to the first node, and the second electrode of the first transistor is connected to the output terminal of the level conversion module.

[0013] Wherein, the first voltage is a negative voltage, and the first transistor is an N-type transistor.

[0014] Optionally, the first input unit includes a first operational amplifier and a voltage divider unit. The first input terminal of the first operational amplifier is connected to the first voltage signal terminal, the second input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is connected to the control terminal of the switching unit via the voltage divider unit.

[0015] The voltage divider unit includes a first resistor and a second resistor. The first end of the first resistor is connected to the output terminal of the first operational amplifier, the second end of the first resistor is connected to the control terminal of the switching unit, the first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is grounded.

[0016] Optionally, the second input unit includes a second operational amplifier, a diode, and a third resistor. The first input terminal of the second operational amplifier is connected to the second voltage signal terminal, the second input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier, the output terminal of the second operational amplifier is connected to the first terminal of the diode, the second terminal of the diode is connected to the first terminal of the third resistor, and the second terminal of the third resistor is connected to the first node.

[0017] Optionally, the output unit includes a first subunit and a second subunit. The control terminals of the first subunit and the second subunit are both connected to the first node. The input terminal of the first subunit is connected to the third voltage signal terminal. The output terminal of the first subunit outputs the common voltage. The input terminal of the second subunit is connected to the first voltage signal terminal. The output terminal of the second subunit outputs the first power supply voltage.

[0018] The first sub-unit includes a second transistor and a fourth resistor. The gate of the second transistor is connected to the first node, the first terminal of the second transistor is connected to the third voltage signal terminal, the second terminal of the second transistor serves as the output terminal of the first sub-unit, the first terminal of the fourth resistor is connected to the second terminal of the second transistor, and the second terminal of the fourth resistor is grounded.

[0019] The second sub-unit includes a third transistor and a fifth resistor. The gate of the third transistor is connected to the first node, the first terminal of the third transistor is connected to the first voltage signal terminal, the second terminal of the third transistor serves as the output terminal of the second sub-unit, the first terminal of the fifth resistor is connected to the second terminal of the third transistor, and the second terminal of the fifth resistor is grounded.

[0020] The second transistor and the third transistor have the same channel type.

[0021] Optionally, the output unit further includes a third subunit, the control terminal of the third subunit is connected to the first node, the input terminal of the third subunit is connected to a fourth voltage signal terminal, and the output terminal of the third subunit outputs a second power supply voltage; the second power supply voltage is less than the first power supply voltage.

[0022] The third subunit includes a fourth transistor and a sixth resistor. The gate of the fourth transistor is connected to the first node, the first terminal of the fourth transistor is connected to the fourth voltage signal terminal, the second terminal of the fourth transistor serves as the output terminal of the third subunit, the first terminal of the sixth resistor is connected to the second terminal of the fourth transistor, and the second terminal of the sixth resistor is grounded.

[0023] The fourth transistor, the second transistor, and the third transistor have the same channel type.

[0024] According to another aspect of the present invention, a display module is provided, the display module including the driving circuit provided in any embodiment of the present invention.

[0025] The technical solution provided by this utility model embodiment, by setting an output control module, uses the first voltage output by the level conversion module in response to the output of the output control module to control the output of the common voltage and the power supply voltage, so that the common voltage and the power supply voltage will only be output after the first voltage reaches a steady state. This ensures that the source drive signal and the common voltage are only input to the display panel after the drive transistor is completely turned off, avoiding the voltage difference between the pixel electrode and the common electrode when the drive transistor is not completely turned off, thereby avoiding the problem of white flickering when the power is turned on and improving the display effect.

[0026] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram of a driving circuit provided for related technologies;

[0029] Figure 2 For the corresponding Figure 1 A schematic diagram of the voltage output waveform;

[0030] Figure 3 A schematic diagram of a driving circuit provided in an embodiment of this utility model;

[0031] Figure 4 A schematic diagram of the structure of an output control module provided in an embodiment of this utility model;

[0032] Figure 5 A voltage waveform diagram provided for an embodiment of this utility model;

[0033] Figure 6 A schematic diagram of another output control module provided in an embodiment of this utility model;

[0034] Figure 7 This is a schematic diagram of another output control module provided in an embodiment of the present utility model. Detailed Implementation

[0035] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0036] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0037] Existing display modules include a display panel and a driving circuit. The display panel includes an array substrate, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate. The array substrate includes scan lines and data lines. The scan lines and data lines intersect to form multiple sub-pixel regions. Driving transistors are disposed in the sub-pixel regions. The gate of the driving transistor is connected to the scan line, the first electrode of the driving transistor is connected to the data line, and the second electrode of the driving transistor is connected to the pixel electrode. The scanning lines can control the on / off state of the driving transistors, thereby controlling whether the data line signal is written to the pixel electrode. The driving circuit provides signals to the scan lines and data lines to control the operation of the display panel. Figure 1 A schematic diagram of a driving circuit is provided for related technologies, for reference. Figure 1 The driving circuit includes a power supply module 10, a level conversion module 20, a source drive module 40, and a gate drive module 50. The gate drive module 50 is connected to the output terminal of the level conversion module 20, and the source drive module 40 is connected to the power supply module 10 to receive the power supply voltage, such as the first power supply voltage AVDD-OUT. The source drive module 40 is used to output the source drive signal SOUT, and the gate drive module is used to generate the gate drive signal GOUT.

[0038] The power supply module 10 is used to output a first reference voltage AVDD, a second reference voltage VCOM, a high level VGH, and a low level VGL according to the input signal VINHE. The level conversion module 20 is used to generate a low level VGL (i.e., the first voltage V1) and a high level VGH of the gate drive signal GOUT according to the signals output by the power supply module 10 and the timing controller (not shown in the figure), and provide them to the gate drive module 50. The gate drive module 50 outputs the gate drive signal GOUT under the control of the signal output by the level conversion module 20.

[0039] When the scan line applies a high level (VGH) gate drive signal GOUT to the gate of the driving transistor, the driving transistor is turned on. The source drive signal SOUT charges the pixel electrode through the driving transistor, and the liquid crystal molecules in the display panel are deflected under the influence of the electric field, thus realizing image display. When the scan line applies a low level (VGL) gate drive signal GOUT to the gate of the driving transistor, the driving transistor is turned off, and the passive drive signal SOUT is applied to the pixel electrode. Figure 2 For the corresponding Figure 1 The voltage output waveform diagram, combined with Figure 1 and Figure 2 In the actual power-on process, there is already a voltage difference between the second reference voltage VCOM and the source drive signal SOUT when the first voltage V1 is at a high level. That is, there is a voltage difference between the pixel electrode and the common electrode before the drive transistor is completely turned off, which causes the white flashing phenomenon.

[0040] To address the above problems, this utility model provides a driving circuit. Figure 3 This is a schematic diagram of a driving circuit provided in an embodiment of the present invention, with reference to... Figure 1 Based on the existing driving circuit, the driving circuit provided in this embodiment also includes an output control module 30. The output control module 30 is connected to the power supply module 10 and the level conversion module 20. The output control module 30 responds to the first voltage V1 output by the output terminal of the level conversion module 20 (corresponding to the low level VGL in the gate drive signal GOUT, used to turn off the driving transistor) and outputs the common voltage VCOM-OUT and the power supply voltage respectively, such as the first power supply voltage AVDD-OUT.

[0041] The technical solution provided by this utility model embodiment, by setting an output control module 30, uses the first voltage V1 output by the level conversion module 20 to control the output of the common voltage VCOM-OUT and the power supply voltage. This ensures that the common voltage and the power supply voltage are only output after the first voltage V1 reaches a steady state. As a result, the source drive signal SOUT and the common voltage VCOM-OUT are only input to the display panel after the drive transistor is completely turned off. This avoids the voltage difference between the pixel electrode and the common electrode when the drive transistor is not completely turned off, thereby avoiding the problem of white flickering when the power is turned on and improving the display effect.

[0042] Figure 4 This is a schematic diagram of the structure of an output control module provided in an embodiment of the present utility model, with reference to... Figure 4Based on the above embodiments, optionally, the output control module 30 includes a first input unit 301, a second input unit 302, a switch unit 303, and an output unit 304; the input terminal of the first input unit 301 is connected to a first voltage signal terminal, the output terminal of the first input unit 301 is connected to the control terminal of the switch unit 303, the input terminal of the second input unit 302 is connected to a second voltage signal terminal, the output terminal of the second input unit 302 and the output terminal of the switch unit 303 are connected to the first node N1, and the input terminal of the switch unit 303 is connected to the output terminal of the level conversion module 20; the control terminal of the output unit 304 is connected to the first node N1, the first input terminal of the output unit 304 is connected to a third voltage signal terminal, the second input terminal of the output unit 304 is connected to the second voltage signal terminal, and the output unit 304 responds to the voltage selection of the first node N1 to output a common voltage VCOM-OUT from its first output terminal and to output a first power supply voltage AVDD-OUT from its second output terminal.

[0043] Among them, the absolute value of the difference between the second voltage VLS output by the first input unit 301 and the first voltage V1 is greater than the threshold voltage of the switching unit 303.

[0044] Specifically, the first voltage signal terminal is connected to the low-level voltage VGL output by the power module 10, the second voltage signal terminal is connected to the first reference voltage AVDD output by the power module 10, and the third voltage signal terminal is connected to the second reference voltage VCOM output by the power module 10. The first input unit 301 is used to convert the low-level voltage VGL output by the power module 10 into the second voltage VLS, and the second input unit 302 is used to output the first reference voltage AVDD output by the power module 10 (or after converting AVDD) to the first node N1.

[0045] In this embodiment, the first power supply voltage AVDD-OUT is greater than the common voltage VCOM-OUT, the first reference voltage AVDD is greater than the second reference voltage VCOM, and the voltage output by the second input unit 302 is the voltage that enables the output unit 304 to be turned off. For example, the first power supply voltage AVDD-OUT and the first reference voltage AVDD are both 10.5V, and the common voltage VCOM-OUT and the second reference voltage VCOM are both 4.8V. The first voltage V1 and the low level VGL are both -6V.

[0046] Figure 5 A voltage waveform diagram provided for an embodiment of this utility model is specifically shown below. Figure 4 The voltage waveforms at each node of the driving circuit shown are combined with... Figure 4 and Figure 5When the first voltage V1 output by the level conversion module 20 is not formed (i.e., when the steady-state low voltage is not reached), the absolute value of the voltage difference between the control terminal and the input terminal of the switching unit 303 is less than the threshold voltage of the switching unit 303. The switching unit 303 is not turned on, and the voltage of the first node N1 is controlled by the output of the second input unit 302. The output unit 304 is in the off state under the voltage control of the first node N1. The output unit 304 cannot output the first reference voltage AVDD and the second reference voltage VCOM output by the power module 10. That is, the output unit 304 cannot output the common voltage VCOM-OUT and the first power supply voltage AVDD-OUT, so as to avoid the problem of voltage difference between the pixel electrode and the common electrode when the driving transistor is not completely turned off, thereby eliminating the white flash phenomenon at power-on.

[0047] After the first voltage V1 output by the level conversion module 20 is formed (i.e., when the steady-state low voltage is reached), since the absolute value of the difference between the second voltage VLS output by the first input unit 301 and the first voltage V1 is greater than the threshold voltage of the switching unit 303, the switching unit 303 is turned on, pulling down the voltage of the first node N1 to the first voltage V1. The output unit 304 responds to the voltage of the first node N1 and turns on, outputting the first reference voltage AVDD and the second reference voltage VCOM output by the power module 10. That is, the output unit 304 outputs the common voltage VCOM-OUT and the first power supply voltage AVDD-OUT.

[0048] In this embodiment, the first voltage V1, the common voltage VCOM-OUT, the first power supply voltage AVDD-OUT, and the source drive signal SOUT are output simultaneously, which can avoid the problem of voltage difference between the pixel electrode and the common electrode when the driving transistor is not completely turned off, thereby eliminating the white flash phenomenon when the power is turned on.

[0049] Of course, in other embodiments, the common voltage VCOM-OUT, the first power supply voltage AVDD-OUT, and the source drive signal SOUT can also be output after the first voltage V1 reaches a steady state, which can also eliminate the white flashing phenomenon when the power is turned on.

[0050] Figure 6 This is a schematic diagram of another output control module provided in an embodiment of the present invention, with reference to... Figure 6 Based on the above embodiments, optionally, the switching unit 303 includes a first transistor Q1, the gate of the first transistor Q1 is connected to the output terminal of the first input unit 301, the first electrode of the first transistor Q1 is connected to the first node N1, and the second electrode of the first transistor Q1 is connected to the output terminal of the level conversion module 20; wherein, the first voltage V1 is a negative voltage (e.g., -6V), and the first transistor Q1 is an N-type transistor.

[0051] The first input unit 301 includes a first operational amplifier U1 and a voltage divider unit 31. The first input terminal of the first operational amplifier U1 is connected to the first voltage signal terminal, the second input terminal of the first operational amplifier U1 is connected to the output terminal of the first operational amplifier U1, and the output terminal of the first operational amplifier U1 is connected to the control terminal of the switching unit 303 via the voltage divider unit 31.

[0052] Specifically, the first input terminal of the first operational amplifier U1 is the positive input terminal, and the second input terminal of the first operational amplifier U1 is the inverting input terminal. The second input terminal of the first operational amplifier U1 is connected to its own output terminal, forming a voltage follower. According to the principle of virtual short and virtual open of operational amplifiers, the voltage at the output terminal of the first operational amplifier U1 changes with the voltage at its first input terminal, and the voltage at the output terminal of the first operational amplifier U1 is equal to the voltage at its first input terminal. Since the low level VGL is a negative voltage, after the voltage divider subunit 31, the voltage at the gate of the first transistor Q1 (i.e., the control terminal of the switching unit 303) is higher than the low level VGL. The first transistor Q1 will only turn on when the first voltage V1 reaches a steady state; otherwise, the first transistor Q1 remains in the off state. For example, both the low-level voltage VGL and the first voltage V1 are -6V. After passing through the voltage divider unit 31, the second voltage VLS is -5.5V. Since the first transistor Q1 is an N-type transistor, it will only turn on when the difference between the second voltage VLS and the first voltage V1 is greater than 0V and greater than the threshold voltage of the first transistor Q1. At this time, the first voltage V1 has reached a steady state, and the voltage of the first node N1 is controlled by the first voltage V1. Otherwise, the first transistor Q1 is turned off, and the voltage of the first node N1 is controlled by the first reference voltage AVDD.

[0053] Optionally, in one embodiment, the voltage divider unit 31 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is connected to the output terminal of the first operational amplifier U1, and the second end of the first resistor R1 is connected to the control terminal of the switching unit 303. The first end of the second resistor R2 is connected to the second end of the first resistor R1, and the second end of the second resistor R2 is grounded. By configuring the parameters of the first resistor R1 and the second resistor R2 in conjunction with the threshold voltage of the first transistor Q1, the second voltage VLS can be made to meet the circuit requirements.

[0054] Continue to refer to Figure 6The second input unit 302 includes a second operational amplifier U2, a diode D, and a third resistor R3. The first input terminal of the second operational amplifier U2 is connected to the second voltage signal terminal, the second input terminal of the second operational amplifier U2 is connected to the output terminal of the second operational amplifier U2, the output terminal of the second operational amplifier U2 is connected to the first terminal of the diode D, the second terminal of the diode D is connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is connected to the first node N1.

[0055] In this circuit, the first input terminal of the second operational amplifier U2 is the positive input terminal, and the second input terminal is the inverting input terminal. The second input terminal of the second operational amplifier U2 is connected to its own output terminal to form a voltage follower. The output voltage of the second operational amplifier U2 is the same as the input voltage of its first input terminal, which is the first reference voltage AVDD. Diode D is unidirectional and prevents the voltage at the first node N1 from being transmitted to the output terminal of the second operational amplifier U2. The third resistor R3 is used for current limiting.

[0056] Optionally, the output unit 304 includes a first subunit 3041 and a second subunit 3042. The control terminals of the first subunit 3041 and the second subunit 3042 are both connected to the first node N1. The input terminal of the first subunit 3041 is connected to the third voltage signal terminal. The output terminal of the first subunit 3041 outputs a common voltage VCOM-OUT. The input terminal of the second subunit 3042 is connected to the first voltage signal terminal. The output terminal of the second subunit 3042 outputs the first power supply voltage AVDD-OUT.

[0057] The first sub-unit 3041 includes a second transistor Q2 and a fourth resistor R4. The gate of the second transistor Q2 is connected to the first node N1, the first terminal of the second transistor Q2 is connected to the third voltage signal terminal, the second terminal of the second transistor Q2 serves as the output terminal of the first sub-unit 3041, the first terminal of the fourth resistor R4 is connected to the second terminal of the second transistor Q2, and the second terminal of the fourth resistor R4 is grounded.

[0058] The second sub-unit 3042 includes a third transistor Q3 and a fifth resistor R5. The gate of the third transistor Q3 is connected to the first node N1, the first terminal of the third transistor Q3 is connected to the first voltage signal terminal, the second terminal of the third transistor Q3 serves as the output terminal of the second sub-unit 3042, the first terminal of the fifth resistor R5 is connected to the second terminal of the third transistor Q3, and the second terminal of the fifth resistor R5 is grounded.

[0059] In this embodiment, the second transistor Q2 and the third transistor Q3 have the same channel type, for example, both are P-type transistors, so that they can be turned on or off simultaneously in response to the voltage of the first node N1. When the first node N1 is controlled by the first reference voltage AVDD, both the second transistor Q2 and the third transistor Q3 are turned off, and the common voltage VCOM-OUT and the first power supply voltage AVDD-OUT cannot be output. When the first node N1 is controlled by the first voltage V1, both the second transistor Q2 and the third transistor Q3 are turned on. The second transistor Q2 outputs the second reference voltage VCOM to form the common voltage VCOM-OUT, and the third transistor Q3 outputs the first reference voltage AVDD to form the first power supply voltage AVDD-OUT. The fourth resistor R4 and the fifth resistor R5 can be used for overcurrent protection.

[0060] Figure 7 A schematic diagram of another output control module provided in this embodiment of the present utility model is shown below. Figure 7 ,exist Figure 6 Based on the circuit shown, the output unit 304 provided in this embodiment further includes a third subunit 3043. The control terminal of the third subunit 3043 is connected to the first node N1, the input terminal of the third subunit 3043 is connected to the fourth voltage signal terminal, and the output terminal of the third subunit 3043 outputs a second power supply voltage HAVDD-OUT; the second power supply voltage HAVDD-OUT is less than the first power supply voltage AVDD-OUT. The fourth voltage signal terminal is connected to the third reference voltage HAVDD output by the power module 10, where the third reference voltage HAVDD is half the voltage of the first reference voltage AVDD. For example, if the first reference voltage AVDD is 10.5V, then the third reference voltage HAVDD is 5.25V.

[0061] In this embodiment, by setting a third subunit 3043 in the output unit 304, the second power supply voltage HAVDD-OUT can also be output after the first voltage V1 reaches a steady state, so as to avoid abnormalities in the circuit connected to the second power supply voltage HAVDD-OUT, which is beneficial to further improve the display effect.

[0062] Optionally, the third sub-unit 3043 includes a fourth transistor Q4 and a sixth resistor R6. The gate of the fourth transistor Q4 is connected to the first node N1, the first terminal of the fourth transistor Q4 is connected to the fourth voltage signal terminal, and the second terminal of the fourth transistor Q4 serves as the output terminal of the third sub-unit 3043. The first terminal of the sixth resistor R6 is connected to the second terminal of the fourth transistor Q4, and the second terminal of the sixth resistor R6 is grounded. The fourth transistor Q4, the second transistor Q2, and the third transistor Q3 have the same channel type.

[0063] The working principle of the third subunit 3043 is the same as that of the first subunit 3041 and the second subunit 3042, and will not be described again.

[0064] Optionally, this utility model embodiment also provides a display module, which includes a display panel and a driving circuit provided in any embodiment of this utility model. The display panel can be a liquid crystal display panel, and the display module also has the beneficial effects described in the above embodiments.

[0065] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0066] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A driving circuit, comprising a power supply module and a level conversion module, wherein the power supply module is connected to the level conversion module, characterized in that, It also includes an output control module, which is connected to the power supply module and the level conversion module. The output control module outputs a common voltage and a power supply voltage respectively in response to the first voltage output by the output terminal of the level conversion module.

2. The driving circuit according to claim 1, characterized in that, The output control module includes a first input unit, a second input unit, a switch unit, and an output unit; The input terminal of the first input unit is connected to the first voltage signal terminal, the output terminal of the first input unit is connected to the control terminal of the switch unit, the input terminal of the second input unit is connected to the second voltage signal terminal, the output terminal of the second input unit and the output terminal of the switch unit are connected to the first node, and the input terminal of the switch unit is connected to the output terminal of the level conversion module. The control terminal of the output unit is connected to the first node, the first input terminal of the output unit is connected to the third voltage signal terminal, the second input terminal of the output unit is connected to the second voltage signal terminal, and the output unit responds to the voltage selection of the first node to output the common voltage from its first output terminal and output the first power supply voltage from its second output terminal.

3. The driving circuit according to claim 2, characterized in that, The absolute value of the difference between the second voltage output by the first input unit and the first voltage is greater than the threshold voltage of the switching unit.

4. The driving circuit according to claim 2, characterized in that, The first power supply voltage is greater than the common voltage; The voltage output by the second input unit is the voltage that turns off the output unit.

5. The driving circuit according to claim 2, characterized in that, The switching unit includes a first transistor, the gate of the first transistor is connected to the output terminal of the first input unit, the first electrode of the first transistor is connected to the first node, and the second electrode of the first transistor is connected to the output terminal of the level conversion module. Wherein, the first voltage is a negative voltage, and the first transistor is an N-type transistor.

6. The driving circuit according to claim 2, characterized in that, The first input unit includes a first operational amplifier and a voltage divider unit. The first input terminal of the first operational amplifier is connected to the first voltage signal terminal, the second input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is connected to the control terminal of the switching unit via the voltage divider unit. The voltage divider unit includes a first resistor and a second resistor. The first end of the first resistor is connected to the output terminal of the first operational amplifier, the second end of the first resistor is connected to the control terminal of the switching unit, the first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is grounded.

7. The driving circuit according to claim 2, characterized in that, The second input unit includes a second operational amplifier, a diode, and a third resistor. The first input terminal of the second operational amplifier is connected to the second voltage signal terminal, the second input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier, the output terminal of the second operational amplifier is connected to the first terminal of the diode, the second terminal of the diode is connected to the first terminal of the third resistor, and the second terminal of the third resistor is connected to the first node.

8. The driving circuit according to claim 2, characterized in that, The output unit includes a first subunit and a second subunit. The control terminals of the first subunit and the second subunit are both connected to the first node. The input terminal of the first subunit is connected to the third voltage signal terminal. The output terminal of the first subunit outputs the common voltage. The input terminal of the second subunit is connected to the first voltage signal terminal. The output terminal of the second subunit outputs the first power supply voltage. The first sub-unit includes a second transistor and a fourth resistor. The gate of the second transistor is connected to the first node, the first terminal of the second transistor is connected to the third voltage signal terminal, the second terminal of the second transistor serves as the output terminal of the first sub-unit, the first terminal of the fourth resistor is connected to the second terminal of the second transistor, and the second terminal of the fourth resistor is grounded. The second sub-unit includes a third transistor and a fifth resistor. The gate of the third transistor is connected to the first node, the first terminal of the third transistor is connected to the first voltage signal terminal, the second terminal of the third transistor serves as the output terminal of the second sub-unit, the first terminal of the fifth resistor is connected to the second terminal of the third transistor, and the second terminal of the fifth resistor is grounded. The second transistor and the third transistor have the same channel type.

9. The driving circuit according to claim 8, characterized in that, The output unit further includes a third subunit, the control terminal of which is connected to the first node, the input terminal of which is connected to a fourth voltage signal terminal, and the output terminal of which outputs a second power supply voltage; the second power supply voltage is less than the first power supply voltage. The third subunit includes a fourth transistor and a sixth resistor. The gate of the fourth transistor is connected to the first node, the first terminal of the fourth transistor is connected to the fourth voltage signal terminal, the second terminal of the fourth transistor serves as the output terminal of the third subunit, the first terminal of the sixth resistor is connected to the second terminal of the fourth transistor, and the second terminal of the sixth resistor is grounded. The fourth transistor, the second transistor, and the third transistor have the same channel type.

10. A display module, characterized in that, It includes a display panel and the driving circuit according to any one of claims 1-9.

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