An over-temperature protection circuit

Abstract

The application provides an over-temperature protection circuit, comprising a current input module, a current source module, a temperature sensing module, a threshold voltage generation module and a comparator. The input end of the current input module is used for connecting a to-be-protected circuit, the output end is connected to the input end of the current source module, the first output end of the current source module is grounded through the temperature sensing module, the second output end and the third output end are respectively grounded through the threshold voltage generation module, the fourth output end and the fifth output end are respectively connected to the first power supply end and the second power supply end of the comparator; the reference end of the threshold voltage generation module is connected to a preset reference power supply, the first output end and the second output end are respectively connected to the first threshold input end and the second threshold input end of the comparator, the output end of the temperature sensing module is also connected to the first detection input end and the second detection input end of the comparator, the first feedback input end and the second feedback input end of the comparator are respectively connected to the output end of the comparator, and the output end is used for outputting a temperature detection signal.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and more specifically, to an over-temperature protection circuit. Background Technology

[0002] With the development of integrated circuit technology, chip integration is becoming increasingly higher, and device density and energy consumption density are also increasing. Power consumption causes chip temperature to rise, which can easily lead to PN junction thermal breakdown and overcurrent, causing the chip to malfunction. Therefore, over-temperature protection circuits are essential in integrated circuit systems.

[0003] However, traditional over-temperature protection circuits are based on the temperature characteristics of the base-emitter voltage of bipolar transistors. They use a voltage that is inversely proportional to or directly proportional to temperature to achieve threshold detection by comparing it with a bandgap reference voltage. However, traditional bandgap references exhibit nonlinear drift over a wide temperature range, and the fixed hysteresis window of the hysteresis comparator is difficult to adapt to nonlinear temperature gradients, which can easily lead to inaccurate detection and affect the protection effect of the over-temperature protection circuit on the chip. Utility Model Content

[0004] The purpose of this invention is to address the shortcomings of the prior art by providing an over-temperature protection circuit. This circuit allows the comparator to output a temperature detection signal for temperature control of the circuit to be protected, thereby achieving over-temperature detection, preventing thermal oscillation in the chip's circuitry, and ensuring the chip's normal operation.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0006] In a first aspect, embodiments of this application provide an over-temperature protection circuit, which includes: a current input module, a current source module, a temperature sensing module, a threshold voltage generation module, and a comparator;

[0007] The input terminal of the current input module is used to connect to the circuit to be protected to receive the detection current of the circuit to be protected. The output terminal of the current input module is connected to the input terminal of the current source module. The first output terminal of the current source module is grounded through the temperature sensing module. The second and third output terminals of the current source module are grounded through the threshold voltage generation module, respectively. The reference terminal of the threshold voltage generation module is also connected to a preset reference power supply. The fourth and fifth output terminals of the current source module are connected to the first and second power supply terminals of the comparator, respectively.

[0008] The first and second output terminals of the threshold voltage generation module are respectively connected to the first and second threshold input terminals of the comparator. The output terminal of the temperature sensing module is also connected to the first and second detection input terminals of the comparator. The first and second feedback input terminals of the comparator are respectively connected to the output terminal of the comparator. The output terminal of the comparator is used to output a temperature detection signal, which is used to perform temperature control on the circuit to be protected.

[0009] In an optional implementation, the current input module is a first current mirror, the input terminal of the first current mirror is the input terminal of the current input module, and the output terminal of the first current mirror is the output terminal of the current input module.

[0010] In an optional implementation, the current source module is a second current mirror, the input terminal of the second current mirror is the input terminal of the current source module, and the multiple output terminals of the second current mirror are respectively the first output terminal, second output terminal, third output terminal, fourth output terminal and fifth output terminal of the current source module.

[0011] In an optional implementation, the temperature sensing module is a negative temperature coefficient thermistor or a negative temperature coefficient transistor.

[0012] In an optional embodiment, the threshold voltage generation module includes: a first voltage generation module and a second voltage generation module, wherein the input terminal of the first voltage generation module and the input terminal of the second voltage generation module are respectively the input terminals of the threshold voltage generation module, the control terminal of the first voltage generation module and the control terminal of the second voltage generation module are respectively the reference terminals of the threshold voltage generation module, and the output terminal of the first voltage generation module and the output terminal of the second voltage generation module are respectively the output terminals of the threshold voltage generation module.

[0013] In an optional implementation, the first voltage generation module includes: a first PMOS transistor and a second PMOS transistor;

[0014] The source of the first PMOS transistor is the input terminal of the first voltage generation module; the gate of the first PMOS transistor is the control terminal of the first voltage generation module; and the drain of the first PMOS transistor is the output terminal of the first voltage generation module.

[0015] The drain of the first PMOS transistor is connected to the drain of the second PMOS transistor; the gate and source of the second PMOS transistor are grounded.

[0016] In an optional embodiment, the second voltage generation module includes: a third PMOS transistor and a fourth PMOS transistor;

[0017] The source of the third PMOS transistor is the input terminal of the second voltage generation module; the gate of the third PMOS transistor is the control terminal of the second voltage generation module; and the drain of the third PMOS transistor is the output terminal of the second voltage generation module.

[0018] The drain of the third PMOS transistor is connected to the drain of the fourth PMOS transistor; the gate and source of the fourth PMOS transistor are grounded.

[0019] In an optional implementation, the comparator includes: a feedback input unit, a threshold input unit, a detection input unit, a third current mirror, a first inverter, and an output unit;

[0020] The power supply terminal of the feedback input unit is the first power supply terminal of the comparator. The output terminal of the comparator is connected to the first control terminal of the feedback input unit through the first inverter. The output terminal of the comparator is also directly connected to the second control terminal of the feedback input unit.

[0021] The first and second output terminals of the feedback input unit are respectively connected to the first and second power supply terminals of the threshold input unit. The first and second control terminals of the threshold input unit are respectively the first and second threshold input terminals of the comparator. The output terminal of the threshold input unit is connected to the input terminal of the third current mirror. The output terminal of the third current mirror is connected to the input terminal of the output unit.

[0022] The first power supply terminal and the second power supply terminal of the detection input unit are respectively connected to the first output terminal and the second output terminal of the feedback input unit; the first control terminal and the second control terminal of the detection input unit are respectively the first detection input terminal and the second detection input terminal of the comparator; the output terminal of the detection input unit is also connected to the input terminal of the output unit.

[0023] The power supply terminal of the output unit is the second power supply terminal of the comparator, and the output terminal of the output unit is the output terminal of the comparator.

[0024] In an optional implementation, the feedback input unit includes a fifth PMOS transistor and a sixth PMOS transistor; the threshold input unit includes a seventh PMOS transistor and an eighth PMOS transistor; and the detection input unit includes a ninth PMOS transistor and a tenth PMOS transistor.

[0025] The source of the fifth PMOS transistor and the source of the sixth PMOS transistor are the power supply terminals of the feedback input unit. The gate of the fifth PMOS transistor and the gate of the sixth PMOS transistor are the first control terminal and the second control terminal of the feedback input unit, respectively. The drain of the fifth PMOS transistor and the drain of the sixth PMOS transistor are the first output terminal and the second output terminal of the feedback input unit, respectively.

[0026] The source of the seventh PMOS transistor and the source of the eighth PMOS transistor are respectively the first power supply terminal and the second power supply terminal of the threshold input unit; the gate of the seventh PMOS transistor and the gate of the eighth PMOS transistor are respectively the first control terminal and the second control terminal of the threshold input unit; the drain of the seventh PMOS transistor and the drain of the eighth PMOS transistor are the output terminals of the threshold input unit.

[0027] The source of the ninth PMOS transistor and the source of the tenth PMOS transistor are respectively the first power supply terminal and the second power supply terminal of the detection input unit; the gate of the ninth PMOS transistor and the gate of the tenth PMOS transistor are respectively the first control terminal and the second control terminal of the detection input unit; the drain of the ninth PMOS transistor and the drain of the tenth PMOS transistor are the output terminals of the detection input unit.

[0028] In an optional embodiment, the output unit includes: a first NMOS transistor and a second inverter, wherein the gate of the first NMOS transistor is the input terminal of the output unit, the source of the first NMOS transistor is grounded, the drain of the first NMOS transistor is connected to the input terminal of the second inverter, and the output terminal of the second inverter is the output terminal of the output unit.

[0029] The beneficial effects of this application are:

[0030] This application provides an over-temperature protection circuit, including: a current input module, a current source module, a temperature sensing module, a threshold voltage generation module, and a comparator. The input terminal of the current input module is connected to the circuit to be protected to receive the detected current from the circuit. The output terminal of the current input module is connected to the input terminal of the current source module. The first output terminal of the current source module is grounded through the temperature sensing module. The second and third output terminals of the current source module are respectively grounded through the threshold voltage generation module. The reference terminal of the threshold voltage generation module is also connected to a preset reference power supply. The fourth and fifth output terminals of the current source module are respectively connected to the first and second power supply terminals of the comparator. The first and second output terminals of the threshold voltage generation module are respectively connected to the first and second threshold input terminals of the comparator. The output terminal of the temperature sensing module is also connected to the first and second detection input terminals of the comparator. The first and second feedback input terminals of the comparator are respectively connected to the output terminal of the comparator. The output terminal of the comparator is used to output a temperature detection signal, which is used for temperature control of the circuit to be protected. This achieves over-temperature detection, avoids thermal oscillation in the chip circuit, and ensures the normal operation of the chip. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A schematic diagram of an over-temperature protection circuit provided in an embodiment of this application;

[0033] Figure 2 A schematic diagram of another over-temperature protection circuit provided in an embodiment of this application;

[0034] Figure 3 A schematic diagram of yet another over-temperature protection circuit provided in an embodiment of this application;

[0035] Figure 4 This is a schematic diagram of another over-temperature protection circuit provided in an embodiment of this application.

[0036] Key component symbols: 110 - Current input module; 120 - Current source module; 130 - Temperature sensing module; 140 - Threshold voltage generation module; 150 - Comparator; 141 - First voltage generation module; 142 - Second voltage generation module; 151 - Feedback input unit; 152 - Threshold input unit; 153 - Detection input unit; 154 - Third current mirror; 155 - Output unit; D1 - First inverter; D2 - Second inverter; P1 - First PMOS transistor; P2 - Second PMOS transistor; P3 - Third PMOS transistor; P4 - Fourth PMOS transistor; P5 - Fifth PMOS transistor; P6 - Sixth PMOS transistor; P7 - Seventh PMOS transistor; P8 - Eighth PMOS transistor; P9 - Ninth PMOS transistor; P10 - Tenth PMOS transistor; N1 - First NMOS transistor; 200 - Circuit to be protected. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this utility model, but not all embodiments.

[0038] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0039] In the description of this application, it should be noted that if the terms "upper", "lower", etc. appear to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0040] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0041] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0042] The following examples, in conjunction with the accompanying drawings, provide specific illustrations of the over-temperature protection circuit provided in this application.

[0043] Figure 1 This is a schematic diagram of an over-temperature protection circuit provided in an embodiment of this application; as shown. Figure 1 As shown, the over-temperature protection circuit includes: a current input module 110, a current source module 120, a temperature sensing module 130, a threshold voltage generation module 140, and a comparator 150.

[0044] The input terminal of the current input module 110 is used to connect to the circuit to be protected 200 to receive the detection current of the circuit to be protected 200. The output terminal of the current input module 110 is connected to the input terminal of the current source module 120. The first output terminal of the current source module 120 is grounded through the temperature sensing module 130. The second and third output terminals of the current source module 120 are grounded through the threshold voltage generation module 140, respectively. The reference terminal of the threshold voltage generation module 140 is also connected to a preset reference power supply. The fourth and fifth output terminals of the current source module 120 are connected to the first and second power supply terminals of the comparator 150, respectively.

[0045] The first and second output terminals of the threshold voltage generation module 140 are respectively connected to the first and second threshold input terminals of the comparator 150. The output terminal of the temperature sensing module 130 is also connected to the first and second detection input terminals of the comparator 150. The first and second feedback input terminals of the comparator 150 are respectively connected to the output terminal of the comparator 150. The output terminal of the comparator 150 is used to output a temperature detection signal, which is used to perform temperature control on the circuit to be protected 200.

[0046] In this embodiment, the circuit to be protected 200 and the over-temperature protection circuit are integrated in the chip. The circuit to be protected 200 is a circuit that outputs a large current. Because the current flowing through it is large, it can quickly release heat energy to various circuits of the chip, causing the chip temperature to rise, thereby affecting the normal operation of the chip.

[0047] The output terminal of the circuit to be protected 200 is connected to the input terminal of the current input module 110. The current input module 110 inputs the detected current to the over-temperature protection circuit. The input terminal of the current source module 120 is connected to the output terminal of the current input module 110. The first output terminal of the current source module 120 is connected to the temperature sensing module 130, so that the temperature sensing module 130 flows through the detected current, thereby generating a negative temperature coefficient voltage. The negative temperature coefficient of the temperature sensing module 130 refers to the characteristic that the detected current decreases as the temperature increases. In other words, as the temperature increases, the negative temperature coefficient voltage gradually decreases.

[0048] The power supply terminal of the current source module 120 is connected to a preset power supply to provide power supply voltage for the entire over-temperature protection circuit. The second and third output terminals of the current source module 120 are respectively connected to the threshold voltage generation module 140. The reference terminal of the threshold voltage generation module 140 is connected to a preset reference power supply. Since the preset reference power supply provides a bias voltage for the threshold voltage generation module 140, the current flowing through the threshold voltage generation module 140 is a current with zero temperature coefficient, so that the threshold voltage generation module 140 generates a threshold voltage that is independent of the power supply voltage.

[0049] Since the first and second output terminals of the threshold voltage generation module 140 are respectively connected to the first and second threshold input terminals of the comparator 150, the threshold voltage generation module 140 can provide the generated threshold voltage to the comparator 150. Since the output terminal of the temperature sensing module 130 is also connected to the first and second detection input terminals of the comparator 150, the output terminal of the temperature sensing module 130 can provide a negative temperature coefficient voltage to the comparator 150. Since the first and second feedback input terminals of the comparator 150 are respectively connected to the output terminal of the comparator 150, the feedback signal output by the comparator 150 can be fed back to the first and second feedback input terminals of the comparator 150.

[0050] The comparator 150 outputs a temperature detection signal based on the threshold voltage, the negative temperature coefficient voltage, and the feedback signal. The temperature detection signal is used to control the temperature of the circuit to be protected 200. For example, if the output temperature detection signal is a high-level signal, it indicates that the temperature is rising and over-temperature protection is required. Specific cooling measures can be taken to control the temperature of the circuit to be protected 200. If the output temperature detection signal is a low-level signal, it indicates that the temperature is normal and detection needs to continue.

[0051] In summary, this application provides an over-temperature protection circuit, including: a current input module, a current source module, a temperature sensing module, a threshold voltage generation module, and a comparator. The input terminal of the current input module is connected to the circuit to be protected to receive the detected current from the circuit. The output terminal of the current input module is connected to the input terminal of the current source module. The first output terminal of the current source module is grounded through the temperature sensing module. The second and third output terminals of the current source module are respectively grounded through the threshold voltage generation module. The reference terminal of the threshold voltage generation module is also connected to a preset reference power supply. The fourth and fifth output terminals of the current source module are respectively connected to the first and second power supply terminals of the comparator. The first and second output terminals of the threshold voltage generation module are respectively connected to the first and second threshold input terminals of the comparator. The output terminal of the temperature sensing module is also connected to the first and second detection input terminals of the comparator. The first and second feedback input terminals of the comparator are respectively connected to the output terminal of the comparator. The output terminal of the comparator is used to output a temperature detection signal, which is used for temperature control of the circuit to be protected. This achieves over-temperature detection, avoids thermal oscillation in the chip circuit, and ensures the normal operation of the chip.

[0052] Figure 2 A schematic diagram of another over-temperature protection circuit provided in an embodiment of this application; as shown Figure 2 As shown, the current input module 110 is a first current mirror, the input terminal of the first current mirror is the input terminal of the current input module 110, and the output terminal of the first current mirror is the output terminal of the current input module 110.

[0053] In this embodiment, the first current mirror includes a second NMOS transistor N2 and a third NMOS transistor N3. The drain of the second NMOS transistor N2 serves as the input terminal of the first current mirror and is used to connect to the circuit to be protected 200. The drain and gate of the second NMOS transistor N2 are connected, and the gate of the second NMOS transistor N2 is also connected to the gate of the third NMOS transistor N3. The drain of the third NMOS transistor N3 serves as the output terminal of the first current mirror and is connected to the input terminal of the current source module 120. The sources of the second NMOS transistor N2 and the third NMOS transistor N3 are grounded. The detection current input at the input terminal is copied to the output terminal through the first current mirror, so that the input terminal of the current source module 120 receives the detection current.

[0054] Optionally, the current source module 120 is a second current mirror, the input terminal of the second current mirror is the input terminal of the current source module 120, and the multiple output terminals of the second current mirror are the first output terminal, the second output terminal, the third output terminal, the fourth output terminal and the fifth output terminal of the current source module 120.

[0055] Continue to refer to Figure 2The second current mirror includes: an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, and a sixteenth PMOS transistor P16. The gate of the eleventh PMOS transistor P11 is connected to the gates of the twelfth PMOS transistor P12, the thirteenth PMOS transistor P13, the fourteenth PMOS transistor P14, the fifteenth PMOS transistor P15, and the sixteenth PMOS transistor P16. The gate of the eleventh PMOS transistor P11 is also connected to its drain. The drain of the eleventh PMOS transistor P11 is the input terminal of the second current mirror, and the drain of the twelfth PMOS transistor P12 is the first output terminal of the second current mirror, used to connect to the temperature sensing module. Block 130 has the following connection points: the drain of the thirteenth PMOS transistor P13 is the second output terminal of the second current mirror, used to connect to the threshold voltage generation module 140; the drain of the fourteenth PMOS transistor P14 is the third output terminal of the second current mirror, used to connect to the threshold voltage generation module 140; the drain of the fifteenth PMOS transistor P15 is the fourth output terminal of the second current mirror, used to connect to the first power supply terminal of the comparator 150; and the drain of the sixteenth PMOS transistor P16 is the fifth output terminal of the second current mirror, used to connect to the second power supply terminal of the comparator 150. The second current mirror outputs detection current to the temperature sensing module 130, the threshold voltage generation module 140, and the comparator 150, respectively.

[0056] The sources of the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, the thirteenth PMOS transistor P13, the fourteenth PMOS transistor P14, the fifteenth PMOS transistor P15, and the sixteenth PMOS transistor P16 are connected to a preset power supply through a fourth current mirror. The fourth current mirror includes: the seventeenth PMOS transistor P17, the eighteenth PMOS transistor P18, the nineteenth PMOS transistor P19, the twentieth PMOS transistor P20, the twenty-first PMOS transistor P21, and the twenty-second PMOS transistor P22. The drains of the seventeenth PMOS transistor P17, the eighteenth PMOS transistor P18, the nineteenth PMOS transistor P19, the twentieth PMOS transistor P20, the twenty-first PMOS transistor P21, and the twenty-second PMOS transistor P22 are respectively connected to the sources of the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, the thirteenth PMOS transistor P13, the fourteenth PMOS transistor P14, the fifteenth PMOS transistor P15, and the sixteenth PMOS transistor P16.

[0057] The gate of the seventeenth PMOS transistor P17 is connected to the gates of the eighteenth PMOS transistor P18, the nineteenth PMOS transistor P19, the twentieth PMOS transistor P20, the twenty-first PMOS transistor P21, and the twenty-second PMOS transistor P22, respectively. The sources of the seventeenth PMOS transistor P17, the eighteenth PMOS transistor P18, the nineteenth PMOS transistor P19, the twentieth PMOS transistor P20, the twenty-first PMOS transistor P21, and the twenty-second PMOS transistor P22 are connected to a preset power supply. The fourth current mirror is used to generate a voltage drop.

[0058] Optionally, the temperature sensing module 130 is a negative temperature coefficient thermistor or a negative temperature coefficient transistor.

[0059] Continue to refer to Figure 2 The temperature sensing module 130 uses a negative temperature coefficient transistor Q1, which mainly consists of three regions: the emitter region, the base region, and the collector region. When the emitter current (IE) flows through the base region, a base current (IB) is generated due to the narrow width of the base region. When the base current (IB) reaches a certain value, the transistor enters the conducting state. At this time, the collector current (IC) is proportional to the base current (IB). When the temperature rises, the emitter current (IE) decreases, which leads to a decrease in the base current (IB), ultimately causing a decrease in the collector current (IC), thus achieving the negative temperature coefficient characteristic and generating a negative temperature coefficient voltage VEB1.

[0060] Similarly, the temperature sensing module 130 can also use a negative temperature coefficient thermistor. The resistance value of a negative temperature coefficient thermistor decreases as the temperature increases, and it can also generate a negative temperature coefficient voltage VEB1.

[0061] Figure 3 A schematic diagram of another over-temperature protection circuit provided in the embodiments of this application; as shown Figure 3 As shown, the threshold voltage generation module 140 includes: a first voltage generation module 141 and a second voltage generation module 142. The input terminal of the first voltage generation module 141 and the input terminal of the second voltage generation module 142 are respectively the input terminals of the threshold voltage generation module 140. The control terminal of the first voltage generation module 141 and the control terminal of the second voltage generation module 142 are respectively the reference terminals of the threshold voltage generation module 140. The output terminal of the first voltage generation module 141 and the output terminal of the second voltage generation module 142 are respectively the output terminals of the threshold voltage generation module 140.

[0062] In this embodiment, the first voltage generation module 141 generates a first threshold voltage, the second voltage generation module 142 generates a second threshold voltage, and transmits the first threshold voltage and the second threshold voltage to the comparator 150.

[0063] Optionally, the first voltage generation module 141 includes: a first PMOS transistor P1 and a second PMOS transistor P2.

[0064] The source of the first PMOS transistor P1 is the input terminal of the first voltage generation module 141; the gate of the first PMOS transistor P1 is the control terminal of the first voltage generation module 141; the drain of the first PMOS transistor P1 is the output terminal of the first voltage generation module 141; the drain of the first PMOS transistor P1 is connected to the drain of the second PMOS transistor P2; the gate and source of the second PMOS transistor P2 are grounded.

[0065] For details, please refer to [link / reference]. Figure 3 The gate of the first PMOS transistor P1 receives a bias voltage V. REF The first threshold voltage, i.e., the over-temperature protection threshold voltage V, is generated by adjusting the width-to-length ratio of the second PMOS transistor P2. H Wherein, the first threshold voltage V H The calculation formula is as follows:

[0066]

[0067] Among them, |V GS2 |=|V H |,μ n For electron mobility, C ox For oxide layer capacitance, μ n C ox Where W / L is the process constant, W / L is the width-to-length ratio, and |V GS2 |-|V TH2 | represents the overdrive voltage.

[0068] Because the second PMOS transistor P2 adopts a common-source, common-gate structure, the impact of power supply voltage changes on the first threshold voltage V is reduced. H Due to the influence of [the above factors], the over-temperature protection circuit has the characteristic of low power supply voltage sensitivity.

[0069] Optionally, the second voltage generation module 142 includes: a third PMOS transistor P3 and a fourth PMOS transistor P4;

[0070] The source of the third PMOS transistor P3 is the input terminal of the second voltage generation module 142; the gate of the third PMOS transistor P3 is the control terminal of the second voltage generation module 142; the drain of the third PMOS transistor P3 is the output terminal of the second voltage generation module 142; the drain of the third PMOS transistor P3 is connected to the drain of the fourth PMOS transistor P4; the gate and source of the fourth PMOS transistor P4 are grounded.

[0071] For details, please refer to [link / reference]. Figure 3 The gate of the third PMOS transistor P3 receives a bias voltage V. REFThe second threshold voltage, i.e., the restored threshold voltage V, is generated by adjusting the width-to-length ratio of the fourth PMOS transistor P4. L Among them, the second threshold voltage V L The calculation formula is as follows:

[0072]

[0073] Among them, |V GS4 |=|V L |,μ n For electron mobility, C ox For oxide layer capacitance, μ n C ox Where W / L is the process constant, W / L is the width-to-length ratio, and |V GS4 |-|V TH4 | represents the overdrive voltage.

[0074] Because the fourth PMOS transistor P4 adopts a common-source, common-gate structure, the impact of power supply voltage changes on the second threshold voltage V is reduced. L Due to the influence of [the above factors], the over-temperature protection circuit has the characteristic of low power supply voltage sensitivity.

[0075] Figure 4 A schematic diagram of another over-temperature protection circuit provided in the embodiments of this application; as shown Figure 4 As shown, the comparator 150 includes: a feedback input unit 151, a threshold input unit 152, a detection input unit 153, a third current mirror 154, a first inverter D1, and an output unit 155.

[0076] The power supply terminal of the feedback input unit 151 is the first power supply terminal of the comparator 150. The output terminal of the comparator 150 is connected to the first control terminal of the feedback input unit 151 through the first inverter D1. The output terminal of the comparator 150 is also directly connected to the second control terminal of the feedback input unit 151.

[0077] The first and second output terminals of the feedback input unit 151 are respectively connected to the first and second power supply terminals of the threshold input unit 152. The first and second control terminals of the threshold input unit 152 are respectively the first and second threshold input terminals of the comparator 150. The output terminal of the threshold input unit 152 is connected to the input terminal of the third current mirror 154. The output terminal of the third current mirror 154 is connected to the input terminal of the output unit 155.

[0078] The first power supply terminal and the second power supply terminal of the detection input unit 153 are respectively connected to the first output terminal and the second output terminal of the feedback input unit 151; the first control terminal and the second control terminal of the detection input unit 153 are respectively the first detection input terminal and the second detection input terminal of the comparator 150; the output terminal of the detection input unit 153 is also connected to the input terminal of the output unit 155.

[0079] The power supply terminal of the output unit 155 is the second power supply terminal of the comparator 150, and the output terminal of the output unit 155 is the output terminal of the comparator 150.

[0080] In this embodiment, the feedback input unit 151 receives the feedback signal output from the output terminal of the comparator 150, the threshold input unit 152 receives the first threshold voltage and the second threshold voltage output from the threshold voltage generation module 140, and the detection input unit 153 receives the negative temperature coefficient voltage output from the temperature sensing module 130. Based on the feedback signal, the comparator 150 compares the negative temperature coefficient voltage, the first threshold voltage, and the second threshold voltage, and outputs a temperature detection signal.

[0081] The third current mirror 154 includes a fourth NMOS transistor N4 and a fifth NMOS transistor N5. The gate of the fourth NMOS transistor N4 is connected to the gate of the fifth NMOS transistor N5. The gate of the fourth NMOS transistor N4 is also connected to the drain of the fourth NMOS transistor N4. The drain of the fourth NMOS transistor N4 is the input terminal of the third current mirror 154 and is connected to the output terminal of the threshold input unit 152. The drain of the fifth NMOS transistor N5 is the output terminal of the third current mirror 154 and is connected to the input terminal of the output unit 155. The source of the fourth NMOS transistor N4 and the source of the fifth NMOS transistor N5 are grounded.

[0082] Optionally, the feedback input unit 151 includes a fifth PMOS transistor P5 and a sixth PMOS transistor P6; the threshold input unit 152 includes a seventh PMOS transistor P7 and an eighth PMOS transistor P8; and the detection input unit 153 includes a ninth PMOS transistor P9 and a tenth PMOS transistor P10.

[0083] The source of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6 are the power supply terminals of the feedback input unit 151. The gate of the fifth PMOS transistor P5 and the gate of the sixth PMOS transistor P6 are the first control terminal and the second control terminal of the feedback input unit 151, respectively. The drain of the fifth PMOS transistor P5 and the drain of the sixth PMOS transistor P6 are the first output terminal and the second output terminal of the feedback input unit 151, respectively.

[0084] The source of the seventh PMOS transistor P7 and the source of the eighth PMOS transistor P8 are the first power supply terminal and the second power supply terminal of the threshold input unit 152, respectively. The gate of the seventh PMOS transistor P7 and the gate of the eighth PMOS transistor P8 are the first control terminal and the second control terminal of the threshold input unit 152, respectively. The drain of the seventh PMOS transistor P7 and the drain of the eighth PMOS transistor P8 are the output terminals of the threshold input unit 152.

[0085] The source of the ninth PMOS transistor P9 and the source of the tenth PMOS transistor P10 are the first power supply terminal and the second power supply terminal of the detection input unit 153, respectively. The gate of the ninth PMOS transistor P9 and the gate of the tenth PMOS transistor P10 are the first control terminal and the second control terminal of the detection input unit 153, respectively. The drain of the ninth PMOS transistor P9 and the drain of the tenth PMOS transistor P10 are the output terminals of the detection input unit 153.

[0086] Optionally, the output unit 155 includes: a first NMOS transistor N1 and a second inverter D2. The gate of the first NMOS transistor N1 is the input terminal of the output unit 155, the source of the first NMOS transistor N1 is grounded, the drain of the first NMOS transistor N1 is connected to the input terminal of the second inverter D2, and the output terminal of the second inverter D2 is the output terminal of the output unit 155.

[0087] For details, please refer to [link / reference]. Figure 4 Under normal chip operation, the temperature detection signal output by the second inverter D2 is a low-level signal, which is fed back to the second control terminal of the feedback input unit 151, i.e., the gate of the sixth PMOS transistor P6. At this time, the sixth PMOS transistor P6 is in the on state. The input terminal of the first inverter D1 is connected to the input terminal of the second inverter D2, inverting the low-level signal to obtain a high-level signal, which is fed back to the first control terminal of the feedback input unit 151, i.e., the gate of the fifth PMOS transistor P5. At this time, the fifth PMOS transistor P5 is in the off state.

[0088] Because the drain of the sixth PMOS transistor P6 is connected to the source of the eighth PMOS transistor P8, the gate of the eighth PMOS transistor P8 receives the second threshold voltage. Under normal chip operation, the negative temperature coefficient voltage and the second threshold voltage are compared. When the negative temperature coefficient voltage V... EB1 Greater than the second threshold voltage V L At this time, the sixth PMOS transistor P6, the eighth PMOS transistor P8, and the fourth NMOS transistor N4 are turned on, so the fifth NMOS transistor N5 is also turned on. The source voltage of the eighth PMOS transistor P8 is greater than the gate voltage, and the source of the eighth PMOS transistor P8 is connected to the source of the tenth PMOS transistor P10. Due to the negative temperature coefficient voltage V EB1 Greater than the second threshold voltage V L That is, the gate voltage of the tenth PMOS transistor P10 is greater than the source voltage. At this time, the tenth PMOS transistor P10 is in the off state. Since the fifth NMOS transistor N5 is also turned on, it will pull the gate voltage of the first NMOS transistor N1 to ground, making the first NMOS transistor N1 in the off state. At this time, the input terminal of the second inverter D2 is supplied with power voltage by the fifth output terminal of the current source module 120. The input terminal of the second inverter D2 is at a high level, so the output terminal of the second inverter D2 outputs a low level signal.

[0089] As temperature increases, the negative temperature coefficient voltage V EB1 Gradually decrease, when the negative temperature coefficient voltage V EB1 Less than the second threshold voltage V L At this time, the sixth PMOS transistor P6, the eighth PMOS transistor P8, and the fourth NMOS transistor N4 are turned on, so the fifth NMOS transistor N5 is also turned on. The source voltage of the eighth PMOS transistor P8 is greater than the gate voltage, and the source of the eighth PMOS transistor P8 is connected to the source of the tenth PMOS transistor P10. Due to the negative temperature coefficient voltage V EB1 Less than the second threshold voltage V L In other words, the gate voltage of the tenth PMOS transistor P10 is less than the source voltage, so P10 is in the on state. Since the fifth NMOS transistor N5 is also on, the first NMOS transistor N1 is also on. At this time, the input of the second inverter D2 is low, so the output of the second inverter D2 outputs a high-level signal, which is fed back to the gate of the sixth PMOS transistor P6, causing P6 to turn off. The first inverter D1 inverts the high-level signal to obtain a low-level signal, which is fed back to the gate of the fifth PMOS transistor P5, causing P5 to turn on. Thus, the comparison threshold is changed from the second threshold voltage V. L Switch to the first threshold voltage V H .

[0090] As the temperature gradually decreases from a high temperature, only when the negative temperature coefficient voltage V... EB1 Voltage greater than the first threshold voltage V H At this time, the fifth PMOS transistor P5, the seventh PMOS transistor P7, and the fourth NMOS transistor N4 are turned on, so the fifth NMOS transistor N5 is also turned on. The source voltage of the seventh PMOS transistor P7 is greater than the gate voltage, and the source of the seventh PMOS transistor P7 is connected to the source of the ninth PMOS transistor P9. Due to the negative temperature coefficient voltage V EB1 Voltage greater than the first threshold voltage V H In other words, the gate voltage of the ninth PMOS transistor P9 is greater than the source voltage, so the ninth PMOS transistor P9 is in the off state. Since the fifth NMOS transistor N5 is also turned on, it will pull the gate voltage of the first NMOS transistor N1 to ground, making the first NMOS transistor N1 in the off state. At this time, the input terminal of the second inverter D2 is supplied with power voltage by the fifth output terminal of the current source module 120. The input terminal of the second inverter D2 is at a high level, so the output terminal of the second inverter D2 resumes to output a low level signal. In this way, temperature hysteresis is generated, avoiding thermal oscillation. In addition, by adjusting the width-to-length ratio of the second PMOS transistor P2 and the fourth PMOS transistor P4, the over-temperature threshold can be precisely set, realizing the adjustability of the threshold.

[0091] The above are merely specific embodiments of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. An over-temperature protection circuit, characterized in that, The over-temperature protection circuit includes: a current input module, a current source module, a temperature sensing module, a threshold voltage generation module, and a comparator; The input terminal of the current input module is used to connect to the circuit to be protected to receive the detection current of the circuit to be protected. The output terminal of the current input module is connected to the input terminal of the current source module. The first output terminal of the current source module is grounded through the temperature sensing module. The second and third output terminals of the current source module are grounded through the threshold voltage generation module, respectively. The reference terminal of the threshold voltage generation module is also connected to a preset reference power supply. The fourth and fifth output terminals of the current source module are connected to the first and second power supply terminals of the comparator, respectively. The first and second output terminals of the threshold voltage generation module are respectively connected to the first and second threshold input terminals of the comparator. The output terminal of the temperature sensing module is also connected to the first and second detection input terminals of the comparator. The first and second feedback input terminals of the comparator are respectively connected to the output terminal of the comparator. The output terminal of the comparator is used to output a temperature detection signal, which is used to perform temperature control on the circuit to be protected.

2. The circuit according to claim 1, characterized in that, The current input module is a first current mirror, the input terminal of the first current mirror is the input terminal of the current input module, and the output terminal of the first current mirror is the output terminal of the current input module.

3. The circuit according to claim 1, characterized in that, The current source module is a second current mirror, the input terminal of the second current mirror is the input terminal of the current source module, and the multiple output terminals of the second current mirror are the first output terminal, the second output terminal, the third output terminal, the fourth output terminal and the fifth output terminal of the current source module.

4. The circuit according to claim 1, characterized in that, The temperature sensing module is a negative temperature coefficient thermistor or a negative temperature coefficient transistor.

5. The circuit according to claim 1, characterized in that, The threshold voltage generation module includes: a first voltage generation module and a second voltage generation module, wherein the input terminals of the first voltage generation module and the second voltage generation module are respectively the input terminals of the threshold voltage generation module, the control terminals of the first voltage generation module and the second voltage generation module are respectively the reference terminals of the threshold voltage generation module, and the output terminals of the first voltage generation module and the second voltage generation module are respectively the output terminals of the threshold voltage generation module.

6. The circuit according to claim 5, characterized in that, The first voltage generation module includes: a first PMOS transistor and a second PMOS transistor; The source of the first PMOS transistor is the input terminal of the first voltage generation module; the gate of the first PMOS transistor is the control terminal of the first voltage generation module; and the drain of the first PMOS transistor is the output terminal of the first voltage generation module. The drain of the first PMOS transistor is connected to the drain of the second PMOS transistor; the gate and source of the second PMOS transistor are grounded.

7. The circuit according to claim 5, characterized in that, The second voltage generation module includes: a third PMOS transistor and a fourth PMOS transistor; The source of the third PMOS transistor is the input terminal of the second voltage generation module; the gate of the third PMOS transistor is the control terminal of the second voltage generation module; and the drain of the third PMOS transistor is the output terminal of the second voltage generation module. The drain of the third PMOS transistor is connected to the drain of the fourth PMOS transistor; the gate and source of the fourth PMOS transistor are grounded.

8. The circuit according to claim 1, characterized in that, The comparator includes: a feedback input unit, a threshold input unit, a detection input unit, a third current mirror, a first inverter, and an output unit; The power supply terminal of the feedback input unit is the first power supply terminal of the comparator. The output terminal of the comparator is connected to the first control terminal of the feedback input unit through the first inverter. The output terminal of the comparator is also directly connected to the second control terminal of the feedback input unit. The first and second output terminals of the feedback input unit are respectively connected to the first and second power supply terminals of the threshold input unit. The first and second control terminals of the threshold input unit are respectively the first and second threshold input terminals of the comparator. The output terminal of the threshold input unit is connected to the input terminal of the third current mirror. The output terminal of the third current mirror is connected to the input terminal of the output unit. The first power supply terminal and the second power supply terminal of the detection input unit are respectively connected to the first output terminal and the second output terminal of the feedback input unit; the first control terminal and the second control terminal of the detection input unit are respectively the first detection input terminal and the second detection input terminal of the comparator; the output terminal of the detection input unit is also connected to the input terminal of the output unit. The power supply terminal of the output unit is the second power supply terminal of the comparator, and the output terminal of the output unit is the output terminal of the comparator.

9. The circuit according to claim 8, characterized in that, The feedback input unit includes a fifth PMOS transistor and a sixth PMOS transistor; the threshold input unit includes a seventh PMOS transistor and an eighth PMOS transistor; the detection input unit includes a ninth PMOS transistor and a tenth PMOS transistor. The source of the fifth PMOS transistor and the source of the sixth PMOS transistor are the power supply terminals of the feedback input unit. The gate of the fifth PMOS transistor and the gate of the sixth PMOS transistor are the first control terminal and the second control terminal of the feedback input unit, respectively. The drain of the fifth PMOS transistor and the drain of the sixth PMOS transistor are the first output terminal and the second output terminal of the feedback input unit, respectively. The source of the seventh PMOS transistor and the source of the eighth PMOS transistor are respectively the first power supply terminal and the second power supply terminal of the threshold input unit; the gate of the seventh PMOS transistor and the gate of the eighth PMOS transistor are respectively the first control terminal and the second control terminal of the threshold input unit; the drain of the seventh PMOS transistor and the drain of the eighth PMOS transistor are the output terminals of the threshold input unit. The source of the ninth PMOS transistor and the source of the tenth PMOS transistor are respectively the first power supply terminal and the second power supply terminal of the detection input unit; the gate of the ninth PMOS transistor and the gate of the tenth PMOS transistor are respectively the first control terminal and the second control terminal of the detection input unit; the drain of the ninth PMOS transistor and the drain of the tenth PMOS transistor are the output terminals of the detection input unit.

10. The circuit according to claim 8, characterized in that, The output unit includes: a first NMOS transistor and a second inverter. The gate of the first NMOS transistor is the input terminal of the output unit, the source of the first NMOS transistor is grounded, the drain of the first NMOS transistor is connected to the input terminal of the second inverter, and the output terminal of the second inverter is the output terminal of the output unit.

Images