Busbar voltage relief device

Abstract

The bus voltage bleeder device provided by the present disclosure includes a bus voltage upper limit judgment circuit, a bus voltage lower limit judgment circuit, a monostable trigger circuit, a drive circuit and a bleeder circuit. The bus voltage upper limit judgment circuit includes a first DC bus voltage sampling circuit, an upper limit reference voltage generating circuit and an upper limit voltage comparison circuit. Two input ends of the upper limit voltage comparison circuit are connected with the first DC bus voltage sampling circuit and the upper limit reference voltage generating circuit respectively. The bus voltage lower limit judgment circuit includes a second DC bus voltage sampling circuit and a lower limit detection module. An input end of the lower limit detection module is connected with the second DC bus voltage sampling circuit. The monostable trigger circuit includes a first input end and a second input end. The first input end is connected with an output end of the upper limit voltage comparison circuit, and the second input end is connected with an output end of the lower limit detection module. The drive circuit is connected with an output end of the monostable trigger circuit. The bleeder circuit is connected with an output end of the drive circuit. The bus voltage bleeder device provided by the present disclosure can improve the instantaneity and reliability of the bus voltage bleeder circuit.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit technology, and in particular to a bus voltage discharge device. Background Technology

[0002] Servo drivers are used to control servo motors for high-precision positioning and motion tracking. During operation, servo motors generate electricity during braking and rapid deceleration, which increases the DC bus voltage. Excessive voltage can damage the circuit. Therefore, a bleeder circuit composed of power switching devices can be connected between the buses to discharge the voltage through a power resistor.

[0003] Traditional bus voltage bleed-off circuits are implemented in hardware. When the bus voltage exceeds a set threshold, the power switch closes to bleed the voltage; when the bus voltage falls below the set threshold hysteresis voltage, the power switch opens to complete the bleed-off process. This approach lacks control over the bleed-off time. If the bus voltage remains consistently above the threshold, the power switch will remain closed, potentially leading to overheating and damage due to prolonged operation.

[0004] In addition, the bus voltage discharge circuit can be controlled by software for voltage discharge. The MCU samples the bus voltage by voltage divider and judges the start and stop of discharge through the program. The discharge time is monitored by the MCU. If the discharge time is too long, an alarm protection will be triggered. However, due to the long sampling and filtering time in the software control method and the low power-on stability of the MCU, the timeliness and reliability of the software-controlled bus voltage discharge are not high. Utility Model Content

[0005] In view of this, the present disclosure provides a bus voltage discharge device to solve the technical problems of low immediacy and reliability in the bus voltage discharge process in the prior art.

[0006] To achieve the above objectives, the technical solution adopted in this disclosure is:

[0007] The bus voltage discharge device provided in this embodiment includes: a bus voltage upper limit judgment circuit, comprising a first DC bus voltage sampling circuit, an upper limit reference voltage generation circuit, and an upper limit voltage comparison circuit; the first DC bus voltage sampling circuit is connected to the DC bus, and the two input terminals of the upper limit voltage comparison circuit are respectively connected to the first DC bus voltage sampling circuit and the upper limit reference voltage generation circuit; a bus voltage lower limit judgment circuit, comprising a second DC bus voltage sampling circuit and a lower limit detection module; the second DC bus voltage sampling circuit is connected to the DC bus, and the input terminal of the lower limit detection module is connected to the second DC bus voltage sampling circuit; a monostable trigger circuit, comprising a first input terminal and a second input terminal; the first input terminal is connected to the output terminal of the upper limit voltage comparison circuit, and the second input terminal is connected to the output terminal of the lower limit detection module; a driving circuit connected to the output terminal of the monostable trigger circuit; and a discharge circuit connected to the output terminal of the driving circuit.

[0008] In some embodiments, the lower limit detection module includes a lower limit reference voltage generation circuit and a lower limit voltage comparison circuit. The two input terminals of the lower limit voltage comparison circuit are respectively connected to the second DC bus voltage sampling circuit and the upper and lower limit reference voltage generation circuits. The output terminal of the lower limit voltage comparison circuit is connected to the second input terminal of the monostable trigger circuit.

[0009] In some embodiments, the second DC bus voltage sampling circuit includes a software voltage sampling circuit, and the lower limit detection module includes a controller. The controller is connected to the output terminal of the software voltage sampling circuit, and the output terminal of the controller is connected to the second input terminal of the monostable trigger circuit.

[0010] In some embodiments, the upper limit voltage comparison circuit includes a first comparator, the positive input terminal of the first comparator is connected to the output terminal of the upper limit reference voltage generation circuit, the negative input terminal of the first comparator is connected to the output terminal of the first DC bus voltage sampling circuit, and the output terminal of the first comparator is connected to the monostable trigger circuit.

[0011] In some embodiments, a first positive feedback resistor is connected between the positive input terminal and the output terminal of the first comparator.

[0012] In some embodiments, the lower limit voltage comparison circuit includes a second comparator, the positive input terminal of which is connected to the output terminal of the second DC bus voltage sampling circuit, the negative input terminal of which is connected to the output terminal of the lower limit reference voltage generation circuit, and the output terminal of which is connected to the monostable trigger circuit.

[0013] In some embodiments, a second positive feedback resistor is connected between the positive input terminal and the output terminal of the second comparator.

[0014] In some embodiments, the monostable trigger circuit includes a monostable trigger chip and an RC adjustment circuit. The RC adjustment circuit includes an adjustment resistor and an adjustment capacitor. The adjustment resistor is connected between the pull-up power supply and the first terminal of the adjustment capacitor. The first terminal of the adjustment capacitor is connected to the external resistor input terminal of the monostable trigger chip, and the second terminal of the adjustment capacitor is connected to the external capacitor input terminal of the monostable trigger chip. The resistance value of the adjustment resistor and the capacitance value of the adjustment capacitor are set according to a preset discharge time.

[0015] In some embodiments, the first DC bus voltage sampling circuit includes a first voltage divider resistor and a second voltage divider resistor. The first voltage divider resistor and the second voltage divider resistor are connected in series between the positive DC bus and the negative DC bus. The first end of the first voltage divider resistor is connected to the first end of the second voltage divider resistor, the second end of the second voltage divider resistor is connected to the negative DC bus, and the first end of the first voltage divider resistor is connected to the output terminal of the first DC bus voltage sampling circuit.

[0016] In some embodiments, the upper limit reference voltage generation circuit includes a third voltage divider resistor and a fourth voltage divider resistor. The third voltage divider resistor and the fourth voltage divider resistor are connected in series between the positive and negative terminals of the standard voltage power supply. The first end of the third voltage divider resistor is connected to the first end of the fourth voltage divider resistor, the second end of the fourth voltage divider resistor is connected to the negative terminal of the standard voltage power supply, and the first end of the fourth voltage divider resistor is connected to the output terminal of the upper limit reference voltage generation circuit.

[0017] The beneficial effects of this embodiment compared with the prior art are as follows: The bus voltage discharge device in this embodiment designs a bus voltage upper limit judgment circuit and a bus voltage lower limit judgment circuit, and further generates a discharge signal based on the detection signals generated by the bus voltage upper limit judgment circuit and the bus voltage lower limit judgment circuit to control the operation of the discharge circuit. It can control the operation of the discharge circuit when the bus voltage reaches the upper limit reference voltage, and can control the discharge circuit to stop voltage discharge when the bus voltage drops to the lower limit reference voltage, thereby improving the immediacy and reliability of bus voltage discharge. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a bus voltage discharge device provided in an embodiment of this disclosure;

[0020] Figure 2This is a schematic diagram of another bus voltage discharge device provided in an embodiment of this disclosure;

[0021] Figure 3 This is a circuit diagram of a bus voltage discharge device provided in an embodiment of this disclosure;

[0022] Figure 4 This is a schematic diagram of another bus voltage discharge device provided in the embodiments of this disclosure. Detailed Implementation

[0023] To make the technical problems, technical solutions, and beneficial effects to be solved by this disclosure clearer, the disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining this disclosure and are not intended to limit this disclosure.

[0024] The bus voltage discharge device according to an embodiment of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0025] Figure 1 This is a schematic diagram of the structure of a bus voltage discharge device provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of another bus voltage discharge device provided in an embodiment of this disclosure; Figure 3 This is a circuit diagram of a bus voltage discharge device provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of another bus voltage discharge device provided in the embodiments of this disclosure. The following is in conjunction with... Figure 1 , Figure 2 , Figure 4 and Figure 3 Let's describe the bus voltage discharge device provided in the embodiments of this disclosure.

[0026] like Figure 1 As shown, the bus voltage discharge device of this disclosure embodiment includes: the bus voltage upper limit judgment circuit, the bus voltage lower limit judgment circuit, the monostable trigger circuit, the driving circuit and the discharge circuit.

[0027] The upper limit determination circuit for the bus voltage includes a first DC bus voltage sampling circuit 111, an upper limit reference voltage generation circuit 112, and an upper limit voltage comparison circuit 113. The first DC bus voltage sampling circuit is connected to the DC bus, and the two input terminals of the upper limit voltage comparison circuit are connected to the first DC bus voltage sampling circuit and the upper limit reference voltage generation circuit, respectively. The upper limit voltage comparison circuit compares the DC bus voltage sampled by the first DC bus voltage sampling circuit with the upper limit reference voltage generated by the upper limit reference voltage generation circuit to obtain an upper limit detection signal, which indicates whether the DC bus voltage exceeds the upper limit reference voltage. The lower limit determination circuit for the bus voltage includes a second DC bus voltage sampling circuit 121 and a lower limit detection module 122. The second DC bus voltage sampling circuit is connected to the DC bus, and the input terminal of the lower limit detection module is connected to the second DC bus voltage sampling circuit. The lower limit detection module 122 compares the DC bus voltage sampled by the second DC bus voltage sampling circuit with a preset lower limit reference voltage to obtain a lower limit detection signal, which indicates whether the DC bus voltage exceeds the lower limit reference voltage. The monostable trigger circuit 130 includes a first input terminal and a second input terminal. The first input terminal of the monostable trigger circuit 130 is connected to the output terminal of the upper limit voltage comparator circuit, and the second input terminal of the monostable trigger circuit 130 is connected to the output terminal of the lower limit detection module. It is used to generate a discharge signal based on the upper limit detection signal and the lower limit detection signal. The drive circuit 150 is connected to the output terminal of the monostable trigger circuit and is used to generate a drive signal based on the discharge signal. The discharge circuit 160 is connected to the output terminal of the drive circuit and is used to perform voltage discharge based on the drive signal.

[0028] The technical solution of this disclosure can be applied to a novel servo driver, providing a novel bus voltage discharge protection circuit for a servo driver. This protection circuit is simple in circuitry, flexible in design, and highly implementable. Based on determining the start of bus voltage discharge through a bus voltage upper limit judgment circuit to ensure timely discharge, a bus voltage lower limit judgment circuit can be used to protect the discharge time. After discharge is completed, the discharge switch is automatically turned off in advance, solving the problem of power switch damage caused by excessively long discharge output time in existing bus voltage discharge methods, thereby improving the reliability of the discharge circuit.

[0029] Specifically, such as Figure 1As shown, the first DC bus voltage sampling circuit 111 is connected to the positive terminal DC+ and the negative terminal DC- of the DC bus. The upper limit reference voltage generation circuit 112 generates an upper limit reference voltage. The upper limit voltage comparison circuit 113 compares the DC bus voltage with the upper limit reference voltage, and outputs a pulse as an upper limit detection signal when the DC bus voltage reaches the upper limit reference voltage. The second DC bus voltage sampling circuit 121 is connected to the positive terminal DC+ and the negative terminal DC- of the DC bus to sample the DC bus voltage. The lower limit detection module 122 generates a lower limit detection signal based on the DC bus voltage and a preset lower limit reference voltage. The monostable trigger circuit 130 receives the trigger signals from the upper limit voltage comparison circuit 113 and the lower limit detection module 122, and performs logic conversion to control the operation of the drive circuit 150 and the discharge circuit 160.

[0030] The lower limit detection module can be a hardware control circuit consisting of a reference voltage generation circuit and a voltage comparison circuit, with the voltage comparison implemented in hardware. Alternatively, it can be a combined hardware and software control circuit consisting of an MCU (Microcontroller Unit) and its peripheral circuits, with the voltage comparison implemented in software. The MCU is the controller, and its peripheral circuits include, but are not limited to, clock and interrupt circuits, general-purpose input / output circuits, analog-to-digital converters, timers, and serial peripheral interfaces.

[0031] like Figure 2 As shown, when the lower limit detection module consists of a reference voltage generation circuit and a voltage comparison circuit, the lower limit detection module includes a lower limit reference voltage generation circuit 222 and a lower limit voltage comparison circuit 223. The two input terminals of the lower limit voltage comparison circuit are connected to the second DC bus voltage sampling circuit and the upper and lower limit reference voltage generation circuits, respectively. The output terminal of the lower limit voltage comparison circuit is connected to the second input terminal of the monostable trigger circuit. The lower limit voltage comparison circuit is used to compare the DC bus voltage collected by the second DC bus voltage sampling circuit 221 with the lower limit reference voltage generated by the lower limit reference voltage generation circuit to obtain the lower limit detection signal. It can be seen that the bus voltage lower limit judgment circuit includes a second DC bus voltage sampling circuit 221, an upper limit reference voltage generation circuit 222, and an upper limit voltage comparison circuit 223, and its detection principle is the same as that of the bus voltage upper limit judgment circuit. The second DC bus voltage sampling circuit 221 is connected to the positive DC+ and negative DC- terminals of the DC bus. The lower limit reference voltage generation circuit 222 generates the upper limit reference voltage. The lower limit voltage comparison circuit 223 compares the DC bus voltage with the lower limit reference voltage. When the DC bus voltage drops to the lower limit reference voltage, it outputs a pulse as a lower limit detection signal.

[0032] Specifically, such as Figure 3As shown, the upper limit voltage comparison circuit includes a first comparator A1. The positive input of the first comparator A1 is connected to the output of the upper limit reference voltage generation circuit to receive the upper limit reference voltage Vref_OV. The negative input of the first comparator A1 is connected to the output of the first DC bus voltage sampling circuit to receive the DC bus voltage. The output of the first comparator A1 is connected to a monostable trigger circuit. The lower limit voltage comparison circuit includes a second comparator A2. The positive input of the second comparator A2 is connected to the output of the second DC bus voltage sampling circuit to receive the DC bus voltage. The negative input of the second comparator A2 is connected to the output of the lower limit reference voltage generation circuit to receive the lower limit reference voltage Vref_UV. The output of the second comparator A2 is connected to a monostable trigger circuit.

[0033] like Figure 3 As shown, the monostable trigger circuit package can be composed of a monostable trigger chip and an RC adjustment circuit 140. The monostable trigger chip can be an integrated circuit 74LVC123, but is not limited to this. The output terminal of the first comparator A1 is connected to the input terminal A / of the monostable trigger chip, and the output terminal of the second comparator A2 is connected to the input terminal CLR / of the monostable trigger chip.

[0034] The RC adjustment circuit can consist of an adjusting resistor R4 and an adjusting capacitor C1. The adjusting resistor is connected between the pull-up power supply VCC and the first terminal of the adjusting capacitor C1. The first terminal of the adjusting capacitor C1 is connected to the external resistor input terminal Rext / Cext of the monostable trigger chip, and the second terminal of the adjusting capacitor is connected to the external capacitor input terminal Cext of the monostable trigger chip. The resistance and capacitance values ​​are set according to a preset discharge time. After designing the RC adjustment circuit, the discharge time of the discharge circuit can be set. The output terminal Q of the monostable trigger chip generates a discharge signal based on the upper limit detection signal and the lower limit detection signal.

[0035] In this embodiment, the first DC bus voltage sampling circuit 111 samples the DC bus voltage using a resistor divider method. Specifically, the first DC bus voltage sampling circuit 111 includes a first voltage divider resistor and a second voltage divider resistor. The first and second voltage divider resistors are connected in series between the positive DC bus and the negative DC bus. The first end of the first voltage divider resistor is connected to the first end of the second voltage divider resistor, the second end of the second voltage divider resistor is connected to the negative DC bus, and the first end of the first voltage divider resistor is connected to the output terminal of the first DC bus voltage sampling circuit. Both the first and second voltage divider resistors can be single resistors or a combination of multiple resistors connected in series. The structure of the second DC bus voltage sampling circuit 221 can be the same as that of the first DC bus voltage sampling circuit 111.

[0036] In this embodiment, the reference voltage generation circuit can be implemented using a resistor divider. The required protection threshold can be set by adjusting the resistor values, and this protection threshold includes an upper reference voltage Vref_OV and a lower reference voltage Vref_UV. Specifically, the upper reference voltage generation circuit 113 includes a third voltage divider resistor and a fourth voltage divider resistor. The third and fourth voltage divider resistors are connected in series between the positive and negative terminals of the standard voltage power supply. The first terminal of the third voltage divider resistor is connected to the first terminal of the fourth voltage divider resistor, the second terminal of the fourth voltage divider resistor is connected to the negative terminal of the standard voltage power supply, and the first terminal of the fourth voltage divider resistor is connected to the output terminal of the upper reference voltage generation circuit. The third and fourth voltage divider resistors can be single resistors or a combination of multiple resistors connected in series. The structure of the lower reference voltage generation circuit 223 can be the same as that of the upper reference voltage generation circuit 113.

[0037] like Figure 3 As shown, the output of the first comparator is connected to the pull-up power supply VCC via pull-up resistor R1, and the output of the second comparator is connected to the pull-up power supply VCC via pull-up resistor R3. A first positive feedback resistor R2 is connected between the positive input and output of the first comparator. A second positive feedback resistor R4 is connected between the positive input and output of the second comparator.

[0038] The positive feedback resistor R2 can be designed to hysteresis the voltage, preventing the action pulse from fluctuating near the threshold voltage. When the bus voltage rises, comparator A1 activates, stabilizing the output falling edge pulse. After the monostable trigger chip is triggered, its output terminal Q will output a pulse width output for a certain period of time. The high-level pulse will drive the bleeder circuit to activate. The bleeder time is set and adjusted by the resistor R4 and capacitor C1 of the RC-regulated circuit, determining the bleeder time t = R4 * C1. After the output terminal Q of the monostable trigger chip reaches this bleeder time, it will turn off, and the pulse width output will return to a low level, achieving protection during the bleeder time. The pulse width output is determined by the trigger. Even if the DC bus voltage sampled by the first DC bus voltage sampling circuit 111 has not dropped to a safe value, the bleeder circuit has already activated once and will not output again. The output terminal Q of the monostable trigger chip maintains a low level, protecting the drive circuit and the bleeder circuit from continuous output.

[0039] like Figure 3 As shown, the positive feedback resistor R4 can be designed to hysteresis the voltage to prevent the action pulse from fluctuating near the threshold voltage. When the bus voltage drops, comparator A2 activates, outputting a falling edge pulse. The output terminal Q of the monostable trigger chip outputs a low level, turning off the discharge circuit. This scheme can achieve the function of turning off the discharge in advance when the DC bus voltage has dropped to a safe value before the discharge time has elapsed.

[0040] like Figure 4As shown, when the lower limit detection module consists of an MCU and its peripheral circuits, the second DC bus voltage sampling circuit can be a software voltage sampling circuit 321. The lower limit detection module includes a controller 322, which is connected to the output of the software voltage sampling circuit. The output of the controller is connected to the second input of the monostable trigger circuit. The controller compares the DC bus voltage acquired by the software voltage sampling circuit with a preset lower limit reference voltage to obtain the lower limit detection signal. The software voltage sampling circuit can perform voltage division sampling on the DC bus voltage. After analog-to-digital conversion analysis and calculation by the controller, a pulse control signal is output, which can forcibly open and close the discharge circuit. This scheme retains the immediacy of the discharge circuit implemented by the hardware circuit, while also having the convenience of software implementation, greatly increasing the reliability of the circuit.

[0041] The technical solution of this disclosure embodiment can achieve overvoltage discharge through a simple hardware circuit of the bus voltage upper limit judgment circuit, and the discharge time can be set using an RC adjustment circuit for discharge time protection. Furthermore, through the design output of the bus voltage lower limit judgment circuit, the discharge action can be shut off in advance when the bus voltage drops to a normal value, avoiding excessive energy consumption and ensuring the immediacy, reliability, and stability of the discharge action. The bus voltage lower limit judgment circuit can implement the discharge function using a simple hardware circuit of the bus voltage upper limit judgment circuit, or it can implement the discharge function using software.

[0042] According to the bus voltage discharge device provided in the embodiments of this disclosure, by designing a bus voltage upper limit judgment circuit and a bus voltage lower limit judgment circuit, and further generating a discharge signal based on the detection signals generated by the bus voltage upper limit judgment circuit and the bus voltage lower limit judgment circuit, the device controls the operation of the discharge circuit. It can control the operation of the discharge circuit when the bus voltage reaches the upper limit reference voltage, and can control the discharge circuit to stop voltage discharge when the bus voltage drops to the lower limit reference voltage, thereby improving the immediacy and reliability of bus voltage discharge.

[0043] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A bus voltage discharge device, characterized in that, The bus voltage discharge device includes: The upper limit determination circuit for bus voltage includes a first DC bus voltage sampling circuit, an upper limit reference voltage generation circuit, and an upper limit voltage comparison circuit. The first DC bus voltage sampling circuit is connected to the DC bus, and the two input terminals of the upper limit voltage comparison circuit are respectively connected to the first DC bus voltage sampling circuit and the upper limit reference voltage generation circuit. The bus voltage lower limit judgment circuit includes a second DC bus voltage sampling circuit and a lower limit detection module. The second DC bus voltage sampling circuit is connected to the DC bus, and the input terminal of the lower limit detection module is connected to the second DC bus voltage sampling circuit. A monostable trigger circuit includes a first input terminal and a second input terminal. The first input terminal is connected to the output terminal of the upper limit voltage comparison circuit, and the second input terminal is connected to the output terminal of the lower limit detection module. The driving circuit is connected to the output terminal of the monostable trigger circuit; The discharge circuit is connected to the output terminal of the drive circuit.

2. The bus voltage discharge device according to claim 1, characterized in that, The lower limit detection module includes a lower limit reference voltage generation circuit and a lower limit voltage comparison circuit. The two input terminals of the lower limit voltage comparison circuit are respectively connected to the second DC bus voltage sampling circuit and the upper and lower limit reference voltage generation circuit. The output terminal of the lower limit voltage comparison circuit is connected to the second input terminal of the monostable trigger circuit.

3. The bus voltage discharge device according to claim 1, characterized in that, The second DC bus voltage sampling circuit includes a software voltage sampling circuit, and the lower limit detection module includes a controller. The controller is connected to the output terminal of the software voltage sampling circuit, and the output terminal of the controller is connected to the second input terminal of the monostable trigger circuit.

4. The bus voltage discharge device according to claim 1, characterized in that, The upper limit voltage comparison circuit includes a first comparator, the positive input terminal of the first comparator is connected to the output terminal of the upper limit reference voltage generation circuit, the negative input terminal of the first comparator is connected to the output terminal of the first DC bus voltage sampling circuit, and the output terminal of the first comparator is connected to the monostable trigger circuit.

5. The bus voltage discharge device according to claim 4, characterized in that, A first positive feedback resistor is connected between the positive input terminal and the output terminal of the first comparator.

6. The bus voltage discharge device according to claim 2, characterized in that, The lower limit voltage comparison circuit includes a second comparator. The positive input terminal of the second comparator is connected to the output terminal of the second DC bus voltage sampling circuit, the negative input terminal of the second comparator is connected to the output terminal of the lower limit reference voltage generation circuit, and the output terminal of the second comparator is connected to the monostable trigger circuit.

7. The bus voltage discharge device according to claim 6, characterized in that, A second positive feedback resistor is connected between the positive input terminal and the output terminal of the second comparator.

8. The bus voltage discharge device according to claim 1, characterized in that, The monostable trigger circuit includes a monostable trigger chip and an RC adjustment circuit. The RC adjustment circuit includes an adjustment resistor and an adjustment capacitor. The adjustment resistor is connected between the pull-up power supply and the first terminal of the adjustment capacitor. The first terminal of the adjustment capacitor is connected to the external resistor input terminal of the monostable trigger chip, and the second terminal of the adjustment capacitor is connected to the external capacitor input terminal of the monostable trigger chip. The resistance value of the adjustment resistor and the capacitance value of the adjustment capacitor are set according to a preset discharge time.

9. The bus voltage discharge device according to claim 1, characterized in that, The first DC bus voltage sampling circuit includes a first voltage divider resistor and a second voltage divider resistor. The first voltage divider resistor and the second voltage divider resistor are connected in series between the positive DC bus and the negative DC bus. The first end of the first voltage divider resistor is connected to the first end of the second voltage divider resistor, the second end of the second voltage divider resistor is connected to the negative DC bus, and the first end of the first voltage divider resistor is connected to the output terminal of the first DC bus voltage sampling circuit.

10. The bus voltage discharge device according to any one of claims 1 to 9, characterized in that, The upper limit reference voltage generation circuit includes a third voltage divider resistor and a fourth voltage divider resistor. The third voltage divider resistor and the fourth voltage divider resistor are connected in series between the positive and negative terminals of the standard voltage power supply. The first end of the third voltage divider resistor is connected to the first end of the fourth voltage divider resistor, the second end of the fourth voltage divider resistor is connected to the negative terminal of the standard voltage power supply, and the first end of the fourth voltage divider resistor is connected to the output terminal of the upper limit reference voltage generation circuit.

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