A kind of pressure-proof protection circuit, chip device, electronic equipment and vehicle
Patent Information
- Application Number
- CN202522128349.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-30
- Publication Date
- 2026-09-04
- Estimated Expiration
- 2035-09-30
AI Technical Summary
[0003]然而，由于非理想效应影响，常态工作时高压管的栅极易发生电荷积累，导致栅极电压失稳
[0039] In summary, the embodiments of this application, through the above technical solutions, use an active pull-down circuit to periodically pull down the gate voltage of the high-voltage metal-oxide-semiconductor transistor, thereby forcibly stabilizing the gate potential to ground potential when the controller area network chip is working normally, eliminating voltage fluctuations caused by charge accumulation, directly improving the stability of the gate-source voltage difference, thus significantly improving the reliability of the output stage current, and ultimately effectively enhancing the electromagnetic compatibility characteristics of the controller area network chip.
Smart Images
Figure CN224721587U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electrical protection technology, and in particular to a withstand voltage protection circuit, chip device, electronic device, and vehicle. Background Technology
[0002] The output stage of traditional Controller Area Network (CAN) bus interface chips typically uses high-voltage metal-oxide-semiconductor (MOS) transistors. To ensure the normal operation of these high-voltage MOS transistors, their gate-source voltage difference (VGS) must be strictly controlled. During normal chip operation, the gate voltage must be maintained at a stable ground potential; however, when a high-voltage signal is input, the gate voltage must follow the source potential change to keep VGS within acceptable limits.
[0003] However, due to non-ideal effects, charge accumulation easily occurs on the gate of the high-voltage transistor during normal operation, leading to gate voltage instability. This phenomenon directly disturbs the VGS setting, thereby affecting the drive current on the CANH side of the output stage. Traditional protection circuits cannot eliminate this charge accumulation in time, ultimately causing abnormal operation of the high-voltage transistor and deteriorating the common-mode characteristics of the chip. Utility Model Content
[0004] This application provides a withstand voltage protection circuit, a chip device, an electronic device, and a vehicle, which solves at least partially the above-mentioned technical problems by periodically pulling down the gate voltage of a high-voltage metal-oxide-semiconductor transistor through an active pull-down circuit.
[0005] To achieve the above objectives, according to a first aspect of this application, a withstand voltage protection circuit is provided, including an active pull-down circuit connected to the gate of a high-voltage metal-oxide-semiconductor transistor; wherein the high-voltage metal-oxide-semiconductor transistor is the output stage of a controller area network (Controller Area Network) chip; the active pull-down circuit stabilizes the gate voltage to ground potential through periodic pull-down operations when the Controller Area Network chip is operating normally.
[0006] Optionally, it also includes:
[0007] A resistor voltage divider circuit is connected in series between the gate terminal of the high-voltage metal-oxide-semiconductor tube and ground.
[0008] Optionally, the resistor divider circuit includes a first resistor and a second resistor;
[0009] The first end of the first resistor is connected to the gate terminal, and the second end is connected to the first end of the second resistor; the second end of the second resistor is grounded.
[0010] The connection node between the first resistor and the second resistor forms the first node.
[0011] Optionally, it also includes:
[0012] The detection and logic processing circuit has its input terminal connected to the first node and its output terminal connected to the active pull-down circuit.
[0013] Optionally, the detection and logic processing circuit includes:
[0014] Inverter, with its input connected to the first node;
[0015] The buffer has its input terminal connected to the output terminal of the inverter.
[0016] The first NAND gate has its first input connected to the output of the buffer and its second input connected to a short pulse signal.
[0017] The first NOT gate has its input connected to the output of the first NAND gate, and its output connected to the active pull-down circuit.
[0018] Optionally, the active pull-down circuit includes:
[0019] A high-voltage laterally diffused metal-oxide-semiconductor transistor, with its gate connected to the power supply voltage and its drain connected to the gate terminal of the high-voltage metal-oxide-semiconductor transistor;
[0020] An N-channel metal-oxide-semiconductor transistor has its gate connected to the output of the first NOT gate, its source grounded, and its drain connected to the source of the high-voltage laterally diffused metal-oxide-semiconductor transistor.
[0021] A capacitor is connected in parallel between the source of the high-voltage laterally diffused metal-oxide-semiconductor and ground.
[0022] Optionally, the active pull-down circuit includes:
[0023] The third resistor is connected to the gate terminal of the high-voltage metal-oxide-semiconductor transistor;
[0024] A high-voltage laterally diffused metal-oxide-semiconductor transistor, with its gate connected to the output terminal of the first NOT gate and its drain connected to the gate terminal of the high-voltage metal-oxide-semiconductor transistor through the third resistor;
[0025] A capacitor is connected in parallel between the drain of the high-voltage laterally diffused metal-oxide-semiconductor and ground.
[0026] Optionally, the detection and logic processing circuit includes:
[0027] The comparator has its positive input connected to a reference voltage and its negative input connected to the first node.
[0028] The second AND gate has its first input terminal connected to the output terminal of the comparator, and its second input terminal connected to an external short pulse signal.
[0029] The buffer has its input connected to the output of the second AND gate, and its output connected to the active pull-down circuit.
[0030] Optionally, the active pull-down circuit includes:
[0031] The third resistor is connected to the gate terminal of the high-voltage metal-oxide-semiconductor transistor;
[0032] A high-voltage laterally diffused metal-oxide-semiconductor transistor, with its gate connected to the output terminal of the buffer and its drain connected to the gate terminal of the high-voltage metal-oxide-semiconductor transistor through the third resistor;
[0033] A capacitor is connected in parallel between the drain of the high-voltage laterally diffused metal-oxide-semiconductor and ground.
[0034] According to a second aspect of this application, a chip device is provided, comprising:
[0035] The voltage-resistant protection circuit described in any of the embodiments of this application;
[0036] A high-voltage metal-oxide-semiconductor transistor, with its gate connected to the voltage protection circuit.
[0037] According to a third aspect of this application, an electronic device is provided, comprising a withstand voltage protection circuit as described in any one of the embodiments of this application, or a chip device as described in the embodiments of this application.
[0038] According to a fourth aspect of this application, a vehicle is also provided, including any of the withstand voltage protection circuits provided in the embodiments of this application, or the electronic devices provided in the embodiments of this application.
[0039] In summary, the embodiments of this application, through the above technical solutions, use an active pull-down circuit to periodically pull down the gate voltage of the high-voltage metal-oxide-semiconductor transistor, thereby forcibly stabilizing the gate potential to ground potential when the controller area network chip is working normally, eliminating voltage fluctuations caused by charge accumulation, directly improving the stability of the gate-source voltage difference, thus significantly improving the reliability of the output stage current, and ultimately effectively enhancing the electromagnetic compatibility characteristics of the controller area network chip.
[0040] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description
[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0042] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.
[0043] Figure 1 This is a schematic diagram of a withstand voltage protection circuit provided in an exemplary embodiment of this application;
[0044] Figure 2 This is a schematic diagram of the withstand voltage protection circuit connection provided in the exemplary first embodiment of this application;
[0045] Figure 3 This is a schematic diagram of the withstand voltage protection circuit connection provided in the exemplary second embodiment of this application;
[0046] Figure 4 This is a schematic diagram of the withstand voltage protection circuit connection provided in the exemplary third embodiment of this application;
[0047] Figure 5 This is a schematic diagram of the vehicle architecture provided in an exemplary embodiment of this application.
[0048] Explanation of reference numerals in the attached figures:
[0049] 10, 20, 30, 40, withstand voltage protection circuit;
[0050] 11, 21, 31, 41, Active pull-down circuits;
[0051] 12, 22, 32, 42, Detection and logic processing circuits;
[0052] 13, 23, 33, 43, resistor voltage divider circuit;
[0053] 40. Vehicles. Detailed Implementation
[0054] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.
[0055] This application provides a withstand voltage protection circuit; please refer to [link / reference]. Figure 1 , Figure 1 This is a schematic diagram of a withstand voltage protection circuit provided in an exemplary embodiment of this application.
[0056] The withstand voltage circuit is applied to the output stage of the CAN chip, wherein the output stage of the CAN chip includes a high-voltage MOSFET.
[0057] The withstand voltage protection circuit 10 includes an active pull-down circuit 11 connected to the gate of the high-voltage MOSFET.
[0058] When the CAN chip is working normally, the active pull-down circuit 11 pulls down the gate voltage of the high-voltage MOS transistor P1 to ground potential based on the refresh mechanism to stabilize the gate voltage and improve EMC characteristics; when a high-voltage event occurs, the active pull-down circuit 11 is turned off, so that the gate voltage changes with the source voltage.
[0059] In the embodiments of this application, by periodically pulling down the gate voltage of the high-voltage MOSFET through the active pull-down circuit, the gate potential is forced to stabilize to ground potential when the CAN chip is working normally, eliminating voltage fluctuations caused by charge accumulation, directly improving the stability of the gate-source voltage difference VGS, thereby significantly improving the reliability of the CANH side current of the output stage, and ultimately effectively enhancing the electromagnetic compatibility (EMC) characteristics of the CAN chip.
[0060] Please see Figure 2 , Figure 2 This is a schematic diagram of the withstand voltage protection circuit connection provided in the exemplary first embodiment of this application.
[0061] In some embodiments, the withstand voltage protection circuit 20 further includes:
[0062] The resistor divider circuit 23 is connected in series between the gate terminal of the high-voltage MOSFET and ground.
[0063] In some embodiments, the resistor divider circuit 23 includes a first resistor R1 and a second resistor R2;
[0064] The first end of the first resistor R1 is connected to the gate terminal, and the second end is connected to the first end of the second resistor R2; the second end of the second resistor R2 is grounded.
[0065] The connection node between the first resistor R1 and the second resistor R2 forms the first node.
[0066] In some embodiments, the withstand voltage protection circuit 20 further includes:
[0067] The detection and logic processing circuit 22 has its input terminal connected to the first node and its output terminal connected to the active pull-down circuit 21.
[0068] The resistor divider circuit 23 is connected in series between the gate terminal of the high-voltage MOSFET P1 and ground to generate the node voltage VC, which characterizes the gate voltage; that is, the node voltage VC is generated at the first node. The input terminal of the detection and logic processing circuit 22 is connected to the first node, and the output terminal generates a pull-down control signal for controlling the active pull-down circuit 21.
[0069] In some embodiments, the detection and logic processing circuit 22 includes:
[0070] Inverter I1, its input is connected to the first node;
[0071] Buffer I2, its input is connected to the output of inverter I1;
[0072] The first NAND gate I3 has its first input connected to the output of buffer I2, and its second input connected to a short pulse signal CLKN.
[0073] The input of the first NOT gate I4 is connected to the output of the first NAND gate I3, and the output is connected to the active pull-down circuit 21.
[0074] In some embodiments, the active pull-down circuit 21 includes:
[0075] The high-voltage LDMOS transistor N1 has its gate connected to the power supply voltage and its drain connected to the gate terminal of the high-voltage MOS transistor P1.
[0076] The N-channel MOSFET NM2 has its gate connected to the output terminal of the first NOT gate I4, its source grounded, and its drain connected to the source of the high-voltage LDMOS transistor N1.
[0077] Capacitor C1 is connected in parallel between the source of the high-voltage LDMOS transistor N1 and ground.
[0078] The node voltage VC is R2 / (R1+R2). The detection and logic processing circuit 22 detects the node voltage VC to obtain information about the gate voltage of the high-voltage MOSFET P1. Under normal operating conditions of the CAN chip, the node voltage VC is much lower than the threshold voltage of the detection circuit; however, when a high-voltage event occurs, the node voltage VC will also increase.
[0079] When the CAN chip is operating normally, the node voltage VC is much lower than the trigger threshold of inverter I1. Therefore, inverter I1 outputs a high-level signal, which, after being processed by buffer I2, is input to the first NAND gate I3 along with a brief pulse signal CLKN. The output is then processed by the first NOT gate I4 to obtain a brief pulse signal. When a high-voltage signal appears on the CAN bus, the node voltage VC is greater than the trigger threshold of inverter I1. Therefore, inverter I1 outputs a low-level signal, which, after being processed by buffer I2, is input to the first NAND gate I3 along with the brief pulse signal CLKN. The output is then processed by the first NOT gate I4 to obtain a low-level signal.
[0080] The first NAND gate I3 and the first NOT gate I4 form a logic gate chain. When the CAN chip is operating normally (node voltage VC is lower than the trigger threshold of inverter I1), the detection and logic processing circuit 22 outputs a brief pulse signal of the pull-down control signal as described above to activate the active pull-down circuit 21. The N-channel MOSFET NM2 turns on in response to the brief pulse signal of the pull-down control signal, and the high-voltage LDMOS transistor N1 periodically pulls down the gate voltage to a stable ground potential VGS. In the event of a high-voltage input event to the CAN chip (node voltage VC is higher than the threshold of inverter I1), the detection and logic processing circuit 22 outputs a low-level signal as described above to turn off the active pull-down circuit 21, turn off the N-channel NMOS transistor NM2, and thus turn off the strong pull-down branch, thereby ensuring that the gate of the high-voltage power MOSFET P1 can float with the source terminal.
[0081] In the embodiments of this application, through the coordination of the resistor voltage divider circuit, the detection and logic processing circuit and the active pull-down circuit, the gate voltage can be greatly stabilized based on the refresh mechanism when the CAN chip is working normally, preventing some non-ideal effects from interfering with the gate and thus affecting the performance of the CAN chip; when a high voltage event occurs, the detection and logic processing circuit protects its high voltage MOSFET P1 by detecting the gate voltage and then shutting down the pull-down branch to prevent damage.
[0082] Please see Figure 3 , Figure 3 This is a schematic diagram of the withstand voltage protection circuit connection provided in the exemplary second embodiment of this application.
[0083] In some embodiments, the active pull-down circuit 31 includes:
[0084] The third resistor R3 is connected to the gate terminal of the high-voltage MOSFET P1;
[0085] The gate of the high-voltage LDMOS transistor N1 is connected to the output terminal of the first NOT gate I4, and the drain is connected to the gate terminal of the high-voltage MOS transistor P1 through the third resistor R3.
[0086] Capacitor C1 is connected in parallel between the drain of the high-voltage LDMOS transistor N1 and ground.
[0087] When the CAN chip is working normally, the active pull-down circuit 31 is activated by the N-channel MOS transistor NM2 in response to the brief pulse of the pull-down control signal, and the high-voltage LDMOS transistor N1 periodically pulls down the gate voltage to the ground potential to stabilize VGS. When the node VC exceeds the threshold, the pull-down control signal turns off the active pull-down circuit so that the gate voltage floats with the source voltage.
[0088] It should be noted that under normal CAN chip operation, the third resistor R3 employs a small resistance value to provide strong pull-down capability, achieving milliamp-level discharge current. This ensures that the gate charge is quickly cleared during the dominant / recessive transition, thereby stabilizing the gate voltage and suppressing EMC noise. When a sudden high-voltage event occurs on the CAN bus, the small resistor R3 causes the drain of the switching transistor to withstand approximately the full bus voltage. At this time, the NLDMOS transistor N1, with its vertical withstand voltage structure, provides higher voltage breakdown protection, replacing the N-channel MOS transistor to avoid drain-source breakdown failure. The small resistor ensures the dynamic stability of the gate voltage, and the NLDMOS ensures reliability under high-voltage conditions.
[0089] The components, connections, and functional implementation methods of the detection and logic processing circuit 32 and the resistor voltage divider circuit 33 in the withstand voltage protection circuit 30 described in this embodiment are the same as those in the previous embodiments. Figure 2 The content described in the relevant instructions is completely consistent with the information provided. For specific technical details, please refer directly. Figure 2 The corresponding textual explanations will not be repeated here.
[0090] Please see Figure 4 , Figure 4 This is a schematic diagram of the withstand voltage protection circuit connection provided in the exemplary third embodiment of this application.
[0091] In some embodiments, the detection and logic processing circuit 42 includes:
[0092] Comparator COMP1 has its positive input connected to the reference voltage VREF and its negative input connected to the first node.
[0093] The second AND gate I5 has its first input connected to the output of COMP1 and its second input connected to an external short pulse signal CLKN.
[0094] Buffer I2 has its input connected to the output of the second AND gate I5, and its output connected to the active pull-down circuit 41.
[0095] In some embodiments, the active pull-down circuit 41 includes:
[0096] The third resistor R3 is connected to the gate terminal of the high-voltage MOSFET P1;
[0097] The gate of the high-voltage LDMOS transistor N1 is connected to the output terminal of the buffer I2, and the drain is connected to the gate terminal of the high-voltage MOS transistor P1 through the third resistor R3.
[0098] Capacitor C1 is connected in parallel between the drain of the high-voltage LDMOS transistor N1 and ground.
[0099] The comparator COMP1 compares the node voltage VC with the reference voltage VREF:
[0100] When the CAN chip is working normally, the node voltage VC obtained by the resistor voltage divider circuit 43, if the node voltage VC does not exceed the reference voltage VREF, the comparator COMP1 outputs a high-level signal, and performs an AND operation with the short pulse signal in the second AND gate I5 and outputs a short pulse signal, which is then output to the active pull-down circuit 41 through the buffer I2 to activate the active pull-down circuit 41.
[0101] When a high voltage signal appears on the CAN chip bus, the node voltage VC obtained by the resistor voltage divider circuit 43 will gradually increase. When the node voltage VC exceeds the reference voltage VREF, the comparator COMP1 outputs a low-level signal and performs an AND operation with the short pulse signal CLKN in the second AND gate I5 to output a low-level signal. After passing through the buffer I2, the signal is output to the active pull-down circuit 41 to turn off the active pull-down circuit 41.
[0102] The components, connections, and functional implementation of the resistor divider circuit 43 in the withstand voltage protection circuit 40 described in this embodiment are the same as those in the previous embodiments. Figure 2 The content described in the relevant instructions is completely consistent with the information provided. For specific technical details, please refer directly. Figure 2 The corresponding textual explanations will not be repeated here.
[0103] The active pull-down circuit consists of a high-voltage LDMOS transistor N1, a third resistor R3, and a capacitor C1. When the CAN chip is operating normally, a brief pulse signal sent by the detection and logic processing circuit briefly turns on the high-voltage LDMOS transistor N1, strongly pulling down the gate voltage of the high-voltage MOS transistor P1 to stabilize it at ground potential. When a high-voltage event occurs in the CAN chip, a low-level signal sent by the detection and logic processing circuit turns off the high-voltage LDMOS transistor N1, thereby disabling the active pull-down circuit, allowing the gate voltage of the high-voltage MOS transistor to change in sync with the source voltage.
[0104] One or more embodiments of this specification also provide a chip device, comprising:
[0105] The voltage protection circuit provided in the embodiments of this application;
[0106] The high-voltage MOSFET has its gate connected to the voltage protection circuit.
[0107] The chip device has all the beneficial effects of the aforementioned voltage protection circuit, which will not be repeated here.
[0108] One or more embodiments of this specification also provide an electronic device including the withstand voltage protection circuit provided in the embodiments of this application, wherein the withstand voltage protection circuit is applied to the output stage of a CAN chip to stabilize the gate voltage and improve the EMC characteristics of the CAN chip. This electronic device possesses all the beneficial effects of the aforementioned withstand voltage protection circuit, which will not be elaborated upon further herein.
[0109] like Figure 5 The diagram shown is a schematic representation of a vehicle architecture provided in an embodiment of this application. In this embodiment, the vehicle includes the aforementioned electronic equipment, or any of the voltage withstand protection provided in the embodiments of this application. In this embodiment, the vehicle may be a gasoline-powered vehicle, a plug-in hybrid electric vehicle, or a new energy vehicle, etc., and this disclosure does not specifically limit it in this way.
[0110] The vehicle has all the beneficial effects of the aforementioned withstand voltage protection circuit, which will not be elaborated further in this disclosure.
[0111] In some embodiments, the vehicle can be configured in a fully or partially autonomous driving mode. For example, the vehicle can control itself while in autonomous driving mode, and can determine the current state of the vehicle and its surrounding environment through human intervention, determine the possible behaviors of at least one other vehicle in the surrounding environment, and determine the confidence level corresponding to the probability of that other vehicle performing the possible behavior, and control the vehicle based on the determined information. When the vehicle is in autonomous driving mode, it can be positioned to operate without human interaction.
[0112] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0113] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0114] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0115] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A withstand voltage protection circuit, characterized in that, It includes an active pull-down circuit connected to the gate of a high-voltage metal-oxide-semiconductor transistor; wherein the high-voltage metal-oxide-semiconductor transistor is the output stage of a controller area network (CLAN) chip; the active pull-down circuit stabilizes the gate voltage to ground potential through periodic pull-down operations when the CLAN chip is operating normally.
2. The withstand voltage protection circuit according to claim 1, characterized in that, Also includes: A resistor voltage divider circuit is connected in series between the gate terminal of the high-voltage metal-oxide-semiconductor tube and ground.
3. The withstand voltage protection circuit according to claim 2, characterized in that, The resistor voltage divider circuit includes a first resistor and a second resistor; The first end of the first resistor is connected to the gate terminal, and the second end is connected to the first end of the second resistor; the second end of the second resistor is grounded. The connection node between the first resistor and the second resistor forms the first node.
4. The withstand voltage protection circuit according to claim 3, characterized in that, Also includes: The detection and logic processing circuit has its input terminal connected to the first node and its output terminal connected to the active pull-down circuit.
5. The withstand voltage protection circuit according to claim 4, characterized in that, The detection and logic processing circuit includes: Inverter, with its input connected to the first node; The buffer has its input terminal connected to the output terminal of the inverter. The first NAND gate has its first input connected to the output of the buffer and its second input connected to a short pulse signal. The first NOT gate has its input connected to the output of the first NAND gate, and its output connected to the active pull-down circuit.
6. The withstand voltage protection circuit according to claim 5, characterized in that, The active pull-down circuit includes: A high-voltage laterally diffused metal-oxide-semiconductor transistor, with its gate connected to the power supply voltage and its drain connected to the gate terminal of the high-voltage metal-oxide-semiconductor transistor; An N-channel metal-oxide-semiconductor transistor has its gate connected to the output of the first NOT gate, its source grounded, and its drain connected to the source of the high-voltage laterally diffused metal-oxide-semiconductor transistor. A capacitor is connected in parallel between the source of the high-voltage laterally diffused metal-oxide-semiconductor and ground.
7. The withstand voltage protection circuit according to claim 5, characterized in that, The active pull-down circuit includes: The third resistor is connected to the gate terminal of the high-voltage metal-oxide-semiconductor transistor; A high-voltage laterally diffused metal-oxide-semiconductor transistor, with its gate connected to the output terminal of the first NOT gate and its drain connected to the gate terminal of the high-voltage metal-oxide-semiconductor transistor through the third resistor; A capacitor is connected in parallel between the drain of the high-voltage laterally diffused metal-oxide-semiconductor and ground.
8. The withstand voltage protection circuit according to claim 4, characterized in that, The detection and logic processing circuit includes: The comparator has its positive input connected to a reference voltage and its negative input connected to the first node. The second AND gate has its first input terminal connected to the output terminal of the comparator, and its second input terminal connected to an external short pulse signal. The buffer has its input connected to the output of the second AND gate, and its output connected to the active pull-down circuit.
9. The withstand voltage protection circuit according to claim 8, characterized in that, The active pull-down circuit includes: The third resistor is connected to the gate terminal of the high-voltage metal-oxide-semiconductor transistor; A high-voltage laterally diffused metal-oxide-semiconductor transistor, with its gate connected to the output terminal of the buffer and its drain connected to the gate terminal of the high-voltage metal-oxide-semiconductor transistor through the third resistor; A capacitor is connected in parallel between the drain of the high-voltage laterally diffused metal-oxide-semiconductor and ground.
10. A chip device, characterized in that, include: The withstand voltage protection circuit as described in any one of claims 1 to 9; A high-voltage metal-oxide-semiconductor transistor, with its gate connected to the voltage protection circuit.
11. An electronic device, characterized in that, It includes a withstand voltage protection circuit as described in any one of claims 1 to 9, or a chip device as described in claim 10.
12. A vehicle, characterized in that, Includes the electronic device as described in claim 11, or the withstand voltage protection circuit as described in any one of claims 1 to 9.