H-bridge driving structure with soft switching

Abstract

The application relates to the technical field of electronic circuits, and provides an H-bridge driving structure with soft switching, which comprises an H-bridge power unit, a complementary control unit and a signal generation unit.The H-bridge power unit comprises two bridge arms, and a load is connected between the two bridge arms.The complementary control unit comprises a plurality of P-type and N-type MOS tubes.The signal generation unit is used for generating two pairs of complementary control signals to drive the complementary control unit in response to an input signal.The signal generation unit comprises a first comparator and a second comparator, and the internal circuits of the first comparator and the second comparator are integrated with a current mirror network.The current mirror network is used for generating and outputting two pairs of complementary control signals according to the level state of the input signal through the proportional relationship of the current mirror network, and the on-off state of corresponding high-voltage devices in the complementary control unit is controlled, so that the gate driving current of corresponding switch tubes in the H-bridge power unit is adjusted to realize soft switching operation.The application is simple and mute, has no burr, shortens the total switching time, and reduces the total switching power loss.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and specifically to an H-bridge drive structure with soft switching. Background Technology

[0002] In DC motor applications, the H-bridge is a typical circuit. It's named "H-bridge" because its circuit shape resembles the letter H. An H-bridge allows the voltage across its connected load or output terminals to be reversed. This type of circuit can be used for forward and reverse control and speed control of DC motors, stepper motor control (bipolar stepper motors require a motor controller with two H-bridges), most DC-AC converters in power conversion (such as inverters and frequency converters), some DC-DC converters (push-pull converters), and other high-current power applications such as power electronic devices.

[0003] In conventional H-bridge structures, during application switching, the current cannot change abruptly. When the switch is turned off, a very large back electromotive force is generated to prevent the current from decreasing. During the switching process, the reverse current will generate sharp spikes that appear at the output or power supply terminals. It is not possible to design an H-bridge that can easily drive and eliminate the back electromotive force. Utility Model Content

[0004] To help solve the above-mentioned technical problems, this application provides an H-bridge drive structure with soft switching.

[0005] This application provides an H-bridge drive structure with soft switching, which adopts the following technical solution: An H-bridge drive structure with soft switching, comprising: The H-bridge power unit includes two bridge arms. Each bridge arm consists of an upper bridge arm switch and a lower bridge arm switch connected in series and connected in parallel between the positive terminal of the power supply and ground. The load is connected between the two bridge arms. The complementary control unit includes multiple P-type and N-type MOS transistors, used to control the gates of corresponding switches in the H-bridge power unit according to the received complementary signals; A signal generation unit is used to generate two pairs of complementary control signals in response to an input signal to drive the complementary control unit. The signal generation unit includes a first comparator and a second comparator. The internal circuits of the first comparator and the second comparator are both integrated with a current mirror network. The two pairs of complementary control signals are generated and output according to the level state of the input signal and the proportional relationship of the current mirror network to control the conduction state of the corresponding high-voltage device in the complementary control unit, so as to adjust the gate drive current of the corresponding switch in the H-bridge power unit to achieve soft switching operation.

[0006] Preferably, the H-bridge power unit includes a first upper bridge arm switch, a first lower bridge arm switch, a second upper bridge arm switch, and a second lower bridge arm switch. The first upper bridge arm switch and the first lower bridge arm switch are connected in series to form a first bridge arm, and the second upper bridge arm switch and the second lower bridge arm switch are connected in series to form a second bridge arm. The first bridge arm and the second bridge arm are connected in parallel between the positive terminal of the power supply and ground, and the load is connected between the first bridge arm and the second bridge arm.

[0007] Preferably, the complementary control unit includes four P-type MOS transistors p1, p2, p3, p4 and four N-type MOS transistors n1, n2, n3, n4. The gates of P-type MOS transistor p1 and N-type MOS transistor n1 receive complementary signals and are used to control the gates of the first upper bridge arm switch. The gates of P-type MOS transistor p2 and N-type MOS transistor n2 receive complementary signals and are used to control the gates of the second upper bridge arm switch. The gates of P-type MOS transistor p3 and N-type MOS transistor n3 receive complementary signals and are used to control the gates of the first lower bridge arm switch. The gates of P-type MOS transistor p4 and N-type MOS transistor n4 receive complementary signals and are used to control the gates of the second lower bridge arm switch.

[0008] Preferably, the first comparator is configured to be enabled when the input signal is high, and to generate complementary signals VO1 and VO2 through an internal current mirror network. The internal current mirror network of the first comparator includes a combination of one or more of MOSFETs p7, p8, p9, n11, n12, n13, and n14.

[0009] Preferably, the first comparator in the signal generation unit includes: A cascaded amplifier structure consisting of P-type MOSFETs p7, p8, p9 and N-type MOSFETs n11, n12, n13, n14, wherein: The source of p7 is connected to the power supply voltage Vdd, and the drain is connected to the drain and gate of n11. The sources of p8 and p9 are both connected to Vdd, and the drains output the complementary signal VO1 and the complementary signal VO2, respectively. The sources of n11 and n12 are grounded, and the sources of n13 and n14 are connected to the drain of n12. The source of n13 is connected to the input signal IN2, and the drain is connected to the drain of p8 and VO1. The source of n14 is connected to the input signal IN1, and the drain is connected to the drain of p9 and VO2. The current mirror network consists of p7 and n11, n12, and is used to establish a bias current reference. Input signal IN2 controls the output of VO1 through n13, and input signal IN1 controls the output of VO2 through n14.

[0010] Preferably, the second comparator is configured to be enabled when the input signals IN1 and IN2 are low, and to generate complementary signals VO1 and VO2 through an internal current mirror network. The internal current mirror network of the second comparator includes a combination of one or more of MOSFETs p10, p11, p12, p13, n15, and n16.

[0011] Preferably, the second comparator in the signal generation unit includes: A differential amplifier structure consisting of P-type MOSFETs p10, p11, p12, p13 and N-type MOSFETs n15, n16, wherein: The source of p10 is connected to the power supply voltage Vdd, the source of p11 is connected to Vdd, the drain is connected to the source of p12 and p13, and the gate is connected to the drain of p10. The gates of p12 and p13 are connected to the input signals IN1 and IN2, respectively, and their drains are connected to the drains of n15 and n16, respectively. The sources of n15 and n16 are grounded, and their drains output complementary signals VO1 and VO2, respectively. The current mirror network consists of p10 and p11, which matches the input current of p12 and p13 by mirroring the current. The input signals IN1 and IN2 are differentially amplified by p12 and p13, and then level conversion is achieved by n15 and n16.

[0012] Preferably, each switch in the H-bridge power unit has a freewheeling diode connected in reverse parallel across its terminals.

[0013] In summary, this application provides a simple, quiet, burr-free switch drive circuit with good performance and a reasonable and advanced structure, which enables most power electronic devices to operate stably in a relatively stable and ideal switching state, thereby reducing the total switching time and the total switching power loss. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the overall structure of an H-bridge drive structure with soft switching according to this application; Figure 2 for Figure 1 The internal structure diagram of comp2 in the embodiment shown is shown. Figure 3 for Figure 1 The internal structure diagram of comp3 in the embodiment shown is shown. Figure 4 for Figure 1 The illustrated embodiment shows a schematic diagram of the output waveforms of VOUT1 / VOUT2. Detailed Implementation

[0015] The present application will be further described below with reference to the accompanying drawings. The structure and principle of the present application are very clear to those skilled in the art. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

[0016] The prior art, referred to in this application as hard switching, involves the switching transistor forcibly traversing the linear region (amplification region) under conditions of simultaneously high voltage and large current. This generates significant instantaneous power, resulting in switching losses. The higher the switching frequency, the larger the proportion of these losses in the total losses, leading to low efficiency and severe heat generation. Furthermore, in hard switching, the rapid turn-off of the switching transistor generates a large voltage spike due to the parasitic inductance of the circuit. This spike not only wastes energy but is also a major source of noise and electromagnetic interference, potentially damaging devices or affecting the normal operation of other parts of the system.

[0017] This application employs soft switching, which creates specific conditions so that when the power switch is turned on, the voltage across it has dropped to zero, and when it is turned off, the current flowing through it has dropped to zero. By performing switching operations under these "zero voltage" or "zero current" conditions, switching losses can be almost eliminated and electromagnetic interference generated during the switching process can be suppressed.

[0018] Figure 1 This is a schematic diagram of the overall structure of an H-bridge drive structure with soft switching according to this application. Figure 2 for Figure 1 The diagram shows the internal structure of comp2 in the embodiment shown. Figure 3 for Figure 1 A schematic diagram of the internal structure of comp3 in the embodiment shown.

[0019] Combination Figures 1 to 3 It is understood that an H-bridge drive structure with soft switching according to this application includes: The H-bridge power unit includes two bridge arms. Each bridge arm consists of an upper bridge arm switch and a lower bridge arm switch connected in series and connected in parallel between the positive terminal of the power supply and ground. The load is connected between the two bridge arms. The complementary control unit includes multiple P-type and N-type MOS transistors, used to control the gates of corresponding switches in the H-bridge power unit according to the received complementary signals; A signal generation unit is used to generate two pairs of complementary control signals in response to an input signal to drive the complementary control unit. The signal generation unit includes a first comparator and a second comparator. The internal circuits of the first comparator and the second comparator are both integrated with a current mirror network. The two pairs of complementary control signals are generated and output according to the level state of the input signal and the proportional relationship of the current mirror network to control the conduction state of the corresponding high-voltage device in the complementary control unit, so as to adjust the gate drive current of the corresponding switch in the H-bridge power unit to achieve soft switching operation.

[0020] H-bridge circuits generate glitches primarily because when the MOSFET turns off, the current through the load cannot be immediately interrupted, and the inductor current cannot change abruptly, resulting in a very large reverse electromotive force voltage that prevents the current from decreasing. According to the formula u=-Ldi / dt, the larger di / dt is, the higher the spike generated at the drain. To reduce these spikes, we can consider the following aspects: 1. The current before the MOSFET turns off; 2. The switching speed; 3. The inductance in the circuit (including parasitic inductance). In a switching circuit composed of PMOS and NMOS transistors, a large current is generated when both PMOS and NMOS are in saturation at a certain moment. Otherwise, the current is extremely small. Here, we add a current source to control this large current, reducing it, extending the switching turn-on speed, decreasing di / dt, and thus reducing the glitches.

[0021] In this embodiment, the H-bridge power unit includes a first upper bridge arm switch, a first lower bridge arm switch, a second upper bridge arm switch, and a second lower bridge arm switch. The first upper bridge arm switch and the first lower bridge arm switch are connected in series to form a first bridge arm, and the second upper bridge arm switch and the second lower bridge arm switch are connected in series to form a second bridge arm. The first bridge arm and the second bridge arm are connected in parallel between the positive terminal of the power supply and ground, and the load is connected between the first bridge arm and the second bridge arm.

[0022] In this embodiment, the complementary control unit includes four P-type MOS transistors p1, p2, p3, p4 and four N-type MOS transistors n1, n2, n3, n4. The gates of P-type MOS transistor p1 and N-type MOS transistor n1 receive complementary signals and are used to control the gates of the first upper bridge arm switch. The gates of P-type MOS transistor p2 and N-type MOS transistor n2 receive complementary signals and are used to control the gates of the second upper bridge arm switch. The gates of P-type MOS transistor p3 and N-type MOS transistor n3 receive complementary signals and are used to control the gates of the first lower bridge arm switch. The gates of P-type MOS transistor p4 and N-type MOS transistor n4 receive complementary signals and are used to control the gates of the second lower bridge arm switch.

[0023] In this embodiment of the application, the first comparator is configured to be enabled when the input signal is high, and to generate complementary signals VO1 and VO2 through an internal current mirror network. The internal current mirror network of the first comparator includes a combination of one or more of MOS transistors p7, p8, p9, n11, n12, n13, and n14.

[0024] Specifically, the first comparator in the signal generation unit includes: A cascaded amplifier structure consisting of P-type MOSFETs p7, p8, p9 and N-type MOSFETs n11, n12, n13, n14, wherein: The source of p7 is connected to the power supply voltage Vdd, and the drain is connected to the drain and gate of n11. The sources of p8 and p9 are both connected to Vdd, and the drains output the complementary signal VO1 and the complementary signal VO2, respectively. The sources of n11 and n12 are grounded, and the sources of n13 and n14 are connected to the drain of n12. The source of n13 is connected to the input signal IN2, and the drain is connected to the drain of p8 and VO1. The source of n14 is connected to the input signal IN1, and the drain is connected to the drain of p9 and VO2. The current mirror network consists of p7 and n11, n12, and is used to establish a bias current reference. Input signal IN2 controls the output of VO1 through n13, and input signal IN1 controls the output of VO2 through n14.

[0025] This structure dynamically adjusts the drain current of p8 and p9 through a current mirror network, making the rise / fall slope of the output signals VO1 and VO2 adjustable. This allows for precise control of the conduction speed of the high-voltage MOSFET in the complementary control unit, achieving flexible adjustment of the gate drive current and effectively suppressing the reverse electromotive force and voltage glitches during the switching process.

[0026] In this embodiment of the application, the second comparator is configured to be enabled when the input signals IN1 and IN2 are low, and to generate complementary signals VO1 and VO2 through an internal current mirror network. The internal current mirror network of the second comparator includes a combination of one or more of the MOS transistors p10, p11, p12, p13, n15, and n16.

[0027] The second comparator in the signal generation unit includes: A differential amplifier structure consisting of P-type MOSFETs p10, p11, p12, p13 and N-type MOSFETs n15, n16, wherein: The source of p10 is connected to the power supply voltage Vdd, the source of p11 is connected to Vdd, the drain is connected to the source of p12 and p13, and the gate is connected to the drain of p10. The gates of p12 and p13 are connected to the input signals IN1 and IN2, respectively, and their drains are connected to the drains of n15 and n16, respectively. The sources of n15 and n16 are grounded, and their drains output complementary signals VO1 and VO2, respectively. The current mirror network consists of p10 and p11, which matches the input current of p12 and p13 by mirroring the current. The input signals IN1 and IN2 are differentially amplified by p12 and p13, and then level conversion is achieved by n15 and n16.

[0028] This structure dynamically adjusts the bias currents of p12 and p13 through a current mirror network, making the response speed of output signals VO1 and VO2 adjustable. This allows for precise control of the switching transient characteristics of the high-voltage MOSFET in the complementary control unit, achieving linear regulation of the gate drive current and effectively suppressing voltage overshoot and electromagnetic interference during the switching process.

[0029] In this embodiment, each switch in the H-bridge power unit is connected in reverse parallel across its terminals with a freewheeling diode. The freewheeling diode provides a preset low-impedance release path for the induced current. When the switch is turned off, the induced current naturally continues to flow through this parallel diode, thereby clamping the voltage across the switch at the level of the power supply voltage plus the forward voltage drop of the diode (typically Vdd + 0.7V), effectively absorbing energy, suppressing voltage spikes, and protecting the switch.

[0030] The soft switch consists of two parts. The middle part is an H-bridge structure, consisting of switching transistors a1, a2, a3, and a4, and diodes z1, z2, z3, and z4. Switches a1 and a3 form the left arm of the H-bridge, with a1 as the upper switch and a3 as the lower switch. Switches a2 and a4 form the right arm of the H-bridge, with a2 as the upper switch and a4 as the lower switch. The other part consists of high-voltage p-transistors p1, p2, p3, p4, and high-voltage n-transistors n1, n2, n3, n4. High-voltage p-transistors p1 and n-transistors n1 complementarily control switch a1; high-voltage p-transistors p2 and n-transistors n2 complementarily control switch a2; high-voltage p-transistors p3 and n-transistors n3 complementarily control switch a3; and high-voltage p-transistors p4 and n-transistors n4 complementarily control switch a4.

[0031] On the left side, the high-voltage p-pipe p1 controlling a1 is connected to the high-voltage p-pipe controlling a2, and the high-voltage n-pipe n2 controlling a2 is connected to the high-voltage n-pipe n2 controlling a2. On the right side, the high-voltage p-pipe p3 controlling a3 is connected to the high-voltage p-pipe controlling a3, and the high-voltage p-pipe p4 controlling a4 is connected to the high-voltage p-pipe controlling a4.

[0032] When inputs IN1 and IN2 are high, comp3 stops working and outputs a low level. The comp2 output V02 drives p1 through the ratios of current mirrors n11 and n12, p8 and p1, and drives p2 through the ratios of current mirrors n11 and n12, p8 and p2. The comp2 output V01 drives n1 through the ratios of current mirrors n11 and n12, p9 and p5, n5 and n1, and drives n2 through the ratios of current mirrors n11 and n12, p9 and p5, n5 and n2.

[0033] When inputs IN1 and IN2 are low, comp2 stops working. In comp3, output V02 drives p1 through the ratios of current mirrors p10 and p11, n15 and n7, n11 and n12, and p8 and p1, and drives p2 through the ratios of current mirrors p10 and p11, n15 and n7, n11 and n12, and p8 and p2. Output V01 of comp3 drives n1 through the ratios of current mirrors p10 and p11, n12 and p6, p9 and p5, and n5 and n1, and drives n2 through the ratios of current mirrors p10 and p11, n12, p6, p9 and p5, and n5 and n2.

[0034] Figure 4 for Figure 1 The schematic diagram of the output waveforms of VOUT1 / VOUT2 in the illustrated embodiment shows the time axis on the horizontal axis and the voltage amplitude on the vertical axis. VOUT1 and VOUT2 present inverted square wave signals, with the voltage amplitude stable between the power supply voltage Vdd and ground level, without any obvious voltage overshoot or glitches. The rising and falling edges of the two signals are symmetrical in time and their steepness is controllable, indicating that the switching transistors in the H-bridge power unit achieve synchronous turn-on / turn-off under soft-switching control.

[0035] When the input signal is high, the first comparator is enabled, and a complementary control signal is generated through its internal current mirror network. When the input signal is low, the second comparator is enabled, and a complementary control signal is generated through its internal current mirror network. The complementary control signal is output to the complementary control unit to drive the internal P-type and N-type MOS transistors; the complementary control unit adjusts the drive current applied to the gate of the corresponding switch in the H-bridge power unit. The magnitude of the drive current is set by controlling the ratio of the current mirror network. In this embodiment, the ratio of the current mirror network can be set by adjusting the aspect ratio of the mirror MOSFETs, including p8, p9, n12, n13, n14; and p11, p12, p13, n15, n16. By controlling the ratio of the current mirror network to set the magnitude of the drive current, the turn-on and turn-off process of the switching transistor is delayed, the rate of current change during the switching process is reduced, and soft-switching operation is achieved to suppress voltage spikes.

[0036] The complementary control unit consists of a pair of high-voltage P-type MOS transistors (such as p1) and high-voltage N-type MOS transistors (such as n1), which jointly control the gate of a main switch (such as a1). The "complementarity" is reflected in two aspects: first, the voltage of the control signal itself is complementary; second, the complementary electrical characteristics of the P-MOS and N-MOS devices are utilized to achieve fast and powerful charging and discharging control of the gate of the subsequent stage.

[0037] The specific control process is divided into two scenarios. When the main switch a1 needs to be turned off, the signal generation unit outputs a high level to the gate of p1 and a low level to the gate of n1 to the complementary pair. The high-voltage P-MOS transistor p1 remains off under the high-level gate signal, cutting off the charging path from the power supply to the gate of a1. Simultaneously, the high-voltage N-MOS transistor n1 turns on under the low-level gate signal, providing a low-impedance discharge path to ground for the gate capacitor charge of a1, thereby rapidly pulling down its gate voltage and achieving fast turn-off. Conversely, when the main switch a1 needs to be turned on, the complementary signal pair flips, becoming a low level to the gate of p1 and a high level to the gate of n1. At this time, n1 is off, cutting off the discharge path; while p1 is on, establishing a low-impedance charging path from the power supply to the gate of a1. The current rapidly charges the gate capacitor, causing its voltage to rise rapidly to the turn-on threshold, achieving fast turn-on.

Claims

1. An H-bridge drive structure with soft switching, characterized in that, include: The H-bridge power unit includes two bridge arms. Each bridge arm consists of an upper bridge arm switch and a lower bridge arm switch connected in series and connected in parallel between the positive terminal of the power supply and ground. The load is connected between the two bridge arms. The complementary control unit includes multiple P-type and N-type MOS transistors, used to control the gates of corresponding switches in the H-bridge power unit according to the received complementary signals; A signal generation unit is used to generate two pairs of complementary control signals in response to an input signal to drive the complementary control unit. The signal generation unit includes a first comparator and a second comparator. The internal circuits of the first comparator and the second comparator are both integrated with a current mirror network. The two pairs of complementary control signals are generated and output according to the level state of the input signal and the proportional relationship of the current mirror network to control the conduction state of the corresponding high-voltage device in the complementary control unit, so as to adjust the gate drive current of the corresponding switch in the H-bridge power unit to achieve soft switching operation.

2. The H-bridge drive structure with soft switching according to claim 1, characterized in that, The H-bridge power unit includes a first upper bridge arm switch, a first lower bridge arm switch, a second upper bridge arm switch, and a second lower bridge arm switch. The first upper bridge arm switch and the first lower bridge arm switch are connected in series to form a first bridge arm, and the second upper bridge arm switch and the second lower bridge arm switch are connected in series to form a second bridge arm. The first bridge arm and the second bridge arm are connected in parallel between the positive terminal of the power supply and ground, and the load is connected between the first bridge arm and the second bridge arm.

3. The H-bridge drive structure with soft switching according to claim 1, characterized in that, The complementary control unit includes four P-type MOS transistors p1, p2, p3, p4 and four N-type MOS transistors n1, n2, n3, n4. The gates of P-type MOS transistor p1 and N-type MOS transistor n1 receive complementary signals and are used to control the gates of the first upper bridge arm switch. The gates of P-type MOS transistor p2 and N-type MOS transistor n2 receive complementary signals and are used to control the gates of the second upper bridge arm switch. The gates of P-type MOS transistor p3 and N-type MOS transistor n3 receive complementary signals and are used to control the gates of the first lower bridge arm switch. The gates of P-type MOS transistor p4 and N-type MOS transistor n4 receive complementary signals and are used to control the gates of the second lower bridge arm switch.

4. The H-bridge drive structure with soft switching according to claim 3, characterized in that, The first comparator is configured to be enabled when the input signal is high, and generates complementary signals VO1 and VO2 through an internal current mirror network. The internal current mirror network of the first comparator includes a combination of one or more of MOSFETs p7, p8, p9, n11, n12, n13, and n14.

5. The H-bridge drive structure with soft switching according to claim 4, characterized in that, The first comparator in the signal generation unit includes: A cascaded amplifier structure consisting of P-type MOSFETs p7, p8, p9 and N-type MOSFETs n11, n12, n13, n14, wherein: The source of p7 is connected to the power supply voltage Vdd, and the drain is connected to the drain and gate of n11. The sources of p8 and p9 are both connected to Vdd, and the drains output the complementary signal VO1 and the complementary signal VO2, respectively. The sources of n11 and n12 are grounded, and the sources of n13 and n14 are connected to the drain of n12. The source of n13 is connected to the input signal IN2, and the drain is connected to the drain of p8 and VO1. The source of n14 is connected to the input signal IN1, and the drain is connected to the drain of p9 and VO2. The current mirror network consists of p7 and n11, n12, and is used to establish a bias current reference. Input signal IN2 controls the output of VO1 through n13, and input signal IN1 controls the output of VO2 through n14.

6. The H-bridge drive structure with soft switching according to claim 3, characterized in that, The second comparator is configured to be enabled when the input signals IN1 and IN2 are low, and to generate complementary signals VO1 and VO2 through an internal current mirror network. The internal current mirror network of the second comparator includes a combination of one or more of the MOSFETs p10, p11, p12, p13, n15, and n16.

7. The H-bridge drive structure with soft switching according to claim 6, characterized in that, The second comparator in the signal generation unit includes: A differential amplifier structure consisting of P-type MOSFETs p10, p11, p12, p13 and N-type MOSFETs n15, n16, wherein: The source of p10 is connected to the power supply voltage Vdd, the source of p11 is connected to Vdd, the drain is connected to the source of p12 and p13, and the gate is connected to the drain of p10. The gates of p12 and p13 are connected to the input signals IN1 and IN2, respectively, and their drains are connected to the drains of n15 and n16, respectively. The sources of n15 and n16 are grounded, and their drains output complementary signals VO1 and VO2, respectively. The current mirror network consists of p10 and p11, which matches the input current of p12 and p13 by mirroring the current. The input signals IN1 and IN2 are differentially amplified by p12 and p13, and then level conversion is achieved by n15 and n16.

8. The H-bridge drive structure with soft switching according to claim 1, characterized in that, Each switch in the H-bridge power unit has a freewheeling diode connected in reverse parallel across its terminals.

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