LDO output secondary power supply current limiting circuit

Abstract

The utility model discloses a kind of LDO output secondary power current limiting circuit, including voltage stabilizing power chip LDO, main MCU, switch tube Q1 and slave MCU, voltage stabilizing power chip LDO is electrically connected with main MCU, the input end of switch tube Q1 is electrically connected with the connecting place of voltage stabilizing power chip LDO and main MCU, the control end of switch tube Q1 is electrically connected with main MCU, the output end of switch tube Q1 is electrically connected with inductance L1, inductance L1 is electrically connected with slave MCU, inductance L1 is electrically connected with capacitor C4, voltage stabilizing power chip LDO is connected with capacitor C1 and capacitor C2 in parallel, resistance R1 is connected in parallel between the input end of switch tube Q1 and the control end of switch tube Q1, resistance R2 is electrically connected between the control end of switch tube Q1 and main MCU, resistance R1 and resistance R2 are electrically connected with capacitor C3.The utility model uses hardware circuit current limiting, i.

Description

Technical Field

[0001] This utility model relates to the field of control circuit technology, and more specifically, to an LDO output two-stage power supply current limiting circuit. Background Technology

[0002] To extend battery standby time by reducing current consumption when the car is parked, various control modules in the vehicle have quiescent current requirements. Therefore, power supplies for circuits that don't need to operate during sleep mode need to be shut down. This often involves branching and managing the logic power supply: one branch provides constant power, while the other is controlled, meaning this branch needs to be shut off during sleep. This presents a problem: if the controlled power branch is an MCU, a micro-capacitor (µF) is required. A large capacitor can generate a very large current when the switching transistor is turned on, causing the voltage regulator (LDO) chip to reset due to undervoltage. However, a small capacitor results in excessive power supply noise for the MCU. A common solution is to use software soft-start to turn on the switching transistor, gradually increasing the control voltage. However, this method generates high-frequency interference, and more importantly, the switching transistor's output capability is inconsistent below the turn-on threshold, occasionally leading to undervoltage reset of the power supply chip. Utility Model Content

[0003] This invention overcomes the shortcomings of the prior art by proposing a current limiting circuit for the LDO output secondary power supply. The current limiting circuit is a hardware circuit consisting of an inductor L1 and a capacitor C4, which limits the charging current and thus prevents sudden current changes and avoids the problem of system undervoltage reset.

[0004] To achieve the above objectives, the present invention provides the following technical solution: A current limiting circuit for a secondary power supply output of an LDO includes a voltage regulator chip LDO, a main MCU, a switching transistor Q1, and a slave MCU. The voltage regulator chip LDO is electrically connected to the main MCU. The input terminal of the switching transistor Q1 is electrically connected to the connection point between the voltage regulator chip LDO and the main MCU. The control terminal of the switching transistor Q1 is electrically connected to the main MCU. An inductor L1 is electrically connected to the output terminal of the switching transistor Q1. The inductor L1 is electrically connected to the slave MCU. A capacitor C4 is electrically connected to the inductor L1.

[0005] Preferably, the voltage regulator chip LDO is connected in parallel with capacitors C1 and C2.

[0006] Preferably, a resistor R1 is connected in parallel between the input terminal and the control terminal of the switching transistor Q1, a resistor R2 is electrically connected between the control terminal of the switching transistor Q1 and the main MCU, and a capacitor C3 is electrically connected between the resistors R1 and R2.

[0007] Preferably, the voltage regulator chip LDO is grounded, the main MCU is grounded, and the slave MCU is grounded.

[0008] Preferably, capacitor C4 is grounded.

[0009] Preferably, capacitor C3 is grounded.

[0010] The beneficial effects of this utility model are: This invention connects an inductor L1 in series between the output terminal of the switching transistor Q1 and the capacitor C4 to impede sudden current changes. The size of the inductor L1 is selected according to the size of the capacitor C4 and the capacitors C1 and C2 at the LDO terminal of the voltage regulator chip. Furthermore, an RC integral stage is added to the control terminal of the switching transistor Q1 to assist in limiting the output current of the switching transistor. Ultimately, the controlled power supply can rise slowly, avoiding the problem of undervoltage reset in the system. Attached Figure Description

[0011] Figure 1 This is a circuit diagram of a specific embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0013] like Figure 1 As shown, an LDO output secondary power supply current limiting circuit includes a voltage regulator chip LDO, a main MCU, a switching transistor Q1, and a slave MCU. The voltage regulator chip LDO is electrically connected to the main MCU. The input terminal of the switching transistor Q1 is electrically connected to the connection point between the voltage regulator chip LDO and the main MCU. The control terminal of the switching transistor Q1 is electrically connected to the main MCU. An inductor L1 is electrically connected to the output terminal of the switching transistor Q1. The inductor L1 is electrically connected to the slave MCU. A capacitor C4 is electrically connected to the inductor L1. Capacitors C1 and C2 are connected in parallel to the voltage regulator chip LDO. A resistor R1 is connected in parallel between the input terminal and the control terminal of the switching transistor Q1. A resistor R2 is electrically connected between the control terminal of the switching transistor Q1 and the main MCU. A capacitor C3 is electrically connected between resistors R1 and R2. The voltage regulator chip LDO is grounded, the main MCU is grounded, the slave MCU is grounded, capacitor C4 is grounded, and capacitor C3 is grounded.

[0014] The main innovation of this invention lies in using an inductor L1 to limit the charging current of capacitor C4. Specifically, an inductor L1 is connected in series between the output terminal of the switching transistor Q1 and the capacitor C4 to prevent sudden current changes. The size of the inductor L1 is selected according to the size of capacitor C4 and the capacitors C1 and C2 at the LDO terminal of the voltage regulator chip. Furthermore, an RC integral stage is added to the control terminal of the switching transistor Q1 as an auxiliary limiter of the switching transistor's output current, ultimately enabling the controlled power supply to rise slowly and avoiding the problem of undervoltage reset in the system.

[0015] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and the inventive concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. A two-stage power supply current limiting circuit for LDO output, comprising a voltage regulator chip LDO, a main MCU, a switching transistor Q1, and a slave MCU, characterized in that, The voltage regulator chip LDO is electrically connected to the main MCU. The input terminal of the switching transistor Q1 is electrically connected to the connection point between the voltage regulator chip LDO and the main MCU. The control terminal of the switching transistor Q1 is electrically connected to the main MCU. The output terminal of the switching transistor Q1 is electrically connected to an inductor L1. The inductor L1 is electrically connected to the slave MCU. The inductor L1 is electrically connected to a capacitor C4.

2. The LDO output two-stage power supply current limiting circuit according to claim 1, characterized in that, The voltage regulator chip LDO has capacitors C1 and C2 connected in parallel.

3. The LDO output secondary power supply current limiting circuit according to claim 1, characterized in that, A resistor R1 is connected in parallel between the input terminal and the control terminal of the switching transistor Q1. A resistor R2 is electrically connected between the control terminal of the switching transistor Q1 and the main MCU. A capacitor C3 is electrically connected between resistors R1 and R2.

4. A current-limiting circuit for a secondary power supply of an LDO output according to claim 1, 2, or 3, characterized in that, The LDO power supply chip is grounded, the main MCU is grounded, and the slave MCU is grounded.

5. The LDO output secondary power supply current limiting circuit according to claim 4, characterized in that, Capacitor C4 is grounded.

6. The LDO output secondary power supply current limiting circuit according to claim 3, characterized in that, Capacitor C3 is grounded.

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