A power handling circuit and power amplifier system

Abstract

The application provides a power processing circuit and a power amplifier system, comprising a first differential signal port, N second differential signal ports, a power processing unit connected between the first differential signal port and the N second differential signal ports, and N isolation modules arranged between homopolar ports of different second differential signal ports, wherein the power processing unit comprises N pairs of differential coupling lines, and N≥2; one end of each of the N isolation modules is connected with one of homopolar coupling lines of the N pairs of differential coupling lines, and the other end of each of the N isolation modules is connected with each other. According to the application, the innovative differential bus type architecture significantly improves the performance of multi-port power distribution / synthesis, and the star type topology of the isolation module, in which one end is connected with the homopolar coupling line of the differential coupling line and the other end is connected with each other, effectively improves the problem that it is difficult to realize resistance cross connection of the parallel power divider, and realizes efficient isolation between ports.

Description

Technical Field

[0001] This application relates to the fields of radio frequency and microwave technology, and in particular to a power processing circuit and a power amplifier system. Background Technology

[0002] As wireless communication technology develops towards higher frequencies, higher integration, and higher performance, it brings new challenges and higher requirements to radio frequency (RF) and microwave integrated circuit (IC) technologies. Therefore, to adapt to the current development of wireless communication technologies, RF and microwave ICs need to possess broadband, integration, miniaturization, and better performance.

[0003] Power processing circuits (such as combiners or power dividers) are among the most commonly used passive devices in the field of radio frequency and microwave integrated circuit technology. Their main function is to combine or distribute power between power modules in a microwave circuit system. Taking power dividers as an example, common implementations include Wilkinson power dividers, T-junction power dividers, and lumped element power dividers. These power dividers have narrow bandwidths and large sizes, making them unsuitable for direct application in differential circuit systems and unable to meet the high-frequency, wide-bandwidth, high-integration, and interference immunity requirements of modern radio frequency circuit systems.

[0004] Therefore, designing a wide-bandwidth, low-insertion-loss, simple-structure, easy-to-integrate, compact, and low-cost differential power divider for use in differential circuit systems is an urgent problem to be solved. Utility Model Content

[0005] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a power processing circuit and a power amplifier system to solve one or more of the aforementioned problems.

[0006] To solve one or more of the above-mentioned technical problems, the technical solution adopted in this application is: In a first aspect, a power processing circuit is provided, including a first differential signal port, N second differential signal ports, a power processing unit connected between the first differential signal port and the N second differential signal ports, and N isolation modules disposed between the same-pole ports of different second differential signal ports, wherein the power processing unit includes N pairs of differential coupling lines, and N ≥ 2; One end of each of the N isolation modules is connected to one of the same-pole coupling lines of the N pairs of differential coupling lines, and the other ends of the N isolation modules are connected to each other.

[0007] In a preferred embodiment, the isolation module includes N first isolation modules and N second isolation modules; One end of each of the N first isolation modules is connected to one of the positive coupling lines of the N pairs of differential coupling lines, and the other ends of the N first isolation modules are connected to each other. One end of each of the N second isolation modules is connected to one of the negative coupling lines of the N pairs of differential coupling lines, and the other ends of the N second isolation modules are connected to each other.

[0008] In a preferred embodiment, the isolation module includes an isolation resistor, or an isolation resistor and a capacitor connected in parallel.

[0009] In a preferred embodiment, the positive coupling lines of the N pairs of differential coupling lines are all connected to the positive port of the first differential signal port, and the negative coupling lines of the N pairs of differential coupling lines are all connected to the negative port of the first differential signal port.

[0010] In a preferred embodiment, the positive and negative ports of each of the second differential signal ports are respectively connected to the positive and negative coupling lines of the same pair of differential coupling lines.

[0011] In a preferred embodiment, the input signal and / or output signal of the power processing circuit are single-ended signals, and the power processing circuit further includes a single-ended signal port and a balun. The balun is connected between the single-ended signal port and the first differential signal port and / or the second differential signal port.

[0012] In a preferred embodiment, the power processing circuit is a differential power divider.

[0013] In a preferred embodiment, the first differential signal port serves as a differential signal input port, and the second differential signal port serves as a differential signal output port.

[0014] In a preferred embodiment, the power processing circuit is a combiner.

[0015] In a preferred embodiment, the first differential signal port serves as a differential signal output port, and the second differential signal port serves as a differential signal input port.

[0016] Secondly, a power amplifier system is also provided, the system including an input port, an output port, and a space disposed between the input port and the output port: N power amplification paths are all connected to the input port, and each power amplification path is configured to amplify one input signal received from the input port. A power divider implemented by the power processing circuit as described in any of the first aspects is connected between the input port and the N power amplification paths, for distributing the power of one input signal input to the input port into multiple output signals; and / or, A combiner implemented by the power processing circuit as described in any of the first aspects is connected between the N power amplification paths and the output port, for power combining of the amplified signals output from all the power amplification paths to obtain a combined output signal.

[0017] This application's solution significantly improves the performance of multi-port power distribution / combining through an innovative differential bus architecture. The power processing circuit employs a structure where a first differential signal port and N second differential signal ports are interconnected via power processing units. Each power processing unit consists of N pairs of differential coupling lines, working in conjunction with N isolation modules positioned between the same-pole ports of different second differential signal ports to form a unique signal transmission network. The isolation modules utilize a star topology, with one end connected to the differential coupling lines and the other end interconnected, effectively addressing the difficulty of resistive cross-connection in parallel power dividers and achieving efficient isolation between ports.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is an architectural diagram of the power processing circuit provided in Embodiment 1 of this application; Figure 2 This is a schematic diagram of the simulation results of the amplitude-frequency and phase-frequency characteristics of the two-equal-division differential power divider implemented by the power processing circuit provided in Embodiment 1 of this application; Figure 3 This is an architecture diagram of the power processing circuit provided in Embodiment 2 of this application; Figure 4 This is a schematic diagram of the simulation results of the amplitude-frequency and phase-frequency characteristics of the four-equal-division differential power divider implemented by the power processing circuit provided in Embodiment 2 of this application; Figure 5 This is an architecture diagram of the power processing circuit provided in Embodiment 3 of this application; Figure 6This is an architecture diagram of the power processing circuit provided in Embodiment 4 of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] This application provides a power processing circuit, including a first differential signal port, N second differential signal ports, a power processing unit connected between the first differential signal port and the N second differential signal ports, and N isolation modules disposed between the same-pole ports of different second differential signal ports. The power processing unit includes N pairs of differential coupling lines, where N ≥ 2. One end of each of the N isolation modules is connected to one of the same-pole coupling lines of the N pairs of differential coupling lines, and the other ends of the N isolation modules are connected to each other.

[0023] Through extensive experimentation, the applicant discovered that the aforementioned improvements effectively address the difficulty of cross-connection of resistors in parallel power dividers, thereby further enhancing the isolation of the entire power processing circuit.

[0024] The present application will be described in detail below through specific embodiments.

[0025] Example 1 Figure 1 A schematic diagram of the power processing circuit provided in Embodiment 1 of this application is shown, with reference to... Figure 1 As shown, in the power processing circuit provided in this embodiment, the number N is selected as 2. The circuit includes a first differential signal port 101, two second differential signal ports 1021 and 1022, a power processing unit connected between the first differential signal port 101 and the two second differential signal ports 1021 and 1022, and two isolation modules disposed between the same-pole ports of the second differential signal ports 1021 and 1022. The power processing unit includes two pairs of differential coupling lines 1031 and 1032, and the isolation modules include two first isolation modules and two second isolation modules.

[0026] The first differential signal port 101 includes a positive port 101a and a negative port 101b, the second differential signal port 1021 includes a positive port 1021a and a negative port 1021b, and the second differential signal port 1022 includes a positive port 1022a and a negative port 1022b.

[0027] The first pair of differential coupling lines 1031 includes a positive coupling line 1031a and a negative coupling line 1031b, and the second pair of differential coupling lines 1032 includes a positive coupling line 1032a and a negative coupling line 1032b.

[0028] Further reference Figure 1 As shown, the positive port 101a of the first differential signal port 101 is connected to the positive coupling line 1031a in the first pair of differential coupling lines 1031 and the positive coupling line 1032a in the second pair of differential coupling lines 1032, and the negative port 101b of the first differential signal port 101 is connected to the negative coupling line 1031b in the first pair of differential coupling lines 1031 and the negative coupling line 1032b in the second pair of differential coupling lines 1032. The positive port 1021a of the second differential signal port 1021 is connected to the positive coupling line 1031a of the first pair of differential coupling lines 1031, the negative port 1021b of the second differential signal port 1021 is connected to the negative coupling line 1031b of the first pair of differential coupling lines 1031, the positive port 1022a of the second differential signal port 1022 is connected to the positive coupling line 1032a of the second pair of differential coupling lines 1032, and the negative port 1022b of the second differential signal port 1022 is connected to the negative coupling line 1032b of the second pair of differential coupling lines 1032.

[0029] Therefore, in this embodiment, the positive coupling lines of all differential coupling lines are connected to the positive port 101a of the first differential signal port 101, and the negative coupling lines of all first differential coupling lines are connected to the negative port 101b of the first differential signal port 101. That is, the positive and negative coupling lines of different pairs of first differential coupling lines are connected in parallel, making the overall circuit structure simpler. When this circuit structure is applied to an amplifier system, it can supply power to multiple amplifiers from the parallel connection point. The positive ports 1021a and 1021b of the second differential signal port 1021 and the positive ports 1022a and 1022b of the second differential signal port 1022 are all connected to the positive and negative coupling lines of the same pair of differential coupling lines, forming a dual-port collinear coupling structure, which can significantly improve the integration and signal consistency of the power distribution / combining circuit.

[0030] In some specific embodiments, the isolation module may employ an isolation resistor; in other specific embodiments, the isolation module may employ an isolation resistor and a capacitor connected in parallel. It should be noted that the specific implementation of the isolation module is not limited in the embodiments of this application, and can be selected according to actual product requirements without departing from the inventive concept of this application.

[0031] The following explanations use the isolation module employing an isolation resistor as an example to illustrate the solution proposed in this application.

[0032] Further reference Figure 1 As shown, isolation resistors, serving as isolation modules, are positioned between the same-pole ports of different second differential signal ports. Specifically, the first isolation modules are isolation resistors R1a and R2a, and the two second isolation modules are isolation resistors R1b and R2b. One end of isolation resistor R1a is connected to the positive coupling line 1031a of the first pair of differential coupling lines 1031, and one end of isolation resistor R2a is connected to the positive coupling line 1032a of the second pair of differential coupling lines 1032. The other end of isolation resistor R1a is connected to the other end of isolation resistor R2a. One end of isolation resistor R1b is connected to the negative coupling line 1031b of the first pair of differential coupling lines 1031, and one end of isolation resistor R2b is connected to the negative coupling line 1032b of the second pair of differential coupling lines 1032. The other end of isolation resistor R1b is connected to the other end of isolation resistor R2b.

[0033] This application's solution further improves the isolation performance and signal integrity of the power processing circuit by optimizing the topology of the isolation module. The design subdivides the isolation module into two first isolation modules (positive path) and two second isolation modules (negative path). The two first isolation modules use a star interconnect to centrally connect the positive coupling lines of each differential coupling line, while the two second isolation modules symmetrically interconnect all negative coupling lines, forming a dual-channel isolation network. This architecture, with independent management of positive and negative isolation paths, has the following technical advantages: 1. Enhanced Common-Mode Suppression: Through the symmetrical isolation design of the positive and negative branches, active compensation for the phase error of the differential signal can be achieved; 2. Crosstalk optimization: The physical separation of the positive and negative isolation networks reduces crosstalk between ports, and can maintain stable isolation characteristics, especially in high-frequency bands (such as millimeter wave bands); 3. Simplified impedance matching: The dual-star isolation structure naturally forms a balanced terminal load, which reduces the range of input impedance fluctuations at each port and solves the matching mismatch problem caused by parasitic parameters in distributed resistor networks.

[0034] It should be noted that the power processing circuit provided in this application embodiment can be used to implement both a power divider and a combiner. It is understood that when the power processing circuit is a power divider, the first differential signal port 101 is used as a differential signal input port, and the two second differential signal ports 1021 and 1022 are used as differential signal output ports; when the power processing circuit is a combiner, the first differential signal port 101 is used as a differential signal output port, and the two second differential signal ports 1021 and 1022 are used as differential signal input ports.

[0035] In some specific embodiments, the impedances of the first differential signal port 101 and the second differential signal ports 1021 and 1022 are different. For example, the characteristic impedance of the first differential signal port 101 is 25Ω, and the characteristic impedances of the two second differential signal ports 1021 and 1022 are both 50Ω, etc., which will not be listed here. The two pairs of differential coupling lines 1031 and 1032 are coupling lines with completely identical performance. For example, the even-mode impedance Ze of the two pairs of differential coupling lines 1031 and 1032 is 200Ω, the odd-mode impedance Zo is 25Ω, and the electrical length E is 10 degrees at a frequency of 1GHz, etc., which will also not be listed here.

[0036] Figure 2 This is a schematic diagram illustrating the simulation results of the amplitude-frequency and phase-frequency characteristics of the two-equal-division differential power divider implemented by the power processing circuit provided in the embodiments of this application. (Refer to...) Figure 2 As shown in the figure, within the 0~20GHz frequency range, the phase curves of the two differential signal output ports (i.e., the second differential signal ports 1021 and 1022) of the two-equal differential power divider coincide with the frequency curves, indicating good phase consistency between the two ports across the entire frequency band. In the 7-11GHz operating frequency band, the return losses S11, S22, and S33 are less than -20dB, indicating very low signal reflection of the two-equal differential power divider. This demonstrates that the two-equal differential power divider network can not only effectively match the impedance of the input and output ports but also maximize... The system absorbs signals to the maximum extent to achieve efficient energy transmission. Within the 7-11 GHz operating frequency band, the transmission coefficients (S21, S31) of the two second differential signal ports 1021 and 1022 of the dual differential power divider are all around -3 dB, indicating that the amplitude consistency of the output signals at each output port is good. Within the 7-11 GHz operating frequency band, the isolation between the two ports 1021 and 1022 of the dual differential power divider is less than -20 dB, indicating that the ports can effectively block power leakage.

[0037] The power processing circuit provided in this application embodiment can optimize in-band insertion loss, callback loss, and isolation by changing one or more combinations of the differential coupling line's electrical length E, even-mode impedance Ze, odd-mode impedance Zo, and isolation modules. It eliminates the need for traditional quarter-wavelength coupling lines, allowing the length of the differential coupling line in this embodiment to be less than a quarter wavelength of the operating center frequency, thereby reducing the overall circuit size, increasing integration density, and improving insertion loss performance. Furthermore, the operating bandwidth can be controlled by changing the electrical length of the differential coupling line, the even-mode impedance Ze, and the odd-mode impedance Zo.

[0038] Furthermore, it should be noted that in this embodiment, "positive" and "negative" are relative concepts, and may simply indicate that the signals at the corresponding ports are "out of phase" or "different in phase". Even if the "positive" and "negative" signals are interchanged, the circuit in this embodiment can still function normally, and this variation is still within the scope of protection of this application.

[0039] Example 2 Figure 3 This is a schematic diagram of the power processing circuit provided in Embodiment 2 of this application, referring to... Figure 3 As shown, in the power processing circuit provided in this application embodiment, the number N is selected as 4. The circuit includes a first differential signal port 201, four second differential signal ports 2021, 2022, 2023 and 2024, a power processing unit connected between the first differential signal port 201 and the four second differential signal ports 2021, 2022, 2023 and 2024, and four isolation modules disposed between the same-pole ports of the second differential signal ports 2021, 2022, 2023 and 2024. The power processing unit includes four pairs of differential coupling lines 2031, 2032, 2033 and 2034, and the isolation modules include four first isolation modules and four second isolation modules.

[0040] The first differential signal port 201 includes a positive port 201a and a negative port 201b; the second differential signal port 2021 includes a positive port 2021a and a negative port 2021b; the second differential signal port 2022 includes a positive port 2022a and a negative port 2022b; the second differential signal port 2023 includes a positive port 2023a and a negative port 2023b; and the second differential signal port 2024 includes a positive port 2024a and a negative port 2024b.

[0041] The first pair of differential coupling lines 2031 includes a positive coupling line 2031a and a negative coupling line 2031b; the second pair of differential coupling lines 2032 includes a positive coupling line 2032a and a negative coupling line 2032b; the third pair of differential coupling lines 2033 includes a positive coupling line 2033a and a negative coupling line 2033b; and the fourth pair of differential coupling lines 2034 includes a positive coupling line 2034a and a negative coupling line 2034b.

[0042] Further reference Figure 3As shown, the positive port 201a of the first differential signal port 201 is connected to the positive coupling line 2031a of the first pair of differential coupling lines 2031, the positive coupling line 2032a of the second pair of differential coupling lines 2032, the positive coupling line 2033a of the third pair of differential coupling lines 2033, and the positive coupling line 2034a of the fourth pair of differential coupling lines 2034. The negative port 201b of the first differential signal port 201 is connected to the negative coupling line 2031b of the first pair of differential coupling lines 2031, the negative coupling line 2032b of the second pair of differential coupling lines 2032, the negative coupling line 2033b of the third pair of differential coupling lines 2033, and the negative coupling line 2034b of the fourth pair of differential coupling lines 2034. The positive port 2021a of the second differential signal port 2021 is connected to the positive coupling line 2031a of the first pair of differential coupling lines 2031, and the negative port 2021b of the second differential signal port 2021 is connected to the negative coupling line 2031b of the first pair of differential coupling lines 2031; the positive port 2022a of the second differential signal port 2022 is connected to the positive coupling line 2032a of the second pair of differential coupling lines 2032, and the negative port 2022b of the second differential signal port 2022 is connected to the negative coupling line 2032b of the second pair of differential coupling lines 2032. The positive port 2023a of the second differential signal port 2023 is connected to the positive coupling line 2033a of the third pair of differential coupling lines 2033, and the negative port 2023b of the second differential signal port 2023 is connected to the negative coupling line 2033b of the third pair of differential coupling lines 2033; the positive port 2024a of the second differential signal port 2024 is connected to the positive coupling line 2034a of the fourth pair of differential coupling lines 2034, and the negative port 2024b of the second differential signal port 2024 is connected to the negative coupling line 2034b of the fourth pair of differential coupling lines 2034.

[0043] Therefore, in this embodiment, the positive coupling lines of all first differential coupling lines are connected to the positive port 201a of the first differential signal port 201, and the negative coupling lines of all first differential coupling lines are connected to the negative port 201b of the first differential signal port 201. That is, the positive and negative coupling lines of different pairs of first differential coupling lines are connected in parallel, making the overall circuit structure simpler. Furthermore, when this circuit structure is applied to an amplifier system, power can be supplied to multiple amplifiers from the parallel connection point. The positive and negative ports of each second differential signal port are connected to the positive and negative coupling lines of the same pair of differential coupling lines, which can significantly improve the integration and signal consistency of the power distribution / combining circuit.

[0044] Further reference Figure 3As shown, the four first isolation modules are implemented by isolation resistors R1a, R2a, R3a, and R4a, respectively, and the four second isolation modules are implemented by isolation resistors R1b, R2b, R3b, and R4b, respectively. One end of isolation resistor R1a is connected to the positive coupling line 1031a of the first pair of differential coupling lines 1031; one end of isolation resistor R2a is connected to the positive coupling line 1032a of the second pair of differential coupling lines 1032; one end of isolation resistor R3a is connected to the positive coupling line 1033a of the third pair of differential coupling lines 1033; and one end of isolation resistor R4a is connected to the positive coupling line 1034a of the fourth pair of differential coupling lines 1034. The other ends of isolation resistors R1a, R2a, R3a, and R4a are connected to each other. One end of the isolation resistor R1b is connected to the negative coupling line 1031b in the first pair of differential coupling lines 1031, one end of the isolation resistor R2b is connected to the negative coupling line 1032b in the second pair of differential coupling lines 1032, one end of the isolation resistor R3b is connected to the negative coupling line 1033b in the third pair of differential coupling lines 1033, and one end of the isolation resistor R4b is connected to the negative coupling line 1034b in the fourth pair of differential coupling lines 1034. The other ends of the isolation resistors R1b, R2b, R3b and R4b are connected to each other.

[0045] This application's solution further improves the isolation performance and signal integrity of the power processing circuit by optimizing the topology of the isolation module. The design subdivides the isolation module into four first isolation modules (positive path) and four second isolation modules (negative path). The four first isolation modules are centrally connected to the positive coupling lines of each differential coupling line using a star interconnection, while the four second isolation modules symmetrically interconnect all negative coupling lines, forming a dual-channel isolation network. This architecture, with independent management of positive and negative isolation paths, has the following technical advantages: 1. Enhanced Common-Mode Suppression: Through the symmetrical isolation design of the positive and negative branches, active compensation for the phase error of the differential signal can be achieved; 2. Crosstalk optimization: The physical separation of the positive and negative isolation networks reduces crosstalk between ports, and can maintain stable isolation characteristics, especially in high-frequency bands (such as millimeter wave bands); 3. Simplified impedance matching: The dual-star isolation structure naturally forms a balanced terminal load, which reduces the range of input impedance fluctuations at each port and solves the matching mismatch problem caused by parasitic parameters in distributed resistor networks.

[0046] It should be noted that the power processing circuit provided in this application embodiment can be used to implement both a power divider and a combiner. It is understood that when the power processing circuit is a power divider, the first differential signal port 201 is used as the differential signal input port, and the four second differential signal ports 2021, 2022, 2023, and 2024 are used as differential signal output ports; when the power processing circuit is a combiner, the first differential signal port 201 is used as the differential signal output port, and the four second differential signal ports 2021, 2022, 2023, and 2024 are used as differential signal input ports. For details, please refer to the relevant content in Embodiment 1, which will not be elaborated here.

[0047] In some specific embodiments, the impedance of the first differential signal port 201 is different from that of the four second differential signal ports 2021, 2022, 2023, and 2024. For example, the characteristic impedance of the first differential signal port 201 is 12.5Ω, while the characteristic impedances of the four second differential signal ports 2021, 2022, 2023, and 2024 are all 50Ω, etc., and will not be listed in detail here. The four pairs of differential coupling lines 2031, 2032, 2033, and 2034 are coupling lines with completely identical performance. For example, the even-mode impedance Ze of the four pairs of differential coupling lines 2031, 2032, 2033, and 2034 is 200Ω, the odd-mode impedance Zo is 25Ω, and the electrical length E is 10 degrees at a frequency of 1GHz, etc., and will not be listed in detail here either.

[0048] Figure 4 This is a schematic diagram illustrating the simulation results of the amplitude-frequency and phase-frequency characteristics of the four-equal-division differential power divider implemented by the power processing circuit provided in the embodiments of this application. (Refer to...) Figure 4As shown in the figure, within the 0~20GHz frequency range, the phase curves of the four differential signal output ports (i.e., the second differential signal ports 2021, 2022, 2023, and 2024) of this quadruple differential power divider coincide with the frequency curves, indicating good phase consistency across the entire frequency band. In the 6-12GHz operating frequency band, the return losses S11, S22, S33, S44, and S55 are less than -20dB, indicating very low signal reflection from the quadruple differential power divider. This demonstrates that the quadruple differential power divider network can not only effectively match the impedance of the input and output ports but also maximize... The four-way differential power divider effectively absorbs signals to achieve efficient energy transmission. Within the 6-12 GHz operating frequency band, the transmission coefficients (S21, S31, S41, S51) of the four differential signal output ports are all around -6 dB, indicating good amplitude consistency of the output signals at each port. Within the 5-13 GHz operating frequency band, the isolation between the four differential signal output ports (i.e., the second differential signal ports 2021, 2022, 2023, and 2024) of the four-way differential power divider is less than -20 dB, indicating that power leakage can be effectively blocked between the ports.

[0049] The power processing circuit provided in this application embodiment can optimize in-band insertion loss, callback loss, and isolation by changing one or more combinations of the differential coupling line's electrical length E, even-mode impedance Ze, odd-mode impedance Zo, and isolation modules. It eliminates the need for traditional quarter-wavelength coupling lines, allowing the length of the differential coupling line in this embodiment to be less than a quarter wavelength of the operating center frequency, thereby reducing the overall circuit size, increasing integration density, and improving insertion loss performance. Furthermore, the operating bandwidth can be controlled by changing the electrical length of the differential coupling line, the even-mode impedance Ze, and the odd-mode impedance Zo.

[0050] Example 3 Figure 5 This is an architectural diagram of the power processing circuit provided in Embodiment 3 of this application. The difference between Embodiment 2 and Embodiment 3 is that, referring to... Figure 5 As shown in the embodiment of this application, the input signal is a single-ended signal, and the power processing circuit also includes a single-ended signal port 204 and a balun 205.

[0051] Taking the power processing circuit as a power divider as an example, further refer to Figure 5As shown, the first differential signal port 201 serves as the differential signal input port, and the four second differential signal ports 2021, 2022, 2023, and 2024 serve as differential signal output ports. A balun 205 is connected between the single-ended signal port 204 and the first differential signal port 201. The balun 205 converts the single-ended input signal output from the single-ended signal port 204 into a differential signal, which is then input to the power processing unit through the positive port 201a and the negative port 201b of the first differential signal port 201. Through the differential power processing architecture integrating the balun, efficient conversion from single-ended signals to multi-channel differential power distribution is achieved, significantly improving system compatibility and RF performance.

[0052] It should be noted that, in the embodiments of this application, the input signal and output signal of the power processing circuit can be single-ended signals or differential signals. In specific implementation, they can be set according to actual needs, and no specific limitation is made here.

[0053] Example 4 Figure 6 This is a schematic diagram of the power processing circuit provided in Embodiment 4 of this application, referring to... Figure 6 As shown, in the power processing circuit provided in this application embodiment, the number of second differential signal ports and the number of differential coupling lines in the power processing unit are set to be more, denoted by the number N, where N≥2 and is a positive integer. Specifically, this application embodiment includes a first differential signal port 301, N second differential signal ports 3021-302N, a power processing unit connected between the first differential signal port 301 and the N second differential signal ports 3021-302N, and N isolation modules disposed between the same-pole ports of the second differential signal ports 3021-302N. The power processing unit includes N pairs of differential coupling lines 3031-303N, and the isolation modules include N first isolation modules and N second isolation modules.

[0054] The first differential signal port 301 includes a positive port 301a and a negative port 301b. Each second differential signal port includes a positive port and a negative port. For example, the second differential signal port 302i includes a positive port 302ia and a negative port 302ib, where 1 ≤ i ≤ N, and i is a positive integer. That is, the second differential signal port 3021 includes a positive port 3021a and a negative port 3021b, the second differential signal port 3022 includes a positive port 3022a and a negative port 3022b, and so on, with the second differential signal port 302N including a positive port 302Na and a negative port 302Nb.

[0055] Each pair of differential coupling lines includes a positive coupling line and a negative coupling line. For example, the i-th pair of differential coupling lines 303i includes a positive coupling line 303ia and a negative coupling line 303ib, where 1≤i≤N and i is a positive integer. That is, the first pair of differential coupling lines 3031 includes a positive coupling line 3031a and a negative coupling line 3031b, the second pair of differential coupling lines 3032 includes a positive coupling line 3032a and a negative coupling line 3032b, and so on, with the N-th pair of differential coupling lines 303N including a positive coupling line 303Na and a negative coupling line 303Nb.

[0056] Further reference Figure 6 As shown, the positive port 301a of the first differential signal port 301 is connected to the positive coupling line of all pairs of first differential coupling lines, and the negative port 301b of the first differential signal port 301 is connected to the negative coupling line of all pairs of first differential coupling lines.

[0057] Further reference Figure 6 As shown in the embodiment of this application, the positive port 302ia of the second differential signal port 302i is connected to the positive coupling line 303ia of the i-th pair of differential coupling lines 303i, and the negative port 302ib of the second differential signal port 302i is connected to the negative coupling line 303ib of the i-th pair of differential coupling lines 303i, where 1≤i<N, and i is a positive integer. That is, the positive port 3021a of the second differential signal port 3021 is connected to the positive coupling line 3031a of the first pair of differential coupling lines 3031, and the negative port 3021b of the second differential signal port 3021 is connected to the negative coupling line 3031b of the first pair of differential coupling lines 3031; the positive port 3022a of the second differential signal port 3022 is connected to the positive coupling line 3032a of the second pair of differential coupling lines 3032. The negative port 3022b of the differential signal port 3022 is connected to the negative coupling line 3032b of the second pair of differential coupling lines 3032, and so on. The positive port 302Na of the second differential signal port 302N is connected to the positive coupling line 303Na of the Nth pair of differential coupling lines 303N, and the negative port 302Nb of the second differential signal port 302N is connected to the negative coupling line 303Nb of the Nth pair of differential coupling lines 303N.

[0058] Therefore, in this embodiment, the positive coupling lines of all first differential coupling lines are connected to the positive port 301a of the first differential signal port 301, and the negative coupling lines of all first differential coupling lines are connected to the negative port 301b of the first differential signal port 301. That is, the positive and negative coupling lines of different pairs of first differential coupling lines are connected in parallel, making the overall circuit structure simpler. When this circuit structure is applied to an amplifier system, it can supply power to multiple amplifiers from the parallel connection point. The positive and negative ports of each second differential signal port are connected to the positive and negative coupling lines of the same pair of differential coupling lines, forming a dual-port collinear coupling structure, which can significantly improve the integration and signal consistency of the power distribution / combining circuit.

[0059] Further reference Figure 6 As shown, N first isolation modules are implemented by isolation resistors R1a-RNa, and N second isolation modules are implemented by isolation resistors R1b-RNb. One end of each isolation resistor R1a-RNa is connected to the positive coupling lines 3031a-303Na of the differential coupling lines 3031-303N (for example, one end of isolation resistor Ria is connected to the positive coupling line 303ia of the i-th pair of differential coupling lines 303i, where 1 ≤ i < N, and i is a positive integer). The other ends of isolation resistors R1a-RNa are connected to each other. One end of each isolation resistor R1b-RNb is connected to the negative coupling lines 3031b-303Nb of the differential coupling lines 3031-303N (for example, one end of isolation resistor Rib is connected to the negative coupling line 303ib of the i-th pair of differential coupling lines 303i, where 1 ≤ i < N, and i is a positive integer). The other ends of isolation resistors R1b-RNb are connected to each other.

[0060] This application's solution further improves the isolation performance and signal integrity of the power processing circuit by optimizing the topology of the isolation module. The design subdivides the isolation module into N first isolation modules (positive paths) and N second isolation modules (negative paths). The N first isolation modules are centrally connected to the positive coupling lines of each differential coupling line using a star interconnection, while the N second isolation modules symmetrically interconnect all negative coupling lines, forming a dual-channel isolation network. This architecture, with independent management of positive and negative isolation paths, has the following technical advantages: 1. Enhanced Common-Mode Suppression: Through the symmetrical isolation design of the positive and negative branches, active compensation for the phase error of the differential signal can be achieved; 2. Crosstalk optimization: The physical separation of the positive and negative isolation networks reduces crosstalk between ports, and can maintain stable isolation characteristics, especially in high-frequency bands (such as millimeter wave bands); 3. Simplified impedance matching: The dual-star isolation structure naturally forms a balanced terminal load, which reduces the range of input impedance fluctuations at each port and solves the matching mismatch problem caused by parasitic parameters in distributed resistor networks.

[0061] It should be noted that the power processing circuit provided in this application embodiment can be used to implement both a power divider and a combiner. It is understood that when the power processing circuit is a power divider, the first differential signal port 301 is used as the differential signal input port, and the N second differential signal ports 3021-302N are used as differential signal output ports; when the power processing circuit is a combiner, the first differential signal port 301 is used as the differential signal output port, and the N second differential signal ports 3021-302N are used as differential signal input ports. For details, please refer to the relevant content in Embodiment 1, which will not be elaborated here.

[0062] In some specific embodiments, the impedance of the first differential signal port 301 is different from that of the N second differential signal ports 3021-302N.

[0063] The power processing circuit provided in this application embodiment can optimize in-band insertion loss, callback loss, and isolation by changing one or more combinations of the differential coupling line's electrical length E, even-mode impedance Ze, odd-mode impedance Zo, and isolation modules. It eliminates the need for traditional quarter-wavelength coupling lines, allowing the length of the differential coupling line in this embodiment to be less than a quarter wavelength of the operating center frequency, thereby reducing the overall circuit size, increasing integration density, and improving insertion loss performance. Furthermore, the operating bandwidth can be controlled by changing the electrical length of the differential coupling line, the even-mode impedance Ze, and the odd-mode impedance Zo.

[0064] Example 5 Corresponding to the power processing circuit described above, this application also provides a power amplifier system, which generally includes an input port, an output port, and N power amplification paths, a power divider, and / or a combiner disposed between the input port and the output port. Each of the N power amplification paths is connected to the input port, and each power amplification path is configured to amplify one input signal received from the input port. The power divider and combiner are implemented by the power processing circuit described in any one of embodiments one to four. The power divider is connected between the input port and the N power amplification paths to distribute the power of one input signal received from the input port, splitting it into multiple output signals. The combiner is connected between the N power amplification paths and the output port to combine the amplified signals output from all the power amplification paths to obtain a combined output signal.

[0065] In some specific embodiments, each power amplification path includes a power amplification unit and an impedance conversion network. The power amplification unit amplifies one input signal of the same phase received from the input port of its respective power amplification path; the impedance conversion network is connected to the power amplification unit and is used for load modulation of the power amplification unit within its respective power amplification path.

[0066] In this embodiment, the positional relationship between the impedance conversion network and the power amplification unit is not specifically limited; it can be configured according to actual needs during implementation. For example, in some specific embodiments, the impedance conversion network is positioned in front of the power amplification unit along the signal transmission direction, i.e., between the input port and the power amplification unit; in other specific embodiments, the impedance conversion network is positioned behind the power amplification unit along the signal transmission direction, i.e., between the power amplification unit and the output port.

[0067] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0068] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0069] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0070] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A power processing circuit, characterized in that, It includes a first differential signal port, N second differential signal ports, a power processing unit connected between the first differential signal port and the N second differential signal ports, and N isolation modules disposed between the same-pole ports of different second differential signal ports, wherein the power processing unit includes N pairs of differential coupling lines, and N ≥ 2; One end of each of the N isolation modules is connected to one of the same-pole coupling lines of the N pairs of differential coupling lines, and the other ends of the N isolation modules are connected to each other.

2. The power processing circuit as described in claim 1, characterized in that, The isolation module includes N first isolation modules and N second isolation modules; One end of each of the N first isolation modules is connected to one of the positive coupling lines of the N pairs of differential coupling lines, and the other ends of the N first isolation modules are connected to each other. One end of each of the N second isolation modules is connected to one of the negative coupling lines of the N pairs of differential coupling lines, and the other ends of the N second isolation modules are connected to each other.

3. The power processing circuit as described in claim 2, characterized in that, The isolation module includes an isolation resistor, or an isolation resistor and a capacitor connected in parallel.

4. The power processing circuit as described in claim 1, characterized in that, All N pairs of positive coupling lines are connected to the positive port of the first differential signal port, and all N pairs of negative coupling lines are connected to the negative port of the first differential signal port.

5. The power processing circuit as described in claim 1, characterized in that, The positive and negative ports of each of the second differential signal ports are respectively connected to the positive and negative coupling lines of the same pair of differential coupling lines.

6. The power processing circuit according to any one of claims 1 to 5, characterized in that, The input signal and / or output signal of the power processing circuit are single-ended signals, and the power processing circuit also includes a single-ended signal port and a balun. The balun is connected between the single-ended signal port and the first differential signal port and / or the second differential signal port.

7. The power processing circuit as described in any one of claims 1 to 5, characterized in that, The power processing circuit is a differential power divider.

8. The power processing circuit as described in claim 7, characterized in that, The first differential signal port serves as the differential signal input port, and the second differential signal port serves as the differential signal output port.

9. The power processing circuit as described in any one of claims 1 to 5, characterized in that, The power processing circuit is a combiner.

10. The power processing circuit as described in claim 9, characterized in that, The first differential signal port serves as the differential signal output port, and the second differential signal port serves as the differential signal input port.

11. A power amplifier system, characterized in that, The system includes an input port, an output port, and a space disposed between the input port and the output port. N power amplification paths are all connected to the input port, and each power amplification path is configured to amplify one input signal received from the input port. A power divider implemented by the power processing circuit as described in any one of claims 1 to 10, connected between the input port and the N power amplification paths, is used to distribute the power of one input signal input to the input port into multiple output signals; and / or, The combiner implemented by the power processing circuit as described in any one of claims 1 to 10 is connected between the N power amplification paths and the output port, and is used to perform power combining of the amplified signals output by all the power amplification paths to obtain the combined output signal.

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