A power amplifier, integrated circuit, chip and terminal

Abstract

This application provides a power amplifier, integrated circuit, chip, and terminal, including at least four cascaded amplifier circuits, comprising a first-stage amplifier circuit that receives the signal to be amplified; at least two second-stage amplifier circuits, with the input terminal of the first second-stage amplifier circuit connected to the output terminal of the first-stage amplifier circuit, and the input and output terminals of adjacent second-stage amplifier circuits connected; and a third-stage amplifier circuit, with its input terminal connected to the output terminal of the last second-stage amplifier circuit. The transistor gate widths used in the first, second, and third-stage amplifier circuits are first, second, and third widths, respectively, with the second width being greater than the first width and the third width being greater than the second width. Each of the first to third-stage amplifier circuits includes an upper half module and a lower half module, with the upper half module and lower half module having symmetrical structures. This application effectively improves the performance of the amplifier, exhibiting high power, high gain, and high stability.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a power amplifier, integrated circuit, chip, and terminal. Background Technology

[0002] Terahertz communication technology is a communication technology that uses terahertz waves with frequencies between 0.1 THz and 10 THz for information transmission. It features ultra-high bandwidth, high transmission rate, strong anti-interference capability, and good directionality. Terahertz communication technology also offers advantages such as good security and flexible networking, meeting potential application scenarios such as holographic communication, micro-scale communication (inter-chip communication and nanometer communication), ultra-large capacity data backhaul, and short-range ultra-high-speed transmission. Therefore, it is considered one of the key candidate technologies for sixth-generation mobile communication (6G).

[0003] Terahertz communication systems use terahertz waves as carrier waves for information transmission. The power amplifier is a core component of terahertz communication systems; its main function is to amplify the weak terahertz signal to increase its transmission power and distance, ensuring sufficient signal strength and stability during long-distance transmission and preventing communication quality degradation or interruption due to signal attenuation. It's like equipping the terahertz communication system with a "power engine."

[0004] Improving the transmit power of power amplifiers and enhancing the gain and stability of signal amplification are technical problems that urgently need to be solved by those skilled in the art. Utility Model Content

[0005] This application provides a power amplifier, integrated circuit, chip, and terminal that effectively improve the performance of the power amplifier, achieving high power, high gain, and high stability.

[0006] In a first aspect, this application provides a power amplifier, including at least four cascaded amplifier circuits, said at least four cascaded amplifier circuits comprising:

[0007] A first-stage amplifier circuit is used to receive the signal to be amplified. The gate width of the transistor used in the first-stage amplifier circuit is a first width.

[0008] At least two second-stage amplifier circuits are provided. The input terminal of the first second-stage amplifier circuit is connected to the output terminal of the first-stage amplifier circuit. The input and output terminals of two adjacent second-stage amplifier circuits are connected. The gate width of the transistor used in each second-stage amplifier circuit is a second width, which is greater than the first width.

[0009] A third-stage amplifier circuit, wherein the input terminal of the third-stage amplifier circuit is connected to the output terminal of the last second-stage amplifier circuit, and the transistor gate width used in the third-stage amplifier circuit is a third width, which is greater than the second width;

[0010] Each of the first-stage amplifier circuit to the third-stage amplifier circuit includes an upper half module and a lower half module, and the upper half module and the lower half module are structurally symmetrical.

[0011] In some embodiments, the upper half module includes: a first transistor, a first gate bias network, a first drain bias network, and an inter-electrode coupling unit;

[0012] The input terminal of the first gate bias network is connected to the output terminal of the previous amplifier circuit;

[0013] The output of the first gate bias network is connected to the gate of the first transistor, the source of the first transistor is grounded, and the drain of the first transistor is connected to the input of the first drain bias network.

[0014] The output of the first drain bias network is connected to the input of the inter-electrode coupling unit, and the output of the inter-electrode coupling unit is connected to the input of the next stage amplifier circuit. The first gate bias network and the first drain bias network are structurally symmetrical.

[0015] In some embodiments, it further includes: a DC blocking coupling unit;

[0016] The input terminal of the DC blocking coupling unit is connected to the signal to be amplified, and the output terminal of the DC blocking coupling unit is connected to the input terminal of the first gate bias network corresponding to the first stage amplifier circuit.

[0017] In some embodiments, the DC blocking coupling unit includes a first capacitor;

[0018] The first gate bias network includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a first inductor, a second capacitor, and a third capacitor;

[0019] One end of the first resistor is connected to one end of the second capacitor, and the other end of the second capacitor is grounded. The other end of the first resistor is connected to one end of the third capacitor and one end of the second resistor. The other end of the third capacitor is connected to one end of the first inductor, and the other end of the first inductor is grounded.

[0020] The other end of the second resistor is connected to one end of the third resistor and one end of the fourth resistor. The other end of the third resistor serves as the input terminal of the first gate bias network. One end of the second capacitor serves as the output terminal of the DC blocking coupling unit. The other end of the first capacitor serves as the input terminal of the DC blocking coupling unit. The other end of the fourth resistor serves as the output terminal of the first gate bias network.

[0021] The first drain bias network includes: a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a second inductor, a fourth capacitor, and a fifth capacitor;

[0022] The inter-electrode coupling unit includes: a sixth capacitor;

[0023] One end of the eighth resistor is connected to one end of the fifth capacitor, the other end of the fifth capacitor is grounded, the other end of the eighth resistor is connected to one end of the fourth capacitor and one end of the seventh resistor, the other end of the fourth capacitor is connected to one end of the second inductor, and the other end of the second inductor is grounded;

[0024] The other end of the seventh resistor is connected to one end of the fifth resistor and one end of the sixth resistor. The other end of the fifth resistor serves as the input terminal of the first drain bias network, and the other end of the sixth resistor serves as the output terminal of the first drain bias network.

[0025] In some embodiments, the lower half module includes: a second transistor, a second gate bias network, a second drain bias network, and a filtering unit;

[0026] The input terminal of the second gate bias network is connected to the output terminal of the inter-electrode coupling unit of the previous amplifier circuit;

[0027] The output of the second gate bias network is connected to the gate of the second transistor, the source of the second transistor is grounded, and the drain of the second transistor is connected to the input of the second drain bias network.

[0028] The second drain bias network and the second gate bias network are symmetrical in structure. The output terminal of the second drain bias network is connected to the input terminal of the filter unit. The output terminal of the filter unit is connected to the input terminal of the next stage amplifier circuit. The output terminal of the filter unit of the fourth stage amplifier circuit is used to output the amplified signal.

[0029] In some embodiments, the second gate bias network includes: a ninth resistor, an eleventh resistor, a thirteenth resistor, a fourteenth resistor, a third inductor, a seventh capacitor, and a ninth capacitor;

[0030] One end of the ninth resistor is connected to one end of the seventh capacitor, the other end of the seventh capacitor is grounded, the other end of the ninth resistor is connected to one end of the ninth capacitor and one end of the eleventh resistor, the other end of the ninth capacitor is connected to one end of the third inductor, and the other end of the third inductor is grounded.

[0031] The other end of the eleventh resistor is connected to one end of the thirteenth resistor and one end of the fourteenth resistor. The other end of the thirteenth resistor serves as the input terminal of the second gate bias network, and the other end of the fourteenth resistor serves as the output terminal of the second gate bias network.

[0032] The second drain bias network includes: a tenth resistor, a twelfth resistor, a fifteenth resistor, a sixteenth resistor, a fourth inductor, an eighth capacitor, and a tenth capacitor;

[0033] The inter-electrode coupling unit includes: an eleventh capacitor;

[0034] One end of the tenth resistor is connected to one end of the eighth capacitor, the other end of the eighth capacitor is grounded, the other end of the tenth resistor is connected to one end of the tenth capacitor and one end of the twelfth resistor, the other end of the tenth capacitor is connected to one end of the fourth inductor, and the other end of the fourth inductor is grounded.

[0035] The other end of the twelfth resistor is connected to one end of the fifteenth resistor and one end of the sixteenth resistor. The other end of the fifteenth resistor serves as the input terminal of the second drain bias network, and the other end of the sixteenth resistor serves as the output terminal of the second drain bias network.

[0036] In some embodiments, the first width is 4×15μm, the second width is 4×20μm, and the third width is 4×25μm.

[0037] Secondly, this application also provides an integrated circuit including the power amplifier described in the first aspect.

[0038] Thirdly, this application also provides a chip, including a circuit board and the integrated circuit described in the second aspect, wherein the integrated circuit is disposed on the circuit board.

[0039] Fourthly, this application also provides a transmitting terminal, including the chip described in the third aspect.

[0040] The power amplifier, integrated circuit, chip, and terminal provided in this application include a power amplifier comprising at least four cascaded amplifier circuits, including a first-stage amplifier circuit for receiving the signal to be amplified; at least two second-stage amplifier circuits, the input terminal of the first second-stage amplifier circuit being connected to the output terminal of the first-stage amplifier circuit, and the input and output terminals of adjacent second-stage amplifier circuits being connected; and a third-stage amplifier circuit, the input terminal of which is connected to the output terminal of the last second-stage amplifier circuit. The transistor gate widths used in the first, second, and third-stage amplifier circuits are a first width, a second width, and a third width, respectively, with the second width being greater than the first width and the third width being greater than the second width. Each of the first to third-stage amplifier circuits includes an upper half module and a lower half module, the upper half module and the lower half module being structurally symmetrical. This application, through multi-stage amplification, can significantly improve the overall gain. Each stage amplifier circuit amplifies the input signal, and after multi-stage amplification, the final output signal power is greatly increased, thereby meeting the high power requirements in terahertz communication. In addition, multi-parallel on-chip power combining power amplifiers can combine the output power of multiple amplifier circuits to further improve the overall output power. This can effectively utilize the limited chip area to achieve higher power output and is suitable for the high power requirements of the terahertz band. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of a power amplifier provided in an embodiment of this application.

[0043] Figure 2 This is a circuit diagram of the upper half module provided in an embodiment of this application.

[0044] Figure 3 This is a circuit diagram of the lower half module provided in an embodiment of this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] In the description of the embodiments of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0047] To enable any person skilled in the art to implement and use this application, the following description is provided. In this description, details are set forth for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other instances, well-known processes will not be described in detail to avoid obscuring the description of the embodiments of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in the embodiments of this application.

[0048] In traditional terahertz communication system architectures, Schottky diodes, often used as the final stage component in terahertz mixers, are frequently employed. However, the inherent saturation output power bottleneck of Schottky diodes significantly limits the upper limit of the communication system's transmit power, thus restricting the power of the transmitted signal and severely limiting the effective transmission distance of terahertz wireless communication.

[0049] The power amplifier, integrated circuit, chip, and terminal of this application will be described below with reference to the accompanying drawings to address the above-mentioned problems.

[0050] Reference Figure 1 As shown, Figure 1 This is a schematic diagram of a power amplifier 100 provided in an embodiment of this application, as shown below. Figure 1 As shown, the power amplifier 100 includes:

[0051] Includes at least four cascaded amplifier stages, said at least four cascaded amplifier stages comprising:

[0052] A first-stage amplifier circuit 110 is used to receive the signal to be amplified. The gate width of the transistor used in the first-stage amplifier circuit 110 is a first width.

[0053] At least two second-stage amplifier circuits 120 are provided. The input terminal of the first second-stage amplifier circuit 120 is connected to the output terminal of the first-stage amplifier circuit 110. The input and output terminals of two adjacent second-stage amplifier circuits 120 are connected. The gate width of the transistor used in each second-stage amplifier circuit 120 is a second width, which is greater than the first width.

[0054] A third-stage amplifier circuit 130 is provided, the input terminal of which is connected to the output terminal of the last second-stage amplifier circuit 120. The transistor gate width used in the third-stage amplifier circuit 130 is a third width, which is greater than the second width.

[0055] The first-stage amplifier circuit 110 to the third-stage amplifier circuit 130 each include an upper half module and a lower half module, and the upper half module and the lower half module are structurally symmetrical.

[0056] Specifically, the power amplifier 100, integrated circuit, chip, and terminal provided in this application include at least four cascaded amplifier circuits: a first-stage amplifier circuit 110 for receiving the signal to be amplified; at least two second-stage amplifier circuits 120, with the input terminal of the first second-stage amplifier circuit 120 connected to the output terminal of the first-stage amplifier circuit 110, and the input and output terminals of adjacent second-stage amplifier circuits 120 connected; and a third-stage amplifier circuit 130, with the input terminal connected to the output terminal of the last second-stage amplifier circuit 120. The transistor gate widths used in the first, second, and third-stage amplifier circuits 130 are a first width, a second width, and a third width, respectively, with the second width being greater than the first width and the third width being greater than the second width. Each of the first-stage amplifier circuit 110 to the third-stage amplifier circuit 130 includes an upper half module and a lower half module, with the upper half module and the lower half module having symmetrical structures. This application significantly improves the overall gain through multi-stage amplification. Each stage amplifies the input signal, resulting in a substantial increase in the final output signal power after multiple stages of amplification, thus meeting the high power requirements of terahertz communication. Furthermore, the multi-parallel on-chip power combining amplifier 100 combines the output power of multiple amplifier circuits, further enhancing the overall output power. This effectively utilizes limited chip area to achieve higher power output, making it suitable for the high power demands of the terahertz frequency band.

[0057] Furthermore, since the upper and lower modules are structurally symmetrical, parasitic effects and instabilities caused by asymmetry can be reduced, as well as the impact of power supply voltage fluctuations and temperature changes on the operating point. This ensures good stability of the transistor both within and outside the operating frequency band, thereby improving the overall performance of the circuit. Moreover, the symmetrical circuit structure and good matching design reduce signal distortion during amplification. This helps improve the signal quality of the communication system, ensuring the accuracy and reliability of data transmission. Because the bias conditions and circuit structure of each channel are consistent, this application reduces design complexity, improves manufacturing consistency and reliability, and allows for the addition or reduction of the number of amplifier circuits according to actual needs, flexibly adjusting the output power while maintaining the symmetry and stability of each amplifier circuit, thus expanding the applicability of the power amplifier 100.

[0058] In some embodiments, the upper half module includes: a first transistor Q1, a first gate bias network, a first drain bias network, and an inter-electrode coupling unit;

[0059] The input terminal of the first gate bias network is connected to the output terminal of the previous amplifier circuit;

[0060] The output terminal of the first gate bias network is connected to the gate of the first transistor Q1, the source of the first transistor Q1 is grounded, and the drain of the first transistor Q1 is connected to the input terminal of the first drain bias network.

[0061] The output of the first drain bias network is connected to the input of the inter-electrode coupling unit, and the output of the inter-electrode coupling unit is connected to the input of the next stage amplifier circuit. The first gate bias network and the first drain bias network are structurally symmetrical.

[0062] Specifically, the gate bias network and drain bias network provide stable bias voltage and current for the transistor, ensuring that the transistor maintains a stable quiescent operating point under various operating conditions. This helps reduce performance variations caused by power supply voltage fluctuations, temperature changes, or load variations. The complete symmetry between the first gate bias network and the first drain bias network reduces parasitic effects and instabilities, ensuring stable operation of the amplifier both within and outside its operating frequency band, further improving the overall stability of the circuit. Additionally, inter-electrode coupling units (such as capacitors, inductors, or transmission lines) are used to transmit signals between amplifier stages while isolating DC bias voltages, effectively reducing signal loss and reflection during transmission and ensuring efficient signal transmission between amplifier stages.

[0063] In some embodiments, it further includes: a DC blocking coupling unit;

[0064] The input terminal of the DC blocking coupling unit is connected to the signal to be amplified, and the output terminal of the DC blocking coupling unit is connected to the input terminal of the first gate bias network corresponding to the first stage amplifier circuit 110.

[0065] Specifically, in amplifier circuits, the input signal may contain DC bias voltage. If these DC components are not isolated, they may interfere with the normal operation of the amplifier circuit. This application isolates the DC components in the input signal using a DC blocking coupling unit, allowing only AC signals to pass through. This ensures that the DC components in the input signal do not affect the quiescent operating point of the amplifier circuit, which is crucial for maintaining the stability and linear amplification characteristics of the amplifier circuit. The DC blocking coupling unit can also effectively remove the DC bias in the input signal, thereby reducing nonlinear distortion caused by DC components and improving the signal quality of the amplifier circuit.

[0066] In some embodiments, the DC blocking coupling unit includes a first capacitor C1;

[0067] The first gate bias network includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first inductor L1, a second capacitor C2, and a third capacitor C3;

[0068] One end of the first resistor R1 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded. The other end of the first resistor R1 is connected to one end of the third capacitor C3 and one end of the second resistor R2. The other end of the third capacitor C3 is connected to one end of the first inductor L1, and the other end of the first inductor L1 is grounded.

[0069] The other end of the second resistor R2 is connected to one end of the third resistor R3 and one end of the fourth resistor R4. The other end of the third resistor R3 serves as the input terminal of the first gate bias network. One end of the second capacitor C2 serves as the output terminal of the DC blocking coupling unit. The other end of the first capacitor C1 serves as the input terminal of the DC blocking coupling unit. The other end of the fourth resistor R4 serves as the output terminal of the first gate bias network.

[0070] The first drain bias network includes: a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a second inductor L2, a fourth capacitor C4, and a fifth capacitor C5;

[0071] The inter-electrode coupling unit includes: a sixth capacitor C6;

[0072] One end of the eighth resistor R8 is connected to one end of the fifth capacitor C5, and the other end of the fifth capacitor C5 is grounded. The other end of the eighth resistor R8 is connected to one end of the fourth capacitor C4 and one end of the seventh resistor R7. The other end of the fourth capacitor C4 is connected to one end of the second inductor L2, and the other end of the second inductor L2 is grounded.

[0073] The other end of the seventh resistor R7 is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6. The other end of the fifth resistor R5 serves as the input terminal of the first drain bias network, and the other end of the sixth resistor R6 serves as the output terminal of the first drain bias network.

[0074] Specifically, IN represents the signal input, and OUT represents the signal output. Taking the first-stage amplifier circuit 110 as an example, as follows... Figure 2 As shown, the upper part of the first-stage amplifier circuit 110 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a first inductor L1, a second inductor L2, and a first transistor Q1. One end of the first resistor R1 is connected to one end of the second capacitor C2, and the other end of the first resistor R1 is connected to the third capacitor C3 and the second resistor R2. The other end of the third capacitor C3 is connected to the first inductor L1, and the other end of the first inductor L1 is grounded. The other end of the second resistor R2 is connected to the third resistor R4, the second resistor R5, the third resistor R6, the seventh resistor R7, the eighth resistor R8, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a first inductor L1, a second inductor L2, and a first transistor Q1. One end of resistor R3 and one end of resistor R4 are connected. The other end of resistor R3 is connected to one end of capacitor C1. The other end of resistor R4 is connected to the gate of transistor Q1. The source of transistor Q1 is grounded. The drain of transistor Q1 is connected to one end of resistor R5. The other end of resistor R5 is connected to resistors R6 and R7. The other end of resistor R7 is connected to capacitor C4 and resistor R8. The other end of capacitor C4 is connected to inductor L2. The other end of inductor L2 is grounded. The other end of resistor R8 is connected to capacitor C5. Capacitor C5 is connected to ground. The other end of capacitor C6 is connected to the second stage amplifier circuit 120. Through the synergistic effect of the inductors, capacitors, resistors, and MOSFETs, the overall performance of the amplifier is improved, including gain, output power, stability, and signal quality.

[0075] In some embodiments, the lower half module includes: a second transistor, a second gate bias network, a second drain bias network, and a filtering unit;

[0076] The input terminal of the second gate bias network is connected to the output terminal of the inter-electrode coupling unit of the previous amplifier circuit;

[0077] The output of the second gate bias network is connected to the gate of the second transistor, the source of the second transistor is grounded, and the drain of the second transistor is connected to the input of the second drain bias network.

[0078] The second drain bias network and the second gate bias network are symmetrical in structure. The output terminal of the second drain bias network is connected to the input terminal of the filter unit. The output terminal of the filter unit is connected to the input terminal of the next stage amplifier circuit. The output terminal of the filter unit of the fourth stage amplifier circuit is used to output the amplified signal.

[0079] Specifically, the second gate bias network provides a stable DC bias voltage for the second transistor, ensuring that the transistor operates at a suitable quiescent operating point, which helps maintain the amplifier's stability and linear amplification characteristics. The second drain bias network provides a stable DC bias for the drain of the second transistor, ensuring stable output power and helping to improve the amplifier's output performance. Filtering units (such as low-pass filters and band-pass filters) can filter the amplified signal, removing unwanted frequency components, optimizing signal quality, helping to reduce noise and interference, and improving signal purity. The lower half of the module, through the synergistic effect of the second gate bias network, the second drain bias network, and the filtering units, further improves the overall performance of the amplifier, including gain, output power, stability, and signal quality. The second drain bias network is symmetrical to the second gate bias network. This symmetrical design ensures that the bias conditions of the transistor are consistent in both the vertical and horizontal directions, thereby improving the overall performance and stability of the circuit. Moreover, the symmetrical bias circuit structure simplifies the design and manufacturing process, improving manufacturing consistency and reliability.

[0080] In some embodiments, the second gate bias network includes: a ninth resistor R9, an eleventh resistor R11, a thirteenth resistor R13, a fourteenth resistor R14, a third inductor L3, a seventh capacitor C7, and a ninth capacitor C9.

[0081] One end of the ninth resistor R9 is connected to one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded. The other end of the ninth resistor R9 is connected to one end of the ninth capacitor C9 and one end of the eleventh resistor R11. The other end of the ninth capacitor C9 is connected to one end of the third inductor L3, and the other end of the third inductor L3 is grounded.

[0082] The other end of the eleventh resistor R11 is connected to one end of the thirteenth resistor R13 and one end of the fourteenth resistor R14. The other end of the thirteenth resistor R13 serves as the input terminal of the second gate bias network, and the other end of the fourteenth resistor R14 serves as the output terminal of the second gate bias network.

[0083] The second drain bias network includes: tenth resistor R10, twelfth resistor R12, fifteenth resistor R15, sixteenth resistor R16, fourth inductor L4, eighth capacitor C8 and tenth capacitor C10;

[0084] The inter-electrode coupling unit includes: an eleventh capacitor C11;

[0085] One end of the tenth resistor R10 is connected to one end of the eighth capacitor C8, and the other end of the eighth capacitor C8 is grounded. The other end of the tenth resistor R10 is connected to one end of the tenth capacitor C10 and one end of the twelfth resistor R12. The other end of the tenth capacitor C10 is connected to one end of the fourth inductor L4, and the other end of the fourth inductor L4 is grounded.

[0086] The other end of the twelfth resistor R12 is connected to one end of the fifteenth resistor R15 and one end of the sixteenth resistor R16. The other end of the fifteenth resistor R15 serves as the input terminal of the second drain bias network, and the other end of the sixteenth resistor R16 serves as the output terminal of the second drain bias network.

[0087] Specifically, taking the third-stage amplifier circuit 130 as an example, such as Figure 3As shown, the upper part of the third-stage amplifier circuit 130 includes a ninth resistor R9, an eleventh resistor R11, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a twelfth resistor R12, a tenth resistor R10, a seventh capacitor C7, a ninth capacitor C9, a tenth capacitor C10, an eighth capacitor C8, an eleventh capacitor C11, a third inductor L3, a fourth inductor L4, and a second transistor Q2. One end of the ninth resistor R9 is connected to one end of the seventh capacitor C7, and the other end of the ninth resistor R9 is connected to both the ninth capacitor C9 and the eleventh resistor R11. The other end of the ninth capacitor C9 is connected to the third inductor L3, and the other end of the third inductor L3 is grounded. The other end of the eleventh resistor R11 is connected to the thirteenth resistor R14. One end of resistor R13 and one end of resistor R14 are connected. The other end of resistor R13 is connected to one end of capacitor C1. The other end of resistor R14 is connected to the gate of transistor Q2. The source of transistor Q2 is grounded. The drain of transistor Q2 is connected to one end of resistor R15. The other end of resistor R15 is connected to resistors R16 and R12. The other end of resistor R12 is connected to capacitor C10 and R10. The other end of capacitor C10 is connected to inductor L4. The other end of inductor L4 is grounded. The other end of resistor R10 is connected to capacitor C8. Capacitor C8 is connected to ground. The other end of capacitor C11 outputs the amplified signal. Through the synergistic effect of the inductors, capacitors, resistors, and MOSFETs, the overall performance of the amplifier is improved, including gain, output power, stability, and signal quality.

[0088] The upper half of the second-stage amplifier circuit 120 is completely identical in structure and device connection method to the first-stage amplifier circuit 110, and the upper half of the third-stage amplifier circuit 130 is completely identical in structure and device connection method to the first and second-stage amplifier circuits. The upper half of each amplifier circuit (first-stage amplifier circuit 110, second-stage amplifier circuit 120, and third-stage amplifier circuit 130) is symmetrical to the lower half of the amplifier circuit, and the upper and lower DC bias circuits of the transistors are completely symmetrical.

[0089] In some embodiments, the first width is 4×15μm, the second width is 4×20μm, and the third width is 4×25μm. Specifically, the progressively increasing gate width design in amplifier circuits can optimize gain and power output, reduce noise, improve matching characteristics, enhance circuit stability, and optimize dynamic range. It is particularly suitable for high-frequency terahertz communication, effectively processing wideband signals while maintaining good matching and stability.

[0090] Secondly, this application also provides an integrated circuit including the power amplifier 100 described in the first aspect.

[0091] Thirdly, this application also provides a chip, including a circuit board and the integrated circuit described in the second aspect, wherein the integrated circuit is disposed on the circuit board.

[0092] Fourthly, this application also provides a transmitting terminal, including the chip described in the third aspect.

[0093] This application also provides an integrated circuit, including the power amplifier 100 described in the above embodiments. At least three conductive coils of the power amplifier are embedded in the integrated circuit substrate via metal layer wiring. This integrated circuit is used in a radio frequency front-end module and supports multi-band signal processing.

[0094] This application also provides a chip, including a circuit board and the integrated circuit described in the above embodiments, wherein the integrated circuit is disposed on the circuit board. The integrated circuit is connected to external circuits via solder pads. This chip is integrated into electronic devices such as mobile phones, tablets, and computers. The power amplifier 100 of the above embodiments of this application is designed to effectively cancel external electromagnetic interference and improve signal transmission stability. Moreover, the non-collinear centroid and multi-shape coil combination adapts to the layout requirements of high-density integrated circuits.

[0095] This application also provides a transmitting terminal, including the chip described in the above embodiments.

[0096] In practice, each of the above units or modules can be implemented as an independent entity or can be combined arbitrarily to be implemented as the same or several entities. The implementation of each of the above units or modules for data collection in supply chain management projects can be referred to the previous method implementation examples, and will not be repeated here.

[0097] In the above embodiments, the descriptions of each embodiment have different focuses. Parts not described in detail in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process and beneficial effects of the data acquisition system and its corresponding units described above can be referred to the description of the power amplifier in the above embodiments, and will not be repeated here.

[0098] The power amplifier, integrated circuit, chip, and terminal provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A power amplifier, characterized in that, Includes at least four cascaded amplifier stages, said at least four cascaded amplifier stages comprising: A first-stage amplifier circuit is used to receive the signal to be amplified. The gate width of the transistor used in the first-stage amplifier circuit is a first width. At least two second-stage amplifier circuits are provided. The input terminal of the first second-stage amplifier circuit is connected to the output terminal of the first-stage amplifier circuit. The input and output terminals of two adjacent second-stage amplifier circuits are connected. The gate width of the transistor used in each second-stage amplifier circuit is a second width, which is greater than the first width. A third-stage amplifier circuit, wherein the input terminal of the third-stage amplifier circuit is connected to the output terminal of the last second-stage amplifier circuit, and the transistor gate width used in the third-stage amplifier circuit is a third width, which is greater than the second width; Each of the first-stage amplifier circuit to the third-stage amplifier circuit includes an upper half module and a lower half module, and the upper half module and the lower half module are structurally symmetrical.

2. The power amplifier according to claim 1, characterized in that, The upper part of the module includes: a first transistor, a first gate bias network, a first drain bias network, and an inter-electrode coupling unit; The input terminal of the first gate bias network is connected to the output terminal of the previous amplifier circuit; The output terminal of the first gate bias network is connected to the gate of the first transistor, the source of the first transistor is grounded, and the drain of the first transistor is connected to the input terminal of the first drain bias network. The output of the first drain bias network is connected to the input of the inter-electrode coupling unit, and the output of the inter-electrode coupling unit is connected to the input of the next stage amplifier circuit. The first gate bias network and the first drain bias network are structurally symmetrical.

3. The power amplifier according to claim 2, characterized in that, Also includes: DC blocking coupling unit; The input terminal of the DC blocking coupling unit is connected to the signal to be amplified, and the output terminal of the DC blocking coupling unit is connected to the input terminal of the first gate bias network corresponding to the first stage amplifier circuit.

4. The power amplifier according to claim 3, characterized in that, The DC blocking coupling unit includes a first capacitor; The first gate bias network includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a first inductor, a second capacitor, and a third capacitor; One end of the first resistor is connected to one end of the second capacitor, and the other end of the second capacitor is grounded. The other end of the first resistor is connected to one end of the third capacitor and one end of the second resistor. The other end of the third capacitor is connected to one end of the first inductor, and the other end of the first inductor is grounded. The other end of the second resistor is connected to one end of the third resistor and one end of the fourth resistor. The other end of the third resistor serves as the input terminal of the first gate bias network. One end of the second capacitor serves as the output terminal of the DC blocking coupling unit. The other end of the first capacitor serves as the input terminal of the DC blocking coupling unit. The other end of the fourth resistor serves as the output terminal of the first gate bias network. The first drain bias network includes: a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a second inductor, a fourth capacitor, and a fifth capacitor; The inter-electrode coupling unit includes: a sixth capacitor; One end of the eighth resistor is connected to one end of the fifth capacitor, the other end of the fifth capacitor is grounded, the other end of the eighth resistor is connected to one end of the fourth capacitor and one end of the seventh resistor, the other end of the fourth capacitor is connected to one end of the second inductor, and the other end of the second inductor is grounded; The other end of the seventh resistor is connected to one end of the fifth resistor and one end of the sixth resistor. The other end of the fifth resistor serves as the input terminal of the first drain bias network, and the other end of the sixth resistor serves as the output terminal of the first drain bias network.

5. The power amplifier according to claim 4, characterized in that, The lower half module includes: a second transistor, a second gate bias network, a second drain bias network, and a filtering unit; The input terminal of the second gate bias network is connected to the output terminal of the inter-electrode coupling unit of the previous amplifier circuit; The output of the second gate bias network is connected to the gate of the second transistor, the source of the second transistor is grounded, and the drain of the second transistor is connected to the input of the second drain bias network. The second drain bias network and the second gate bias network are symmetrical in structure. The output terminal of the second drain bias network is connected to the input terminal of the filter unit. The output terminal of the filter unit is connected to the input terminal of the next stage amplifier circuit. The output terminal of the filter unit of the fourth stage amplifier circuit is used to output the amplified signal.

6. The power amplifier according to claim 5, characterized in that, The second gate bias network includes: a ninth resistor, an eleventh resistor, a thirteenth resistor, a fourteenth resistor, a third inductor, a seventh capacitor, and a ninth capacitor; One end of the ninth resistor is connected to one end of the seventh capacitor, the other end of the seventh capacitor is grounded, the other end of the ninth resistor is connected to one end of the ninth capacitor and one end of the eleventh resistor, the other end of the ninth capacitor is connected to one end of the third inductor, and the other end of the third inductor is grounded. The other end of the eleventh resistor is connected to one end of the thirteenth resistor and one end of the fourteenth resistor. The other end of the thirteenth resistor serves as the input terminal of the second gate bias network, and the other end of the fourteenth resistor serves as the output terminal of the second gate bias network. The second drain bias network includes: a tenth resistor, a twelfth resistor, a fifteenth resistor, a sixteenth resistor, a fourth inductor, an eighth capacitor, and a tenth capacitor; The inter-electrode coupling unit includes: an eleventh capacitor; One end of the tenth resistor is connected to one end of the eighth capacitor, the other end of the eighth capacitor is grounded, the other end of the tenth resistor is connected to one end of the tenth capacitor and one end of the twelfth resistor, the other end of the tenth capacitor is connected to one end of the fourth inductor, and the other end of the fourth inductor is grounded. The other end of the twelfth resistor is connected to one end of the fifteenth resistor and one end of the sixteenth resistor. The other end of the fifteenth resistor serves as the input terminal of the second drain bias network, and the other end of the sixteenth resistor serves as the output terminal of the second drain bias network.

7. The power amplifier according to any one of claims 1 to 6, characterized in that, The first width is 4×15μm, the second width is 4×20μm, and the third width is 4×25μm.

8. An integrated circuit, characterized in that, Includes the power amplifier as described in any one of claims 1 to 7.

9. A chip, characterized in that, It includes a circuit board and the integrated circuit of claim 8, wherein the integrated circuit is disposed on the circuit board.

10. A transmitting terminal, characterized in that, Includes the chip described in claim 9.

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