An interface output circuit

Abstract

The utility model relates to load identification and protection technical field discloses an interface output circuit with load identification function, including controller (110), level output circuit (120), load identification circuit (130) and signal feedback circuit (140), wherein, when the resistance value of load (RL) is below minimum resistance value threshold value, load identification circuit (130) according to current state pulls the voltage of output end of level output circuit (120) to low level, and triggers signal feedback circuit (140) to output the high level signal of abnormal indication to controller (110).

Description

Technical Field

[0001] This utility model relates to the field of load identification and protection technology, and more specifically, to an interface output circuit. Background Technology

[0002] Existing SOC or MCU chips generally lack load identification functionality in their logic level output interfaces. When the load resistor connected to the interface is too small or a short circuit occurs, the output current will increase sharply, easily damaging the switching transistors in the chip's internal interface circuit due to overcurrent. This problem is particularly prominent in cost-sensitive or space-constrained applications, where the lack of integrated load identification and protection mechanisms in the chip design severely impacts system reliability.

[0003] Currently, there is no circuit structure in the industry that can identify the load status of the output interface in real time and automatically cut off the output to protect the chip when the load is abnormal.

[0004] Therefore, there is an urgent need for an interface output circuit with load identification and protection functions to solve the problem of interface damage caused by abnormal load in the existing technology and improve the stability and security of the system. Utility Model Content

[0005] The technical problem to be solved by this utility model is to address the defect in the prior art where, when the load resistance connected to the interface is too small or a short circuit occurs, the output current of the output interface increases sharply, which can easily damage the switching transistor of the internal interface circuit of the chip due to overcurrent. This utility model provides an interface output circuit that can automatically cut off the high-level output and has a load identification function when the load resistance is detected to be lower than a set threshold.

[0006] The technical solution adopted by this utility model to solve its technical problem is: to construct an interface output circuit, which has the following features:

[0007] Controller;

[0008] The level output circuit has a minimum resistance threshold value, wherein,

[0009] The input terminal of the level output circuit is coupled to one output terminal of the controller for receiving a control signal.

[0010] The output terminal of the level output circuit is connected to one end of the load, and is inverted and output according to the level state of the input control signal.

[0011] A load identification circuit, whose input terminal is connected to the output terminal of the level output circuit, is used to detect the resistance value of the load and determine whether the resistance value is lower than the minimum resistance threshold value.

[0012] A signal feedback circuit, the input of which is coupled to the output of the load identification circuit, and the output of the signal feedback circuit is connected to the feedback terminal of the controller;

[0013] Specifically, when the resistance value of the load is lower than the minimum resistance threshold, the load identification circuit pulls the voltage at the output terminal of the level output circuit to a low level according to the current state, and triggers the signal feedback circuit to output a high-level signal indicating an abnormality to the controller.

[0014] In some embodiments, the level output circuit includes a threshold setting module and a push-pull output module, wherein,

[0015] The threshold setting module is used to set the minimum resistance threshold value, and one end of the threshold setting module is connected to an input terminal of the load identification circuit.

[0016] The other end of the threshold setting module is connected to one end of the push-pull output module.

[0017] The other end of the push-pull output module is connected to one end of the load.

[0018] In some implementations, the threshold setting module includes a second resistor.

[0019] The second resistor is connected in series between the power supply and one end of the push-pull output module;

[0020] The minimum resistance threshold value is set by the resistance value of the second resistor.

[0021] In some embodiments, the push-pull output module includes a first MOSFET and a second MOSFET.

[0022] The gates of the first MOSFET and the second MOSFET are connected to the first terminal of the load identification circuit.

[0023] The gates of the first MOSFET and the second MOSFET are connected to the second terminal of the load identification circuit through a first resistor.

[0024] The drain of the first MOSFET is connected to the drain of the second MOSFET.

[0025] The source of the second MOSFET is connected to one end of the second resistor.

[0026] The source of the first MOSFET is connected to the common terminal.

[0027] In some embodiments, the load identification circuit includes at least

[0028] The comparison trigger module has its input connected to the output of the push-pull output module and one end of the threshold setting module.

[0029] When the level output circuit outputs a high level, it compares the voltage at the output terminal of the level output circuit with a reference voltage, and outputs a trigger signal when the resistance of the load is lower than the minimum resistance threshold.

[0030] A feedback control module, one end of which is connected to one end of the comparison trigger module, is used to respond to the trigger signal to pull the voltage at the output terminal of the push-pull output module to a low level and output a feedback voltage.

[0031] In some implementations, the comparison trigger module includes a third MOS transistor;

[0032] The gate of the third MOS transistor is connected to the output terminal of the push-pull output module.

[0033] The source of the third MOS transistor is connected to one end of the second resistor and the power supply.

[0034] The drain of the third MOS transistor serves as the output terminal of the trigger signal;

[0035] When the voltage at the output terminal of the push-pull output module is lower than the difference between the power supply voltage and the turn-on voltage of the third MOSFET, the third MOSFET is turned on.

[0036] In some implementations, the feedback control module includes a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET;

[0037] The source of the fourth MOS transistor is connected to the drain of the third MOS transistor, and the gate of the fourth MOS transistor is connected to the gate of the first MOS transistor.

[0038] The drain of the fourth MOS transistor is connected to the gate of the sixth MOS transistor.

[0039] The gate of the fifth MOS transistor and the drain of the sixth MOS transistor are connected to an input terminal of the signal feedback circuit.

[0040] The drain of the sixth MOS transistor serves as the output terminal of the feedback control module, which outputs the feedback voltage.

[0041] The gate of the sixth MOS transistor is connected to the common terminal through the third resistor;

[0042] The gate of the fourth MOS transistor is connected to the power supply through the first resistor;

[0043] When both the third and fourth MOSFETs are turned on, the feedback control module enters a negative feedback balance state, causing the sixth MOSFET to be critically turned on and output a stable feedback voltage.

[0044] The gate of the fourth MOS transistor is at a high level, which controls the first MOS transistor to turn on and the second MOS transistor to turn off, thereby pulling the voltage at the output terminal of the push-pull output module to a low level.

[0045] In some embodiments, the signal feedback circuit includes at least a seventh MOS transistor.

[0046] The gate of the seventh MOSFET is connected to the drain of the sixth MOSFET through an RC delay circuit, and the feedback voltage is input to the gate of the seventh MOSFET through the RC delay circuit.

[0047] The drain of the seventh MOS transistor is connected to the input terminal of the signal feedback circuit.

[0048] The source of the seventh MOS transistor is connected to the common terminal.

[0049] In some embodiments, the signal feedback circuit further includes an eighth MOS transistor.

[0050] The gate of the eighth MOS transistor is connected to the drain of the sixth MOS transistor to receive the feedback voltage.

[0051] The source of the eighth MOS transistor is connected to the power supply.

[0052] The drain of the eighth MOS transistor is connected to the input terminal of the signal feedback circuit;

[0053] When the feedback voltage is low, the seventh MOS transistor is turned off and the eighth MOS transistor is turned on, pulling the voltage at the input of the signal feedback circuit to a high level.

[0054] When the feedback voltage is high, the seventh MOS transistor is turned on and the eighth MOS transistor is turned off, pulling the voltage at the input of the signal feedback circuit to a low level.

[0055] In some embodiments, the RC delay circuit includes a fourth resistor and a first capacitor connected in series.

[0056] One end of the fourth resistor is connected to the drain of the sixth MOS transistor to receive the feedback voltage.

[0057] The other end of the fourth resistor and one end of the first capacitor are respectively connected to the gate of the seventh MOS transistor, and the other end of the first capacitor is connected to the common terminal.

[0058] The interface output circuit of this invention includes a controller, a level output circuit, a load identification circuit, and a signal feedback circuit. When the resistance of the load is lower than the minimum resistance threshold, the load identification circuit pulls the voltage at the output terminal of the level output circuit to a low level based on the current state, and triggers the signal feedback circuit to output a high-level signal indicating an abnormality to the controller. Compared with the prior art, on the one hand, by obtaining the current load resistance value through the load identification circuit and then analyzing and processing it, the controller's output interface has a load identification function. It can determine whether the resistance value of the load connected to the interface is less than the preset minimum resistance value (minimum resistance threshold), and the identification result can be fed back to the controller, allowing the controller to monitor the load connected to the interface in real time.

[0059] On the other hand, this design also has the function of protecting the interface. When the load connected to the interface is too small, it will force the output level of the level output circuit to be pulled to a low level to prevent excessive current output from burning out the electronic components inside the output interface circuit. Attached Figure Description

[0060] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings:

[0061] Figure 1 This is a circuit schematic diagram of an embodiment of the interface output circuit provided by this utility model;

[0062] Figure 2 This is a schematic diagram of the voltage at various points of the load identification circuit under protected state provided by this utility model;

[0063] Figure 3 This is a schematic diagram of the present invention when RL > RLmin, Vi = 1, or when the object is suspended.

[0064] Figure 4 This is a schematic diagram of the present invention when RL > RLmin and Vi = 0;

[0065] Figure 5 This is a schematic diagram of the present invention when RL < RLmin, Vi = 1, or when the object is suspended.

[0066] Figure 6 This is a schematic diagram of the present invention when RL < RLmin and Vi = 0;

[0067] Figure 7 This is the waveform diagram of the output when RL > Rlmin provided by this utility model;

[0068] Figure 8 This is the waveform diagram of the output when RL < Rlmin provided by this utility model. Detailed Implementation

[0069] To provide a clearer understanding of the technical features, objectives, and effects of this utility model, the specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings.

[0070] like Figures 1-8 As shown, in the first embodiment of the interface output circuit of this utility model, the interface output circuit 10 includes a controller 110, a level output circuit 120, a load identification circuit 130, and a signal feedback circuit 140.

[0071] The controller 110 has the functions of logic operation, signal reception and analysis, and output control signal;

[0072] The level output circuit 120 is used to output logic levels. The level of its output terminal (corresponding to Vo) is out of phase with the level of its input terminal (corresponding to Vi). The load RL is connected to the output terminal (corresponding to Vo), while the input terminal (corresponding to Vi) is connected to the output terminal of the controller 110. The logic level of Vi is provided by the controller 110.

[0073] When a low level is input to the input terminal (corresponding to Vi), the output terminal (corresponding to Vo) will output a high level to the load RL;

[0074] When a high level is input to the input terminal (corresponding to Vi), the output terminal (corresponding to Vo) will output a low level to the load RL;

[0075] The function of the load identification circuit 130 is to determine whether the resistance of the load RL connected to the output terminal (corresponding to Vo) meets the specified value.

[0076] If the resistance of the load RL connected to the output terminal (corresponding to Vo) is greater than the preset value / minimum resistance threshold, the load identification circuit 130 will not provide protection, and the input Vi can normally control the level of the output Vo.

[0077] If the load resistance connected to the output terminal (corresponding to Vo) is less than the preset value / minimum resistance threshold, the load identification circuit 130 will play a protective role, keeping the output terminal (corresponding to Vo) at a low level when the input at the input terminal (corresponding to Vi) is low.

[0078] If the input at the input terminal (corresponding to Vi) is high, then the output terminal (corresponding to Vo) will normally output a low level.

[0079] That is, when the load identification circuit 130 is in protective mode, the output of the output terminal (corresponding to Vo) will always be low level, thereby preventing excessive interface output current from burning out the MOS transistor in the level output circuit 120;

[0080] The function of the signal feedback circuit 140 is to feed back a signal from the INT port to the controller 110 based on whether the load identification circuit 130 is in a protective role, so that the controller 110 can determine whether the load RL connected to the current output port Vo meets the specified value.

[0081] When the load identification circuit 130 is in protection mode, when the input terminal (corresponding to Vi) is low, the INT port of the signal feedback circuit will output a high level, indicating that the resistance of the load RL connected to the output terminal (corresponding to Vo) is too small and does not meet the specified requirements.

[0082] If the input terminal (corresponding to Vi) is high, the INT port of the signal feedback circuit 140 will output a low level.

[0083] When the load identification circuit 130 does not perform its protection function, regardless of whether the input terminal (corresponding to Vi) is high or low, the INT port of the signal feedback circuit 140 will output a low level, indicating that the load resistor RL connected to the output terminal (corresponding to Vo) meets the specified requirements.

[0084] That is, when the load identification circuit 130 is in protection mode, the INT output will change in opposite phase as the input terminal (corresponding to Vi) changes high or low level, indicating that the resistance value of the load RL connected to the output terminal (corresponding to Vo) is too small.

[0085] When the load identification circuit 130 does not provide protection, the INT output will remain low, indicating that the resistance value of the load RL connected to the output terminal (corresponding to Vo) meets the specified requirements.

[0086] Specifically, the controller 110 is configured in the interface output circuit to receive feedback voltage and output control signals;

[0087] Furthermore, the level output circuit 120 is provided with a preset value / minimum resistance threshold value, wherein,

[0088] The input terminal (corresponding to Vi) of the level output circuit 120 is coupled to an output terminal (corresponding to Vi) of the controller 110, and is used to receive a control signal (corresponding to Vi). The input control signal (corresponding to Vi) is used to control the on / off state of the level output circuit 120.

[0089] Furthermore, the output terminal (corresponding to Vo) of the level output circuit 120 is connected to one end of the load RL. The level output circuit 120 can be controlled to output an inverted signal according to the level state (high level or low level) of the input control signal (corresponding to Vi).

[0090] That is, when the input control signal (corresponding to Vi) is high, the level output circuit 120 outputs a low level.

[0091] When the input control signal (corresponding to Vi) is low, the level output circuit 120 outputs a high level;

[0092] Furthermore, the input terminal of the load identification circuit 130 is connected to the output terminal (corresponding to Vo) of the level output circuit 120, which is used to detect the resistance value of the load RL and determine whether the resistance value is lower than the preset value / minimum resistance threshold value.

[0093] The input terminal of the signal feedback circuit 140 is coupled to the output terminal (corresponding to D) of the load identification circuit 130, and the output terminal (corresponding to INT) of the signal feedback circuit 140 is connected to the feedback terminal (corresponding to INT) of the controller 110, and outputs a feedback voltage (corresponding to VD).

[0094] When the resistance of the load RL is lower than the preset value / minimum resistance threshold, the load identification circuit 130 pulls the voltage of the output terminal (corresponding to Vo) of the level output circuit 120 to a low level according to the current state, and triggers the signal feedback circuit 140 to output a high-level signal (corresponding to INT) indicating an abnormality to the controller 110.

[0095] Using this technical solution, on the one hand, the current resistance value of the load RL is obtained through the load identification circuit 130, and then analyzed and processed to enable the output interface of the controller 110 to have a load identification function. It can determine whether the resistance value of the load connected to the interface is less than the preset minimum resistance value (minimum resistance threshold value), and the identification result can be fed back to the controller 110 so that the controller 110 can monitor the load connected to the interface in real time.

[0096] On the other hand, this design also has the function of protecting the interface. When the load connected to the interface is too small, it will force the output level of the level output circuit 120 to be pulled to a low level to prevent excessive current output from burning out the electronic components inside the output interface circuit, thereby improving the safety and reliability of the interface output circuit operation.

[0097] In some implementations, such as Figures 1-6 As shown, to accommodate different load resistance values, the level output circuit 120 includes a threshold setting module and a push-pull output module.

[0098] The threshold setting module is used to set the preset value / minimum resistance threshold value.

[0099] One end of the threshold setting module is connected to one input of the load identification circuit 130 to obtain the resistance value of the current load RL;

[0100] The other end of the threshold setting module is connected to one end of the push-pull output module.

[0101] The other end of the push-pull output module is connected to one end of the load RL.

[0102] In some implementations, such as Figures 1-6 As shown, the threshold setting module includes a second resistor R102, wherein the preset value / minimum resistance threshold value can be set by adjusting the resistance value of the second resistor R102, so that the interface output circuit can set different specified resistance values ​​for different loads RL.

[0103] The second resistor R102 is connected in series between the power supply VCC and one end of the push-pull output module.

[0104] Specifically, the minimum load resistance setting:

[0105] RL is the load. One end of the load RL is connected to the output terminal (corresponding to Vo) of the push-pull output module. Under normal circumstances, the resistance of the load RL connected to the controller 110 interface is mostly in the kΩ range. If the load RL is damaged, the load resistance will drop to between a few Ω and tens of Ω. In some cases, the resistance of the load RL will become 0Ω when it is completely burned out.

[0106] When the load RL is damaged for some reason, the resistance of the load RL will decrease, which will cause the pull current of the controller 110 output interface to increase, thereby causing the output voltage Vo of the controller 110 output interface to decrease.

[0107] When Vo is lower than the minimum threshold for high-level detection, the high level at the output (corresponding to Vo) may be neither high nor low, affecting the load's level recognition. Therefore, when outputting a high level at the output (corresponding to Vo), it is essential to ensure that the voltage value at the output (corresponding to Vo) is greater than the minimum threshold for high-level detection. H.min .

[0108] In some implementations, such as Figures 1-6 As shown, the push-pull output module includes a first MOSFET Q101 and a second MOSFET Q102. The first MOSFET Q101 is selected as an N-channel MOSFET, and the second MOSFET Q102 is selected as a P-channel MOSFET, both of which have the function of switching.

[0109] Specifically, the gates of the first MOSFET Q101 and the second MOSFET Q102 are connected to the first terminal of the load identification circuit 130.

[0110] The gates of the first MOSFET Q101 and the second MOSFET Q102 are connected to the second terminal of the load identification circuit 130 through the first resistor R101.

[0111] Among them, the first resistor R101 is a pull-up resistor, one end of which is connected to the power supply VCC terminal.

[0112] The drain of the first MOSFET Q101 is connected to the drain of the second MOSFET Q102.

[0113] The source of the second MOSFET Q102 is connected to one end of the second resistor R102.

[0114] The source of the first MOSFET Q101 is connected to the common terminal.

[0115] That is, when the first MOSFET Q101 is turned on, the second MOSFET Q102 is turned off, and vice versa.

[0116] In some implementations, such as Figures 1-6 As shown, the load identification circuit 130 includes at least a comparison trigger module.

[0117] The input of the comparison trigger module is connected to the output of the push-pull output module (corresponding to Vo) and one end of the threshold setting module.

[0118] The comparison trigger module is used to compare the voltage at the output terminal (corresponding to Vo) of the level output circuit 120 with a reference voltage when the level output circuit 120 outputs a high level, and outputs a trigger signal when the resistance value of the load RL is lower than the minimum resistance threshold value.

[0119] One end of the feedback control module is connected to one end of the comparison trigger module. In response to the trigger signal, the voltage of the output terminal (corresponding to Vo) of the push-pull output module is pulled to a low level, and a feedback voltage VD is output to the signal feedback circuit 140.

[0120] In some implementations, such as Figures 1-6 As shown, the comparison trigger module includes a third MOSFET Q103, wherein the third MOSFET Q103 is selected as a P-channel MOSFET.

[0121] Specifically, the gate of the third MOSFET Q103 is connected to the output terminal (corresponding to Vo) of the push-pull output module.

[0122] The source of the third MOSFET Q103 is connected to one end of the second resistor R102 and the power supply VCC.

[0123] The drain of the third MOSFET Q103 is used as the output terminal of the trigger signal;

[0124] When the voltage at the output terminal (corresponding to Vo) of the push-pull output module is lower than the difference between the power supply VCC voltage and the turn-on voltage Vth_Q103 of the third MOSFET Q103, the third MOSFET Q103 is turned on.

[0125] Specifically, the third MOSFET Q103 is used to determine whether the voltage at the output terminal (corresponding to Vo) of the push-pull output module is greater than the minimum value V for determining a high level when a high level is output.H.min The voltage when Vo < V H.min When this happens, the third MOSFET Q103 will turn on, turning on the power supply VCC to the source of the fourth MOSFET Q104;

[0126] Assume the resistance of the load RL is lower than RL min If the load RL is abnormal, the circuit's judgment value for the minimum load RL can be adjusted by setting the value of the second resistor R102. The calculation formula is as follows:

[0127] Among them, V TP.Q103 is the maximum gate-source voltage when the third MOSFET Q103 is turned on, and is the turn-on voltage of the third MOSFET Q103;

[0128] When RL < RL min At that time, the third MOSFET Q103 is turned on;

[0129] When RL > RL min At that time, the third MOSFET Q103 is controlled to turn off.

[0130] In some implementations, such as Figures 1-6 As shown, the feedback control module includes a fourth MOSFET Q104, a fifth MOSFET Q105, and a sixth MOSFET Q106; wherein, the fourth MOSFET Q104 is selected as a P-channel MOSFET, the fifth MOSFET Q105 is selected as an N-channel MOSFET, and the sixth MOSFET Q106 is selected as a P-channel MOSFET, all of which have the function of switching;

[0131] Specifically, the source of the fourth MOSFET Q104 is connected to the drain of the third MOSFET Q103, and the gate of the fourth MOSFET Q104 is connected to the gate of the first MOSFET Q101.

[0132] The drain of the fourth MOSFET Q104 is connected to the gate of the sixth MOSFET Q106.

[0133] The gate of the fifth MOSFET Q105 and the drain of the sixth MOSFET Q106 are connected to an input terminal of the signal feedback circuit 140.

[0134] The drain of the sixth MOSFET Q106 serves as the output terminal of the feedback control module, outputting the feedback voltage (corresponding to VD).

[0135] The gate of the sixth MOSFET Q106 is connected to the common terminal (corresponding to GND) through the third resistor R103;

[0136] The gate of the fourth MOSFET Q104 is connected to the power supply VCC through the first resistor R101;

[0137] When both the third MOSFET Q103 and the fourth MOSFET Q104 are turned on, the feedback control module enters a negative feedback balance state, causing the sixth MOSFET Q106 to be critically turned on and output a stable feedback voltage (corresponding to VD).

[0138] When the gate of the fourth MOSFET Q104 is at a high level, it controls the first MOSFET Q101 to turn on and the second MOSFET Q102 to turn off, pulling the voltage at the output terminal (corresponding to Vo) of the push-pull output module to a low level.

[0139] Specifically, such as Figure 2 , Figure 3 and Figure 5 As shown, when the input terminal (corresponding to Vi) is high or Vi is floating, the fifth MOSFET Q105 is turned off, and the voltage at point B is pulled high by the first resistor R110. At this time, the second MOSFET Q102 will be turned off, while the first MOSFET Q101 will be turned on, and the output terminal (corresponding to Vo) will be low. In this case, the output terminal (corresponding to Vo) only has sinking current and there will be no sourcing current. Naturally, there will be no situation where the sourcing current is too large and burns out the second MOSFET Q102.

[0140] Although point A is at a low level, causing the third MOSFET Q103 to conduct, point B is at a high level, so the fourth MOSFET Q104 is in the off state. Therefore, the voltage at point C will be pulled low by the third resistor R103, which will cause the sixth MOSFET Q106 to conduct, bringing the voltage at point D to the power supply VCC.

[0141] Therefore, when the input terminal (corresponding to Vi) is high or Vi is floating, regardless of the value of the load RL, the output terminal (corresponding to Vo) is low, and the voltage at point D is the power supply VCC.

[0142] When the input terminal (corresponding to Vi) is low, the second MOSFET Q102 is triggered to turn on, making the output terminal (corresponding to Vo) high.

[0143] When RL < RL min At this time, the third MOSFET Q103 is turned on, and the source voltage of the fourth MOSFET Q104 becomes the power supply VCC;

[0144] Previously, the third resistor R103 pulled the voltage at point C down to a low level of 0V, causing the sixth MOSFET Q106 to turn on, making the voltage at point D become the power supply VCC. Since the input terminal (corresponding to Vi) is at a low level, the fifth MOSFET Q105 also turns on, and point B is at a low level.

[0145] When the third MOSFET Q103 turns on and changes the source voltage of the fourth MOSFET Q104 to the power supply VCC, the fourth MOSFET Q104 turns on because point B is at a low level, which causes the voltage at point C to rise from 0V.

[0146] During the voltage rise at point C, the gate-source voltage of the sixth MOSFET Q106 gradually increases, causing the sixth MOSFET Q106 to gradually turn off from the on state. This causes the voltage at point D to gradually decrease from the power supply VCC. The decrease in the voltage at point D will cause the gate-source voltage of the fifth MOSFET Q105 to gradually decrease, which causes the voltage at point B to gradually increase under the pull-up effect of the first resistor R101.

[0147] Since the third MOSFET Q103 remains on, the increase in the voltage at point B will cause the gate-source voltage of the fourth MOSFET Q104 to gradually increase. This causes the fourth MOSFET Q104 to gradually transition from a fully on state to a off state, and the rise rate of the output voltage of the fourth MOSFET Q104 will slow down. Figure 2 The figure shows the voltage values ​​at various points when the load RL is too small and the load identification circuit 130 is triggered to activate protection when the input Vi is low.

[0148] Ultimately, under the influence of negative feedback, the fourth MOSFET Q104, the fifth MOSFET Q105, and the sixth MOSFET Q106 remain in a critical conduction state, and the voltage at point C stabilizes at VCC+V. TP.Q106 The voltage at point D stabilizes at V. TN.Q105 The voltage at point B remains stable at VCC+V. TP.Q104 .

[0149] When selecting the first MOSFET Q101, it should be chosen so that its turn-on voltage is less than VCC + V. TP.Q104 The switching transistor, namely the turn-on voltage V of the first MOSFET Q101. TN.Q101 <VCC+V TP.Q104 ;

[0150] When selecting the second MOSFET Q102, it should be chosen so that its turn-on voltage is less than V. TP.Q104 The switching transistor, namely the second MOSFET Q102, has a turn-on voltage V. TP.Q102 <V TP.Q104 This ensures that when the load identification circuit 130 is in protective mode, the second MOSFET Q102 is turned off, while the first MOSFET Q101 is turned on.

[0151] When the load identification circuit 130 is activated for protection, the output Vo will be turned on to GND by the first MOSFET Q101, and the second MOSFET Q102 will disconnect the load RL from the power supply VCC to prevent excessive pull-up current from flowing through the second MOSFET Q102 and causing damage to the second MOSFET Q102.

[0152] In summary, when the input Vi is low, if the load resistance RL is less than the set minimum resistance value RLmin, the load identification circuit 130 will activate its protection function, and the output Vo will be forcibly pulled low, causing the voltage at point D to become V. TN.Q105 .

[0153] In some embodiments, the signal feedback circuit 140 includes at least a seventh MOSFET Q107, wherein the seventh MOSFET Q107 is selected as an N-channel MOSFET and has a switching function;

[0154] Specifically, the gate of the seventh MOSFET Q107 is connected to the drain of the sixth MOSFET Q106 through an RC delay circuit, and the feedback voltage VD is input to the gate of the seventh MOSFET Q107 through the RC delay circuit.

[0155] The drain of the seventh MOSFET Q107 is connected to the output terminal (corresponding to F) of the signal feedback circuit 140.

[0156] The source of the seventh MOSFET Q107 is connected to the common terminal (corresponding to GND).

[0157] In some embodiments, the signal feedback circuit 140 further includes an eighth MOSFET Q108, wherein the eighth MOSFET Q108 is selected as a P-channel MOSFET and has a switching function;

[0158] Specifically, the gate of the eighth MOSFET Q108 is connected to the drain of the sixth MOSFET Q106 to receive the feedback voltage VD.

[0159] The source of the eighth MOSFET Q108 is connected to the power supply VCC.

[0160] The drain of the eighth MOSFET Q108 is connected to the output terminal (corresponding to F) of the signal feedback circuit 140;

[0161] When the feedback voltage VD is low, the seventh MOSFET Q107 is turned off and the eighth MOSFET Q108 is turned on, pulling the voltage at the output terminal (corresponding to F) of the signal feedback circuit 140 to a high level.

[0162] When the feedback voltage VD is high, the seventh MOSFET Q107 is turned on and the eighth MOSFET Q108 is turned off, pulling the voltage at the output terminal (corresponding to F) of the signal feedback circuit 140 to a low level.

[0163] In some implementations, the RC delay circuit includes a fourth resistor R104 and a first capacitor C101 connected in series.

[0164] One end of the fourth resistor R104 is connected to the drain of the sixth MOSFET Q106 to receive the feedback voltage VD.

[0165] The other end of the fourth resistor R104 and one end of the first capacitor C101 are respectively connected to the gate of the seventh MOS transistor Q107, and the other end of the first capacitor C101 is connected to the common terminal GND.

[0166] Specifically, when the voltage at point D rises, the conduction of the seventh MOSFET Q107 is delayed to prevent a short circuit in the power supply when the eighth MOSFET Q108 is not completely turned off, while the second capacitor C102 is used to store the level state.

[0167] When the load identification circuit 130 is not functioning, the voltage at point D is VCC, the eighth MOSFET Q108 is turned off, and the voltage at point E is pulled high.

[0168] At this time, the output INT of the signal feedback circuit 140 should be low, meaning the seventh MOSFET Q107 should be turned on, pulling the INT terminal low to the common terminal GND. The charge stored in the second capacitor C102 will also be discharged through the seventh MOSFET Q107. Therefore, when selecting the seventh MOSFET Q107, its turn-on voltage must be less than V. E.H Alternatively, the requirements can be met by appropriately setting the resistance values ​​of the fourth resistor R104 and the fifth resistor R105;

[0169] When the load identification circuit 130 is in protective mode, the voltage at point D is V. TN.Q105 The voltage at point E becomes

[0170]

[0171] At this point, the output INT of the signal feedback circuit should be high, meaning the seventh MOSFET Q107 should be off and the eighth MOSFET Q108 should be on. The second capacitor C102 should be charged to VCC. Therefore, when selecting the seventh MOSFET Q107, its turn-on voltage must be greater than VCC. E.L When selecting the eighth MOSFET Q108, it is required that the turn-on voltage of the eighth MOSFET Q108 be greater than V. TN.Q105 -VCC, or by appropriately setting the resistance values ​​of the fourth resistor R104 and the fifth resistor R105 to meet the requirements;

[0172] In summary, when the load identification circuit 130 does not perform its protection function, the INT terminal output is always low, while when the load identification circuit 130 performs its protection function, the INT terminal will have a high-level output.

[0173] Circuit operating states under different loads

[0174] When the resistance of the load RL is normal, i.e., RL > RLmin

[0175] like Figure 3 As shown, when Vi is floating or becomes high (1), the fifth MOS transistor Q105 is turned off. Since the first resistor R101 provides a high pull-up level, that is, point B is high (1), the first MOS transistor Q101 is controlled to be turned on, while the second MOS transistor Q102 is controlled to be turned off. Point A is shorted to the common terminal, and the output terminal (corresponding to Vo) outputs a low level (0).

[0176] That is, when the input Vi is left floating or becomes high (1), the output Vo is low (0);

[0177] Since point A is at a low level (0), the third MOSFET Q103 is turned on. The third MOSFET Q103 turns VCC to the source of the fourth MOSFET Q104. However, since point B is pulled up to a high level (1), the fourth MOSFET Q104 is turned off. As a result, point C is pulled down to a low level (0) by the third resistor R103, which causes the sixth MOSFET Q106 to turn on.

[0178] After the sixth MOSFET Q106 turns on, the voltage at point D rises from 0V to VCC, and at the same time, the voltage at point E also rises from 0V to VCC. E.H The eighth MOSFET Q108 will be turned off, while the seventh MOSFET Q107 will be turned on. Point F will be shorted to GND by the seventh MOSFET Q107, and the second capacitor C102 will discharge the charge. The INT terminal outputs a low level (0).

[0179] like Figure 4 As shown, when Vi is low (0), since the sixth MOSFET Q106 has been turned on and connected point D to VCC, the fifth MOSFET Q105 will be turned on, and point B will be pulled low (0). Then the second MOSFET Q102 will be turned on and the first MOSFET Q101 will be turned off, the voltage at point A will be pulled high, and the output terminal (corresponding to Vo) will be high (1).

[0180] That is, when the input Vi is low (0), the output Vo is high (1);

[0181] Since point A is at a high level (1), the third MOSFET Q103 is turned off. After the third MOSFET Q103 is turned off, the source of the fourth MOSFET Q104 becomes floating, so the fourth MOSFET Q104 is also turned off. Therefore, point C is pulled low to a low level (0) by the third resistor R103, which causes the sixth MOSFET Q106 to remain on.

[0182] The voltage at point D remains constant at VCC, while the voltage at point E continues to remain constant at V. E.H The eighth MOSFET Q108 will continue to be off, while the seventh MOSFET Q107 will continue to be on. Point F will be shorted to the common terminal GND by the seventh MOSFET Q107, and the INT terminal will continue to output a low level (0).

[0183] In summary, when the load resistor RL is normal (RL>RLmin), the interface output (corresponding to Vo) changes in opposite phase with the level of the input Vi, while the INT output will always remain at a low level, indicating that the load connected to the port meets the specified requirements.

[0184] When the load resistance RL is abnormal, i.e. RL < RLmin

[0185] like Figure 5 As shown, when Vi is floating or becomes high (1), the fifth MOS transistor Q105 is turned off. Since the first resistor R101 provides a pull-up high level, that is, point B is high (1), the first MOS transistor Q101 is turned on and the second MOS transistor Q102 is turned off. Point A is shorted to the common terminal GND, and the output terminal (corresponding to Vo) is low (0).

[0186] That is, when the input Vi is left floating or becomes high (1), the output Vo is low (0);

[0187] Since point A is at a low level (0), the third MOSFET Q103 is turned on, and Q103 turns VCC to the source of the fourth MOSFET Q104. However, because point B is pulled up to a high level (1), the fourth MOSFET Q104 is turned off. Therefore, point C is pulled down to a low level (0) by the third resistor R103, which causes the sixth MOSFET Q106 to turn on.

[0188] After the sixth MOSFET Q106 turns on, the voltage at point D rises from 0V to VCC, and at the same time, the voltage at point E also rises from 0V to VCC. E.H The eighth MOSFET Q108 will be turned off, while the seventh MOSFET Q107 will be turned on. Point F will be shorted to the common terminal GND by the seventh MOSFET Q107. The second capacitor C102 will discharge the charge, and the INT terminal will output a low level (0).

[0189] like Figure 6As shown, when Vi is low (0), due to negative feedback, the three switching transistors, the fourth MOSFET Q104, the fifth MOSFET Q105, and the sixth MOSFET Q106, remain in a critical conduction state.

[0190] The voltage values ​​at various points of the load identification circuit 130 are as follows: Figure 6 As shown;

[0191] At this time, the first MOSFET Q101 is turned on while the second MOSFET Q102 is turned off. That is, when the input Vi is low level 0, the output Vo is low level (0).

[0192] Since point A is at a low level (0), the third MOSFET Q103 conducts, turning VCC to the source of the fourth MOSFET Q104. The fourth MOSFET Q104, the fifth MOSFET Q105, and the sixth MOSFET Q106 remain in a critical conduction state, and the voltage at point D becomes V. TN.Q105 ;

[0193] At this moment, the voltage at point E is V. E.L The eighth MOSFET Q108 will be turned on, while the seventh MOSFET Q107 will be turned off. Point F will be turned on to VCC by the eighth MOSFET Q108, the second capacitor C102 will be in a charging state, and the INT terminal will output a high level (1).

[0194] In summary, when the resistance of the load RL is abnormal (RL < RLmin), the interface output (corresponding to Vo) will remain at a low level, while the INT output will change in opposite phase with the level of the input Vi, indicating that the load connected to the port does not meet the specified requirements.

[0195] Interface waveforms of circuits under different loads

[0196] Figure 7 The waveform when the resistance value of the load RL connected to the circuit output interface is greater than the set resistance is shown. Regardless of whether the Vi input level is high or low, the INT port output remains low, indicating that the resistance value of the load RL is normal at this time.

[0197] Figure 8 The waveform when the resistance value of the load RL connected to the circuit output interface is less than the set resistance value is shown. Regardless of whether the input level Vi is high or low, the output Vo remains low, while the output waveform of the INT port is inversely phase with the input Vi, indicating that the resistance value of the load RL is abnormal at this time.

[0198] Therefore, the controller 110 can determine whether the load RL connected to the output interface meets the specified requirements by judging whether the level state fed back by the INT port is always low.

[0199] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. An interface output circuit, characterized in that, have: Controller; The level output circuit has a minimum resistance threshold value, wherein, The input terminal of the level output circuit is coupled to one output terminal of the controller for receiving a control signal. The output terminal of the level output circuit is connected to one end of the load, and is inverted and output according to the level state of the input control signal. A load identification circuit, whose input terminal is connected to the output terminal of the level output circuit, is used to detect the resistance value of the load and determine whether the resistance value is lower than the minimum resistance threshold value. A signal feedback circuit, the input of which is coupled to the output of the load identification circuit, and the output of the signal feedback circuit is connected to the feedback terminal of the controller; Specifically, when the resistance value of the load is lower than the minimum resistance threshold, the load identification circuit pulls the voltage at the output terminal of the level output circuit to a low level according to the current state, and triggers the signal feedback circuit to output a high-level signal indicating an abnormality to the controller.

2. The interface output circuit according to claim 1, characterized in that, The level output circuit includes a threshold setting module and a push-pull output module, wherein... The threshold setting module is used to set the minimum resistance threshold value, and one end of the threshold setting module is connected to an input terminal of the load identification circuit. The other end of the threshold setting module is connected to one end of the push-pull output module. The other end of the push-pull output module is connected to one end of the load.

3. The interface output circuit according to claim 2, characterized in that, The threshold setting module includes a second resistor. The second resistor is connected in series between the power supply and one end of the push-pull output module; The minimum resistance threshold value is set by the resistance value of the second resistor.

4. The interface output circuit according to claim 3, characterized in that, The push-pull output module includes a first MOSFET and a second MOSFET. The gates of the first MOSFET and the second MOSFET are connected to the first terminal of the load identification circuit. The gates of the first MOSFET and the second MOSFET are connected to the second terminal of the load identification circuit through a first resistor. The drain of the first MOSFET is connected to the drain of the second MOSFET. The source of the second MOSFET is connected to one end of the second resistor. The source of the first MOSFET is connected to the common terminal.

5. The interface output circuit according to claim 4, characterized in that, The load identification circuit includes at least the following: The comparison trigger module has its input connected to the output of the push-pull output module and one end of the threshold setting module. When the level output circuit outputs a high level, it compares the voltage at the output terminal of the level output circuit with a reference voltage, and outputs a trigger signal when the resistance of the load is lower than the minimum resistance threshold. A feedback control module, one end of which is connected to one end of the comparison trigger module, is used to respond to the trigger signal to pull the voltage at the output terminal of the push-pull output module to a low level and output a feedback voltage.

6. The interface output circuit according to claim 5, characterized in that, The comparison trigger module includes a third MOS transistor; The gate of the third MOS transistor is connected to the output terminal of the push-pull output module. The source of the third MOS transistor is connected to one end of the second resistor and the power supply. The drain of the third MOS transistor serves as the output terminal of the trigger signal; When the voltage at the output terminal of the push-pull output module is lower than the difference between the power supply voltage and the turn-on voltage of the third MOSFET, the third MOSFET is turned on.

7. The interface output circuit according to claim 6, characterized in that, The feedback control module includes a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET; The source of the fourth MOS transistor is connected to the drain of the third MOS transistor, and the gate of the fourth MOS transistor is connected to the gate of the first MOS transistor. The drain of the fourth MOS transistor is connected to the gate of the sixth MOS transistor. The gate of the fifth MOS transistor and the drain of the sixth MOS transistor are connected to an input terminal of the signal feedback circuit. The drain of the sixth MOS transistor serves as the output terminal of the feedback control module, which outputs the feedback voltage. The gate of the sixth MOS transistor is connected to the common terminal through the third resistor; The gate of the fourth MOS transistor is connected to the power supply through the first resistor; When both the third and fourth MOSFETs are turned on, the feedback control module enters a negative feedback balance state, causing the sixth MOSFET to be critically turned on and output a stable feedback voltage. The gate of the fourth MOS transistor is at a high level, which controls the first MOS transistor to turn on and the second MOS transistor to turn off, thereby pulling the voltage at the output terminal of the push-pull output module to a low level.

8. The interface output circuit according to claim 7, characterized in that, The signal feedback circuit includes at least a seventh MOS transistor. The gate of the seventh MOSFET is connected to the drain of the sixth MOSFET through an RC delay circuit, and the feedback voltage is input to the gate of the seventh MOSFET through the RC delay circuit. The drain of the seventh MOS transistor is connected to the input terminal of the signal feedback circuit. The source of the seventh MOS transistor is connected to the common terminal.

9. The interface output circuit according to claim 8, characterized in that, The signal feedback circuit also includes an eighth MOS transistor. The gate of the eighth MOS transistor is connected to the drain of the sixth MOS transistor to receive the feedback voltage. The source of the eighth MOS transistor is connected to the power supply. The drain of the eighth MOS transistor is connected to the input terminal of the signal feedback circuit; When the feedback voltage is high, the seventh MOSFET is turned off and the eighth MOSFET is turned on, pulling the voltage at the input of the signal feedback circuit to a high level. When the feedback voltage is low, the seventh MOS transistor is turned on and the eighth MOS transistor is turned off, pulling the voltage at the input of the signal feedback circuit to a low level.

10. The interface output circuit according to claim 8, characterized in that, The RC delay circuit includes a fourth resistor and a first capacitor connected in series. One end of the fourth resistor is connected to the drain of the sixth MOS transistor to receive the feedback voltage. The other end of the fourth resistor and one end of the first capacitor are respectively connected to the gate of the seventh MOS transistor, and the other end of the first capacitor is connected to the common terminal.

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