A compact full 10-gigabit ethernet switch with hybrid ports

Abstract

The utility model discloses a compact full gigabit ethernet switch of mixed port, it includes the casing, and the front panel left side of casing is equipped with 6 RJ45 type electric port, and the right side is equipped with 2 SFP+ type optical port, the circuit board is set up in the casing, and the circuit board includes the exchange core circuit, three electric port PHY chips and its peripheral circuit, two way optical port SerDes and its peripheral circuit, dial code rate locking circuit, power tree circuit, heat dissipation and grounding circuit and protection circuit, 6 electric port and 2 optical port realize photoelectricity mixed access through the exchange core circuit, electric port PHY chip and its peripheral circuit, optical port SerDes and its peripheral circuit, and dial code rate locking circuit, power tree circuit, heat dissipation and grounding circuit and protection circuit all are connected with the exchange core circuit electricity. The utility model discloses the above -mentioned scheme has reduced the whole machine cost and power consumption significantly.

Description

Technical Field

[0001] This utility model relates to the field of power supply and interface technology for data communication equipment, specifically a compact 6-electric + 2-optical full 10 Gigabit Ethernet switch with hybrid ports. Background Technology

[0002] With the popularization of technology and the decrease in cost, 10 Gigabit Ethernet switches have become the standard configuration for many scenarios with high bandwidth requirements. They can solve the bottleneck problems brought about by any gigabit scenario. Most 10 Gigabit switches on the market have 8 ports or less, all of which are either all electrical ports or all optical ports. However, although 24-port 10 Gigabit switches have 10 Gigabit electrical ports and optical ports, they may be wasted in some scenarios where the number of electrical ports and optical ports is not required.

[0003] Existing desktop 8-port 10 Gigabit switches are all either "all electrical ports" or "all optical ports," making it impossible to handle both short-distance twisted-pair access and long-distance fiber optic uplink within the same device. Users are forced to purchase two devices or additional optoelectronic conversion modules, resulting in increased costs, power consumption, and potential points of failure.

[0004] While rack-mounted 24-port 10 Gigabit switches offer hybrid optical / electrical ports, their port count is redundant, they are expensive, and they are bulky, resulting in significant waste in scenarios where only 6–8 10 Gigabit nodes are needed.

[0005] Due to space constraints, compact devices present a prominent contradiction between heat dissipation and signal integrity: (1) Multiple DC-DC converters generate concentrated heat, which can easily form local hot spots; (2) The coexistence of 10 Gigabit SerDes and 10 GBase-T analog front-ends results in an incomplete reference plane, leading to deterioration of return loss; (3) High-speed fan operation generates noise, affecting the office environment. Utility Model Content

[0006] A brief overview of embodiments of the present invention is provided below to provide a basic understanding of certain aspects of the invention. It should be understood that this overview is not an exhaustive summary of the invention. It is not intended to identify key or essential parts of the invention, nor is it intended to limit the scope of the invention. Its purpose is merely to present certain concepts in a simplified form as a prelude to the more detailed description that follows.

[0007] To adapt to scenarios requiring both electrical and optical connections, this utility model provides a compact 6-electrical + 2-optical 10 Gigabit Ethernet switch with hybrid ports. The circuit structure of existing switches is improved to simultaneously address the following issues without adding redundancy: on-demand configuration of the hybrid optical and optical ports with zero redundancy; surface temperature rise of the casing ≤20℃ and noise ≤25dB(A) under full load heat dissipation of 80W; return loss >18dB @5GHz at 10Gbps full speed operation, meeting IEEE 02.3an / ch requirements.

[0008] Specifically, this utility model discloses a compact all-10 Gigabit Ethernet switch with hybrid ports, comprising a housing. The front panel of the housing has six RJ45 electrical ports on the left and two SFP+ optical ports on the right. Inside the housing is a circuit board, which includes a switching core circuit, three electrical port PHY (physical layer transceiver) chips and their peripheral circuits, two optical port SerDes and their peripheral circuits, a DIP switch rate locking circuit, a power tree circuit, a heat dissipation and grounding circuit, and a protection circuit. Each electrical port PHY chip is dual-port and is directly connected to the switching core circuit via a USXGMII differential pair. The six electrical ports and two optical ports achieve hybrid optoelectronic access through the switching core circuit, the electrical port PHY chips and their peripheral circuits, and the optical port SerDes and their peripheral circuits. The DIP switch rate locking circuit, the power tree circuit, the heat dissipation and grounding circuit, and the protection circuit are all electrically connected to the switching core circuit.

[0009] Furthermore, the core switching circuit includes a network switching chip, a decoupling unit, a clock unit, and a reset unit; the decoupling unit, clock unit, and reset unit are all electrically connected to the network switching chip; the network switching chip is implemented using a Realtek RTL9300 chip; in the decoupling unit, each power ball corresponds to at least one set of decoupling capacitors, each set consisting of a 0.1µF (0402 package) capacitor and a 4.7µF (0603 package) capacitor connected in parallel; the reset unit uses an RC network with a 10ms delay, and simultaneously sends the data to all electrical port PHY chips.

[0010] Furthermore, the Ethernet PHY chip and its peripheral circuitry include an Ethernet PHY transceiver, a USXGMII serial line, an MDI interface, and a center tap; the dual ports of the Ethernet PHY transceiver are connected to the switching core circuitry via the USXGMII serial line, and the MDI interface and center tap are both connected to the Ethernet PHY transceiver; the Ethernet PHY transceiver is implemented using a chip of model RTL8261BE.

[0011] Furthermore, the optical port SerDes and its peripheral circuitry include SerDes differential pairs, which are connected to the SFP+ cage via a 0.1µFAC coupling capacitor. The LOS, TX_DIS, and TX_FAULT signals of the SFP+ cage are connected to the GPIO of the network switching chip via a 33Ω series resistor to achieve hot-plug detection. As a feasible solution, the SerDes differential pairs are derived from the built-in SerDes of the network switching chip RTL9300.

[0012] Furthermore, the DIP switch rate locking circuit includes a 4-position rotary switch. The output of the rotary switch is connected to the GPIO of the network switching chip. When the switching chip is powered on, it reads the GPIO level and accesses the rate configuration table in the EEPROM accordingly to complete the hardware locking of the optical port rate.

[0013] Furthermore, the power tree circuit includes multiple synchronous buck DC-DC converters, with each output consisting of a 22µF surface-mount capacitor, a 4.7µH power inductor, and a 600Ω@100MHz ferrite bead forming a π-type filter.

[0014] Furthermore, the heat dissipation and grounding circuit includes a thermal pad and an aluminum extruded heat sink on the bottom of the housing; one side of the thermal pad is attached to the exposed copper foil on the back of the PCB, and the other side is attached to the aluminum extruded heat sink.

[0015] Furthermore, the seams of the shell are provided with conductive foam for shielding, forming a Faraday cage.

[0016] Furthermore, the protection circuit includes an RJ45 interface surge suppression network: the center tap is grounded via a 47nF / 2kV capacitor, and a 75Ω / 1W resistor and a bidirectional TVS diode SM712 are connected in parallel between the center tap and ground to achieve IEC 61000-4-5 differential mode 1kV and common mode 1kV surge protection.

[0017] The present invention adopts the above solution and has the following beneficial effects: 1. Zero port redundancy: It adopts a combination of 6 electrical ports + 2 optical ports, which reduces the number of ports and the corresponding number of PHYs, transformers and power rails compared with traditional 24-port hybrid switches, significantly reducing the overall cost and power consumption.

[0018] 2. Signal integrity: π-type filtering + complete reference plane + center tap surge suppression, 10G return loss >18dB@5GHz, passed IEEE 802.3an / ch compliance test.

[0019] 3. Electromagnetic compatibility: The shell is made of conductive foam + TVS array, with a radiated disturbance Class A margin of >6dB and a surge voltage of 1kV.

[0020] 4. Excellent heat dissipation: The aluminum shell is integrated for heat dissipation, and the surface temperature rise of the shell is ≤20℃ under 80W full load. Attached Figure Description

[0021] This invention can be better understood by referring to the following description taken in conjunction with the accompanying drawings, in which the same or similar reference numerals are used throughout the drawings to denote the same or similar parts. These drawings, together with the following detailed description, are incorporated in and form part of this specification, and are used to further illustrate preferred embodiments of the invention and explain the principles and advantages of the invention. In the drawings: Figure 1 This is a schematic diagram of the principle of this utility model; Figure 2 A schematic diagram of the PHY chip and its peripheral circuitry is provided for exchanging the schematic diagram of the core circuitry. Figure 3 A schematic diagram of the optical port SerDes and its peripheral circuitry for the core switching circuit. Figure 4 Schematic diagram of a power tree circuit Figure 1 ; Figure 5 Schematic diagram of a power tree circuit Figure 2 ; Figure 6 Schematic diagram of a power tree circuit Figure 3 ; Figure 7 Schematic diagram of a power tree circuit Figure 4 ; Figure 8 Schematic diagram of a power tree circuit Figure 4 . Detailed Implementation

[0022] Embodiments of the present invention will now be described with reference to the accompanying drawings. Elements and features described in one drawing or embodiment of the present invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that, for clarity, representations and descriptions of components and processes unrelated to the present invention and known to those skilled in the art have been omitted from the drawings and description.

[0023] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0024] This utility model discloses a compact all-10 Gigabit Ethernet switch with mixed ports, including a housing. The front panel of the housing has six RJ45 electrical ports on the left side and two SFP+ optical ports on the right side. A circuit board is housed inside the housing. (See attached diagram.) Figure 1The circuit board includes a switching core circuit, three electrical port PHY (physical layer transceiver) chips and their peripheral circuits, two optical port SerDes and their peripheral circuits, a DIP switch rate lock circuit, a power tree circuit, a heat dissipation and grounding circuit, and a protection circuit. Each electrical port PHY chip is dual-port and is directly connected to the switching core circuit via a USXGMII differential pair. The six electrical ports and two optical ports achieve hybrid optoelectronic access through the switching core circuit, the electrical port PHY chips and their peripheral circuits, and the optical port SerDes and their peripheral circuits. The DIP switch rate lock circuit, the power tree circuit, the heat dissipation and grounding circuit, and the protection circuit are all electrically connected to the switching core circuit.

[0025] As a specific embodiment, the core switching circuit includes a network switching chip, a decoupling unit, a clock unit, and a reset unit; the decoupling unit, clock unit, and reset unit are all electrically connected to the network switching chip; the network switching chip is implemented using a Realtek RTL9300 (BGA-676) chip; in the decoupling unit, each power supply ball corresponds to at least one set of decoupling capacitors, each set consisting of a 0.1µF (0402 package) capacitor and a 4.7µF (0603 package) capacitor connected in parallel; the clock unit has a clock frequency of Y125MHz±10ppm, a load capacitance of 18pF, and a 1MΩ parallel feedback resistor; the reset unit uses a 10kΩ / 10µF RC network with a delay of 10ms, simultaneously sending data to all electrical port PHY chips. The core switching circuit is implemented using a Realtek RTL9300 switching chip. As a specific example, see Figure 2 The Ethernet PHY chip and its peripheral circuitry (taking Ports 1-2 as an example, the other 4 ports are symmetrical) include an Ethernet PHY transceiver, a USXGMII serial line, an MDI interface, and a center tap. The dual ports of the Ethernet PHY transceiver are connected to the switching core circuitry via the USXGMII serial line. The MDI interface and center tap are both connected to the Ethernet PHY transceiver. The Ethernet PHY transceiver is implemented using the RTL8261BE chip. The USXGMII serial line includes four pairs of 100Ω differential traces with AC coupling of 0.1µF and length matching ≤5mil. The MDI interface consists of four pairs of 100Ω differential traces via an HX5124NL transformer to an RJ45 port. The center tap is: TransformerCT → 47nF / 2kV → GND, connected in parallel with a 75Ω / 1W ohmmeter to form a common-mode discharge. Its power supply section achieves π-type filtering through 4.7µH+22µF×2+600Ω@100MHz ferrite beads.

[0026] See Figure 3The optical port SerDes and its peripheral circuitry include SerDes differential pairs, which are connected to the SFP+ cage via a 0.1µF AC coupling capacitor. The LOS, TX_DIS, and TX_FAULT signals of the SFP+ cage are connected to the GPIO of the network switching chip via a 33Ω series resistor to achieve hot-plug detection. In this embodiment, the SerDes differential pairs are led out from the built-in SerDes of the network switching chip RTL9300, with two 100Ω differential pairs, AC coupled at 0.1µF / 50V (0402), and connected to the SFP+ cage via a common-mode choke of 90Ω / 100MHz; LOS: cage pin8 → 33Ω → RTL9300-GPIO18, pulled down by 10kΩ; TX_DIS: GPIO21 → 33Ω → cage pin3, pulled up by 4.7kΩ to 3.3V by default; TX_FAULT: cage pin6 → 33Ω → GPIO20, pulled down by 10kΩ; EEPROM: AT24C64, SDA / SCL pulled up to 3.3V via 2.2kΩ for digital diagnostics of the optical module.

[0027] In this embodiment, the DIP switch rate lock circuit includes a 4-position rotary switch, outputting 2-bit binary + 1-bit latch; a pull-up resistor of 10kΩ to 3.3V, and the switch common terminal grounded; the output is connected to the EEPROM A0 / A1 address pins. After power-on, the RTL9300 reads the EEPROM 0x00-0x03 range value and directly configures the SerDes rate register to achieve 10G / 5G / 2.5G / 1G hardware lock.

[0028] In this embodiment, see Figures 4-8 The power tree circuit includes interface J1, fuse F1, inductor L1, and 5 synchronous buck DC-DC converters. Interface J1: 5.5-2.1mm socket, 12V / 7A input; Fuse F1: 3A / 30V self-resetting fuse; Inductor L1: 2mH common-mode choke / 6A; First synchronous buck DC-DC converter: MPQ8633A, 5V / 6A, switching frequency 600kHz, external 10µH / 22µF×2; Second synchronous buck DC-DC converter: TPS53355, 3.3V / 8A, external 4.7µH / 47µF×2; Third synchronous buck DC-DC converter: TP... S62130, 1.9V / 4A, external 4.7µH / 22µF×2; Fourth synchronous buck DC-DC: MP2143DJ, 1.0V / 6A, external 2.2µH / 22µF×2; Fifth synchronous buck DC-DC: MPQ8633B, 0.9V / 8A, external 3.3µH / 22µF×2; The output of each synchronous buck DC-DC consists of two 22µF surface mount capacitors, a 4.7µH power inductor, and a 600Ω@100MHz ferrite bead forming a π-type filter (one of the 22µF surface mount capacitors is located after the ferrite bead), with peak-to-peak noise <20mV.

[0029] In this embodiment, the heat dissipation and grounding circuit includes a thermal pad and an aluminum extruded heat sink on the bottom of the housing; one side of the thermal pad is attached to the exposed copper foil on the back of the PCB, and the other side is attached to the aluminum extruded heat sink. Specifically, the aluminum extruded heat sink has a bottom shell thickness of 0.8mm, fin thickness of 1.2mm, and is anodized black; the thermal pad has a strength of 1W / (m·K), a thickness of 0.5mm, and a coverage area of ​​30mm×30mm; the exposed copper foil on the back of the circuit board has layers 2, 4, and 5 as a complete ground plane, with a via array spacing of 0.3mm / 1mm and a thermal resistance ≤5℃ / W; shielding includes conductive foam at the housing seams with an impedance <0.1Ω and a radiated interference Class A margin >6dB.

[0030] In this embodiment, the protection circuit includes an RJ45 interface surge suppression network: the center tap is grounded via a 47nF / 2kV capacitor, connected in parallel with a 75Ω / 1W capacitor, and then connected in parallel with a TVS diode SM712, which meets the IEC 61000-4-5 requirement for differential / common mode 1kV surge; SFP+: TX / RX differential pair connected in parallel with a TVS diode RCLamp0502B, clamped at 5V / 2A; power input: 12V in parallel with 33V / 1500WTVS, allowing reverse 1kV surge passage.

[0031] This embodiment adopts the above-described solution, with an electrical port of RJ45 10GBase-T and an optical port of SFP+ 10 Gigabit optical port. Internally, it uses an RTL9300 SoC, three RTL8261BE PHYs, and two SerDes channels to achieve hybrid optoelectronic access. A four-position DIP switch on the front panel, linked to the EEPROM, allows for hardware locking of the optical port rate. π-type filtering, a complete reference plane, and center tap surge suppression ensure signal integrity. An integrated aluminum casing provides heat dissipation, with a full-load temperature rise of ≤20℃. This invention features zero port redundancy, low cost, and flexible deployment, making it widely applicable to small and medium-sized enterprises and data center edge scenarios.

[0032] Although the present invention has been disclosed above through the description of specific embodiments, it should be understood that all the embodiments and examples described above are exemplary and not restrictive. Those skilled in the art can design various modifications, improvements, or equivalents to the present invention within the spirit and scope of the appended claims. These modifications, improvements, or equivalents should also be considered to be included within the protection scope of the present invention.

Claims

1. A compact all-10 Gigabit Ethernet switch with hybrid ports, characterized in that: The device includes a housing. The front panel of the housing has six RJ45 electrical ports on the left and two SFP+ optical ports on the right. Inside the housing is a circuit board comprising a core switching circuit, three electrical port PHY chips and their peripheral circuits, two optical port SerDes and their peripheral circuits, a DIP switch rate lock circuit, a power tree circuit, a heat dissipation and grounding circuit, and a protection circuit. Each electrical port PHY chip is dual-port and directly connected to the core switching circuit via a USXGMII differential pair. The six electrical ports and two optical ports achieve hybrid optoelectronic access via the core switching circuit, the electrical port PHY chips and their peripheral circuits, and the optical port SerDes and their peripheral circuits. The DIP switch rate lock circuit, the power tree circuit, the heat dissipation and grounding circuit, and the protection circuit are all electrically connected to the core switching circuit.

2. The compact all-10 Gigabit Ethernet switch with hybrid ports according to claim 1, characterized in that: The core switching circuit includes a network switching chip, a decoupling unit, a clock unit, and a reset unit; the decoupling unit, clock unit, and reset unit are all electrically connected to the network switching chip; the network switching chip is implemented using a Realtek RTL9300 chip.

3. The compact all-10 Gigabit Ethernet switch with hybrid ports according to claim 1, characterized in that: The Ethernet PHY chip and its peripheral circuitry include an Ethernet PHY transceiver, a USXGMII serial line, an MDI interface, and a center tap. The dual ports of the Ethernet PHY transceiver are connected to the USXGMII interface of the switching core circuit, and the MDI interface and the center tap are both connected to the Ethernet PHY transceiver. The Ethernet PHY transceiver is implemented using a chip of model RTL8261BE.

4. The compact all-10 Gigabit Ethernet switch with hybrid ports according to claim 2, characterized in that: The optical port SerDes and its peripheral circuitry include SerDes differential pairs, which are connected to the SFP+ cage via a 0.1µF AC coupling capacitor. The LOS, TX_DIS, and TX_FAULT signals of the SFP+ cage are connected to the GPIO of the network switching chip via a 33Ω series resistor to achieve hot-plug detection. The SerDes differential pairs are brought out from the SerDes built into the network switching chip.

5. The compact all-10 Gigabit Ethernet switch with hybrid ports according to claim 1, characterized in that: The DIP rate locking circuit includes a 4-position rotary switch, and the output of the rotary switch is connected to the GPIO of the network switching chip.

6. The compact all-10 Gigabit Ethernet switch with hybrid ports according to claim 1, characterized in that: The power tree circuit includes multiple synchronous buck DC-DC converters, and the output of each synchronous buck DC-DC converter consists of a π-type filter composed of a 22µF chip capacitor, a power inductor, and a ferrite bead.

7. The compact all-10 Gigabit Ethernet switch with hybrid ports according to claim 1, characterized in that: The heat dissipation and grounding circuit includes a thermal pad and an aluminum extruded heat sink on the bottom of the housing; one side of the thermal pad is attached to the exposed copper skin on the back of the circuit board, and the other side is attached to the aluminum extruded heat sink.

8. The compact all-10 Gigabit Ethernet switch with hybrid ports according to claim 1, characterized in that: The seams of the shell are provided with conductive foam for shielding, forming a Faraday cage.

9. The compact all-10 Gigabit Ethernet switch with hybrid ports according to claim 1, characterized in that: The protection circuit includes an RJ45 interface surge suppression network: the RJ45 center tap is grounded via a 47nF / 2kV capacitor, and a 75Ω / 1W resistor and a bidirectional TVS diode SM712 are connected in parallel between the center tap and ground to achieve surge protection.

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