Stacked capacitor and semiconductor device

Abstract

The application provides a stacked capacitor and a semiconductor device. The stacked capacitor includes a base dielectric layer and a capacitor body located on one side of the base dielectric layer. The capacitor body includes a plurality of conductive layers and a spacer dielectric layer located between the conductive layers. In a first direction from the base dielectric layer to the capacitor body, the plurality of conductive layers includes first sub-conductive layers and second sub-conductive layers alternately arranged in sequence. The stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a second direction. Each first sub-conductive layer is located in the first connection region and the conductive layer stack region, and each second sub-conductive layer is located in the second connection region and the conductive layer stack region. The first sub-conductive layer includes a first side surface facing the second connection region, and the second sub-conductive layer includes a second side surface facing the first connection region. The capacitor body further includes an isolation dielectric layer covering the first side surface of at least one first sub-conductive layer and / or the second side surface of at least one second sub-conductive layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a stacked capacitor and a semiconductor device. Background Technology

[0002] Capacitors are common and important passive electronic components in integrated circuits. Common capacitors include metal-oxide-semiconductor (MOS) capacitors, PN junction capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and metal-insulator-metal (MIM) capacitors. MIM capacitors are typically formed on a metal interconnect structure in the back-end of line (BEOL) process. This increases the distance between the MIM capacitor and the silicon substrate, thereby reducing the parasitic capacitance between the MIM capacitor and the substrate. Furthermore, the performance of MIM capacitors is less affected by frequency and temperature. In addition, MIM capacitors are formed during the metal interconnect process, making the MIM formation process compatible with existing integrated circuit technologies. Therefore, MIM capacitors have gradually become the mainstream type of passive capacitor. As Moore's Law continues to evolve, the requirements for capacitor density in integrated circuits are becoming increasingly stringent. This is particularly evident in high-performance chips such as CPUs, GPUs, and FPGAs; mobile chips including 5G modems, system-on-a-chip (SoC), power management chips (PMIC), and 2.5D / 3D chiplets, where there is a significant demand for high-density capacitors. Currently, a major mainstream structure for achieving high-density capacitors is stacked capacitors.

[0003] Local electric field concentration exists at the edge of the conductive layer of stacked capacitors, which can easily cause breakdown and leakage of the dielectric layer, thus having an adverse effect on the stacked capacitors. Utility Model Content

[0004] This application provides a stacked capacitor and a semiconductor device.

[0005] A first aspect of this application provides a stacked capacitor, the stacked capacitor comprising: Base dielectric layer; A capacitor body located on one side of the base dielectric layer, the capacitor body comprising multiple stacked conductive layers and spacer dielectric layers located between each adjacent pair of conductive layers; in each conductive layer, in a first direction from the base dielectric layer to the capacitor body, the multiple conductive layers include sequentially alternating first sub-conductive layers and second sub-conductive layers; wherein, the stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a second direction; each first sub-conductive layer is located in the first connection region and the conductive layer stack region, and each second sub-conductive layer is located in the second connection region and the conductive layer stack region; Each of the first sub-conductive layers includes a first side facing the second connection region, and each of the second sub-conductive layers includes a second side facing the first connection region; the capacitor body further includes an isolation dielectric layer, and the first side of at least one of the first sub-conductive layers and / or the second side of at least one of the second sub-conductive layers is covered by the isolation dielectric layer.

[0006] In some embodiments, at least one surface of the first sub-conductive layer away from the base dielectric layer, adjacent to the first side, is covered by the isolation dielectric layer; and / or, at least one surface of the second sub-conductive layer away from the base dielectric layer, adjacent to the second side, is covered by the isolation dielectric layer.

[0007] In some embodiments, the surface of the isolation dielectric layer covering the surface of the first sub-conductive layer away from the base dielectric layer is substantially flush with the surface of the first sub-conductive layer away from the base dielectric layer; the surface of the isolation dielectric layer covering the surface of the second sub-conductive layer away from the base dielectric layer is substantially flush with the surface of the second sub-conductive layer away from the base dielectric layer.

[0008] In some embodiments, the material of the isolation dielectric layer covering the conductive layer is a metal oxide, the material of the conductive layer is a metal, and the isolation dielectric layer and the conductive layer contain the same metal element.

[0009] In some embodiments, the thickness of the isolation dielectric layer is 0.7 to 1.5 times the thickness of the spacer dielectric layer.

[0010] In some embodiments, each of the conductive layers is a metal layer made of the same material.

[0011] In some embodiments, the thickness of the conductive layer is 10 nm to 100 nm; in the conductive layer stack region, the thickness of the spacer dielectric layer located between two adjacent conductive layers is 5 nm to 50 nm.

[0012] In some embodiments, the stacked capacitor further includes a top dielectric layer, a first connection hole, and a second connection hole; The top dielectric layer is located on the side of the capacitor body opposite to the base dielectric layer; the first connection hole is located in the first connection area, and along the first direction, the first connection hole penetrates the top dielectric layer, each of the first sub-conductive layers and each of the spacer dielectric layers, and exposes the base dielectric layer; the second connection hole is located in the second connection area, and along the first direction, the second connection hole penetrates the top dielectric layer, each of the second sub-conductive layers and each of the spacer dielectric layers, and exposes the base dielectric layer; The first connecting hole is provided with a first conductive structure, and the second connecting hole is provided with a second sub-conductive structure; the first conductive structure is electrically connected to the sidewall of the first sub-conductive layer; the second sub-conductive structure is electrically connected to the sidewall of the second sub-conductive layer.

[0013] A second aspect of this application provides a semiconductor device comprising the stacked capacitors described above.

[0014] In some embodiments, the semiconductor device further includes a chip, and the stacked capacitors are disposed outside the surface of the chip or inside the chip.

[0015] The stacked capacitors provided in this application increase the total thickness of the dielectric layer in the conductive layer edge region by setting an isolation dielectric layer. This effectively avoids dielectric layer breakdown and leakage caused by electric field concentration, thus improving the operational reliability and durability of the stacked capacitors. Furthermore, the isolation dielectric layer does not increase the overall thickness of the spacer dielectric layer, preventing the capacitance density of the stacked capacitors from being affected.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0018] Figure 1 This is a schematic diagram of the structure of a stacked capacitor provided in an embodiment of this application; Figure 2 This is a top view of a stacked capacitor provided in an embodiment of this application; Figures 3 to 12 This is a schematic diagram showing the structure of different processes corresponding to the fabrication of stacked capacitors according to an embodiment of this application. Detailed Implementation

[0019] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0020] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0021] The stacked capacitors and semiconductor devices of the present application embodiments are described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can complement or combine with each other.

[0022] This application provides a stacked capacitor, such as Figure 1 As shown, the stacked capacitor includes a base dielectric layer 10 and a capacitor body 20 located on one side of the base dielectric layer 10.

[0023] The capacitor body 20 includes multiple stacked conductive layers 21 and spacer dielectric layers 22 located between each adjacent pair of conductive layers 21. In each conductive layer 21, along a first direction X from the base dielectric layer 10 towards the capacitor body 20, the multiple conductive layers 21 include sequentially alternating first sub-conductive layers 21A and second sub-conductive layers 21B. The stacked capacitor has a first connection region Q1, a conductive layer stack region Q3, and a second connection region Q2 arranged along a second direction Y. Each first sub-conductive layer 21A is located in the first connection region Q1 and the conductive layer stack region Q3, and each second sub-conductive layer 21B is located in the second connection region Q2 and the conductive layer stack region Q3.

[0024] Each first sub-conductive layer 21A includes a first side surface 2121 facing the second connection region Q2, and each second sub-conductive layer 21B includes a second side surface 2122 facing the first connection region Q1. The capacitor body 20 also includes an isolation dielectric layer 23, wherein the first side surface 2121 of at least one first sub-conductive layer 21A is covered by the isolation dielectric layer 23, and the second side surface 2122 of at least one second sub-conductive layer 21B is covered by the isolation dielectric layer 23.

[0025] During the manufacturing or operation of stacked capacitors, the sharp edge effect of the conductive layer can lead to localized electric field concentration. This concentrated electric field may exceed the breakdown field strength of the dielectric material between the conductive layers, causing problems such as insulation failure, increased leakage current, or even capacitor short circuits. The stacked capacitor provided in this application increases the total thickness of the dielectric layer in the conductive layer edge region by setting an isolation dielectric layer 23, effectively avoiding dielectric layer breakdown and leakage caused by electric field concentration, thus improving the operational reliability and durability of the stacked capacitor. Furthermore, the isolation dielectric layer 23 does not increase the overall thickness of the spacer dielectric layer 22, preventing the capacitance density of the stacked capacitor from being affected.

[0026] In one embodiment, such as Figure 1 As shown, the material of the base dielectric layer 10 can be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride, etc., to provide a platform for the subsequent manufacturing of stacked capacitors (and MIM stacked capacitors).

[0027] It is understood that the stacked capacitor can be a capacitor structure formed inside the chip or on the chip surface. In the implementation where the stacked capacitor is formed inside the chip or on the chip surface, the base dielectric layer 10 can also be used to isolate the previous metal interconnect structure in the back-end of line (BEOL) process, that is, to electrically isolate the stacked capacitor from the chip.

[0028] In one embodiment, such as Figure 1 As shown, each conductive layer 21 includes a first straight portion 211 and a second straight portion 212 connected together. The first straight portion 211 of the first sub-conductive layer 21A is located within the first connection region Q1, and the second straight portion 212 of the first sub-conductive layer 21A is located within the conductive layer stack region Q3. The first straight portion 211 of the second sub-conductive layer 21B is located within the second connection region Q2, and the second horizontal portion 212 of the second sub-conductive layer 21B is located within the conductive layer stack region Q3.

[0029] The first side 2121 is the side of the second straight portion 212 of the first sub-conductive layer 21A that is away from the first straight portion 211; the second side 2122 is the side of the second straight portion 212 of the second sub-conductive layer 21B that is away from the first straight portion 211.

[0030] exist Figure 1In the illustrated embodiment, the conductive layer 21 includes conductive layers 21a to 21d, and a spacer dielectric layer 22 is provided between adjacent conductive layers 21. The first side surface 2121 of the second straight portion 212 of conductive layers 21a and 21c is covered by an isolation dielectric layer 23, and the second side surface 2122 of the second straight portion 212 of conductive layers 21b and 21d is covered by an isolation dielectric layer 23.

[0031] In the above embodiments, the conductive layer 21 is 4 layers. In other embodiments, the conductive layer can also be multiple layers, such as 3 layers, 4 layers, 5 layers, 7 layers, 8 layers, etc.

[0032] In one embodiment, such as Figure 1 As shown, the conductive layer 21 closest to the base dielectric layer 10 includes only a first flat portion 211 and a second flat portion 212 that are equidistant from the base dielectric layer 10. The remaining conductive layers 21 include a first flat portion 211, a second flat portion 212, and a connecting portion 213 that connects the first flat portion 211 and the second flat portion 212. The distance between the first flat portion 211 and the base dielectric layer 10 is less than the distance between the second flat portion 212 and the base dielectric layer 10.

[0033] In one embodiment, such as Figure 1 As shown, at least one surface of the first sub-conductive layer 21A away from the base dielectric layer 10, adjacent to the first side surface 2121, is covered by an isolation dielectric layer 23. The corner area adjacent to the first side surface 2121 on the upper surface of the first sub-conductive layer 21A is where the electric field concentration effect is most significant and breakdown is most likely to occur. Through the above arrangement, the isolation dielectric layer 23 can more effectively prevent breakdown or leakage at the corner area of ​​the first sub-conductive layer 21A, which is beneficial to further improve the insulation reliability and long-term operating stability of the stacked capacitor.

[0034] In one embodiment, such as Figure 1 As shown, at least one surface of the second sub-conductive layer 21B away from the base dielectric layer 10, adjacent to the second side surface 2122, is covered by an isolation dielectric layer 23. Through this arrangement, the isolation dielectric layer 23 can more effectively prevent breakdown or leakage at the corners of the second sub-conductive layer 21B, which is beneficial for further improving the insulation reliability and long-term operational stability of the stacked capacitor.

[0035] In one embodiment, such as Figure 1As shown, the surface of the isolation dielectric layer 23 covering the surface of the first sub-conductive layer 21A away from the base dielectric layer 10 is substantially flush with the surface of the first sub-conductive layer 21A away from the base dielectric layer 10. Similarly, the surface of the isolation dielectric layer 23 covering the surface of the second sub-conductive layer 21B away from the base dielectric layer 10 is substantially flush with the surface of the second sub-conductive layer 21B away from the base dielectric layer 10. This configuration ensures the overall flatness of the upper surface of the conductive layers of the stacked capacitor, avoiding processing defects caused by surface undulations. Furthermore, the flush surface structure facilitates a uniform distribution of the electric field inside the capacitor, thereby improving the local breakdown voltage while ensuring the overall stability and reliability of the stacked capacitor performance.

[0036] In one embodiment, the material of the insulating dielectric layer 23 covering the conductive layer 21 is a metal oxide, and the material of the conductive layer 21 is a metal. The insulating dielectric layer 23 and the conductive layer 21 contain the same metal element. From a manufacturing perspective, the above material selection allows the insulating dielectric layer 23 to be directly formed by oxidizing the surface of the conductive layer 21, simplifying the process and reducing manufacturing costs.

[0037] In one embodiment, the conductive layer 21 is made of a metallic material, such as aluminum. Of course, in other embodiments, the conductive layer material can also be, but is not limited to, titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, gypsum, molybdenum, hafnium, and other etchable metals. In some embodiments, the material of each conductive layer 101 can be the same.

[0038] In one embodiment, the thickness of the conductive layer 21 is 10 nm to 100 nm. For example, the thickness of the conductive layer 21 can be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm. In some embodiments, the thickness of each conductive layer 21 can be the same.

[0039] In one embodiment, the material of the spacer dielectric layer 22 may be any one or a mixture of materials selected from, but not limited to, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN. In some embodiments, the thickness of each spacer dielectric layer 22 may be the same.

[0040] In one embodiment, in the conductive stack region Q3, the thickness of the spacer dielectric layer 22 located between two adjacent conductive layers 21 is 5 nm to 50 nm. The thickness of the spacer dielectric layer 22 can be, for example, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm. In some embodiments, the thickness of each spacer dielectric layer 22 can be the same.

[0041] It is understood that in some other embodiments, the materials of the conductive layers 21 may also be different. The thickness of the conductive layers 21 may also be different. The materials of the spacer dielectric layers 22 may also be different. The thickness of the spacer dielectric layers 22 may also be different.

[0042] In one embodiment, the thickness of the isolation dielectric layer 23 is 0.7 to 1.5 times the thickness of the spacer dielectric layer 22. When the isolation dielectric layer 23 is too thin, its effect on suppressing the electric field at the edge of the conductive layer 21 is insufficient, making it difficult to effectively prevent voltage breakdown; when the isolation dielectric layer 23 is too thick, it will occupy too much space, which is not conducive to improving the capacitance density of the stacked capacitor.

[0043] In one embodiment, such as Figure 1 As shown, the stacked capacitor also includes a top dielectric layer 30 located on the side of the capacitor body 20 facing away from the base dielectric layer 10. The material of the top dielectric layer 30 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0044] The top dielectric layer 30 is relatively thick, at least greater than the thickness of a spacer dielectric layer. The thickness of the top dielectric layer 30 can be greater than the thickness of a conductive layer.

[0045] For stacked capacitors that are away from the base dielectric layer 10 (which can be understood as the top of the stacked capacitors) and require other metal interconnect structures to be set later, the top dielectric layer 30 can be used to isolate the metal interconnect structures in the back-end of line (BEOL) process on the top of the stacked capacitors.

[0046] In one embodiment, such as Figure 1As shown, the stacked capacitor also includes a first connection hole 411 and a second connection hole 421. The first connection hole 411 is located in the first connection region Q1, and along the first direction X, the first connection hole 411 penetrates the top dielectric layer 30, each first sub-conductive layer 21A, and each spacer dielectric layer 22, and exposes the base dielectric layer 10. The second connection hole 421 is located in the second connection region Q2, and along the first direction X, the second connection hole 421 penetrates the top dielectric layer 30, each second sub-conductive layer 21B, and each spacer dielectric layer 22, and exposes the base dielectric layer 10.

[0047] A first conductive structure 412 is provided in the first connecting hole 411, and a second conductive structure 422 is provided in the second connecting hole 421. The first conductive structure 412 is electrically connected to the sidewall of the first sub-conductive layer 21A, and the second conductive structure 422 is electrically connected to the sidewall of the second sub-conductive layer 21B.

[0048] In one embodiment, such as Figure 1 As shown, the first conductive structure 412 includes a first conductive body 4121 and a first seed layer 4122. The first conductive body 4121 fills the first connection hole 411. The first seed layer 4122 is located between the first conductive body 4121 and the inner wall of the first connection hole 411.

[0049] The second conductive structure 422 includes a second conductive body 4221 and a second seed layer 4222. The second conductive body 4221 fills the second connection hole 421, and the second seed layer 4222 is located between the second conductive body 4221 and the inner wall of the second connection hole 421.

[0050] In one embodiment, the materials of the first conductive body 4121 and the second conductive body 4221 may be metals such as copper (Cu) and tungsten (W). The materials of the first seed layer 4122 and the second seed layer 4222 may be metals such as TiN and TaN.

[0051] In one embodiment, such as Figure 2 As shown, there are multiple first conductive structures 412 and multiple second conductive structures 422, and the number of first conductive structures 412 and second conductive structures 422 is the same. This arrangement can increase the contact area between the first conductive structures 412 and second conductive structures 422 and the conductive layer, thereby reducing the contact resistance.

[0052] This application also provides a semiconductor device. The semiconductor device includes stacked capacitors as described above.

[0053] In some embodiments, the semiconductor device further includes a chip, and the stacked capacitors are disposed outside the chip surface or inside the chip.

[0054] Chips include, but are not limited to, high-performance chips such as CPU chips, GPU chips, FPGA chips, 5G modem chips, system-on-a-chip (SoC), power management chips (PMIC), and 2.5D / 3D chiplets.

[0055] This application also provides a method for preparing stacked capacitors, such as... Figures 3 to 12 As shown, the preparation method includes: Step S100: Form the base dielectric layer; Step S200: Form a capacitor body located on one side of the base dielectric layer. The capacitor body includes multiple stacked conductive layers and a spacer dielectric layer located between each adjacent pair of conductive layers. In each conductive layer, from the surface of the base dielectric layer toward the conductive layer furthest from the base dielectric layer in a first direction, the multiple conductive layers include sequentially alternating first sub-conductive layers and second sub-conductive layers. The stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a second direction. Each first sub-conductive layer is located in the first connection region and the conductive layer stack region, and each second sub-conductive layer is located in the second connection region and the conductive layer stack region. Each first sub-conductive layer includes a first side facing the second connection region, and each second sub-conductive layer includes a second side facing the first connection region. The capacitor body also includes an isolation dielectric layer, wherein the first side of at least one first sub-conductive layer is covered by the isolation dielectric layer, or the second side of at least one second sub-conductive layer is covered by the isolation dielectric layer.

[0056] In step S100, the base dielectric layer 10 can be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods.

[0057] In step S200, the steps of forming the first sub-conductive layer and the isolation dielectric layer covering its sides include: like Figure 3 As shown, a first sub-conductive layer thin film 21a' is formed, and the orthogonal projection of the first sub-conductive layer thin film 21a' onto the base dielectric layer 10 covers the base dielectric layer 10.

[0058] like Figure 4 As shown, the first sub-conductive layer film 21a' is patterned, and the portion of the first sub-conductive film 21a' located in the second connection region Q2 is removed to obtain the first sub-conductive film layer 21a". Figure 5 and Figure 6 As shown, at least the side of the first sub-conductive film layer 21a” facing the second connection region Q2 is oxidized to obtain the first sub-conductive layer 21a and the isolation dielectric layer 23. The isolation dielectric layer 23 at least covers the first side 2121 of the first sub-conductive layer 21a facing the second connection region Q2.

[0059] Specifically, at least the side of the first sub-conductive film layer 21a” facing the second connection region Q2 is oxidized to obtain the first sub-conductive layer 21a and the isolation dielectric layer 23. The isolation dielectric layer 23 at least covers the first side 2121 of the first sub-conductive layer 21a facing the second connection region Q2, including: like Figure 4 and Figure 5 As shown, a first photoresist layer 51 is formed on the surface of the first sub-conductive film layer 21a” away from the base dielectric layer 10.

[0060] Oxygen is used to etch the first photoresist layer 51 to form a first opening. The first opening exposes at least the side of the first sub-conductive film layer 21a” facing the second connection region Q2. Simultaneously, oxygen is used to oxidize the side of the first sub-conductive film layer 21a” facing the second connection region Q2 to form an isolation dielectric layer 23. Figure 5 In the embodiment shown, the first opening also exposes the area of ​​the first sub-conductive film layer 21a” that is away from the surface of the base dielectric layer 10 and adjacent to the first side surface 2121, where oxygen simultaneously oxidizes the area to form an isolation dielectric layer 23.

[0061] After that, as Figure 6 As shown, a first spacer dielectric layer 22a is formed on the conductive layer 21a.

[0062] In step S200, the steps of forming the second sub-conductive layer and the isolation dielectric layer covering its sides include: A second sub-conductive layer thin film is formed, and the orthogonal projection of the second sub-conductive layer thin film onto the base dielectric layer 10 covers the base dielectric layer 10.

[0063] like Figure 7 As shown, the second sub-conductive layer film is patterned, and the portion of the second sub-conductive film located in the first connection region Q1 is removed to obtain the second sub-conductive film layer 22b. Figure 8 As shown, at least the side of the second sub-conductive film layer 22b” facing the first connection region Q1 is oxidized to obtain the second sub-conductive layer 22b and the isolation dielectric layer 23. The isolation dielectric layer 23 at least covers the second side 2122 of the second sub-conductive layer 22b facing the first connection region Q1.

[0064] Specifically, at least the side of the second sub-conductive film layer 22b” facing the first connection region Q1 is oxidized to obtain the second sub-conductive layer 22b and the isolation dielectric layer 23. The isolation dielectric layer 23 at least covers the second side 2122 of the second sub-conductive layer 22b facing the first connection region Q1, including: like Figure 7 and Figure 8 As shown, a second photoresist layer 52 is formed on the surface of the second sub-conductive film layer 22b” away from the base dielectric layer 10.

[0065] Oxygen is used to etch the second photoresist layer 52 to form a second opening. The second opening exposes at least the side of the second sub-conductive film layer 22b” facing the first connection region Q1. Simultaneously, oxygen is used to oxidize the side of the second sub-conductive film layer 22b” facing the first connection region Q1 to form an isolation dielectric layer 23. Figure 8 In the embodiment shown, the second opening also exposes the area of ​​the second sub-conductive film layer 21b” that is away from the surface of the base dielectric layer 10 and adjacent to the second side surface 2122, where oxygen simultaneously oxidizes the area to form an isolation dielectric layer 23.

[0066] Specifically, when forming the insulating dielectric layer 23 using oxygen, a higher reaction temperature and oxygen concentration can be employed, such as a reaction temperature of 150°C or 200°C and an O2 flow rate of 100 sccm. This high temperature accelerates the oxidation reaction rate. Simultaneously, argon gas is introduced, for example, at a flow rate of 280 sccm, using Ar as a carrier gas or to maintain the gas atmosphere within the reaction chamber, aiding in uniform gas distribution. Furthermore, ozone can be added to further enhance the oxidation capacity, while controlling the plasma power or microwave power to a lower level, such as a microwave power of 40W, to provide adequate energy to excite the oxidation reaction, but avoiding excessive ion bombardment that could damage the metal surface due to high power.

[0067] After that, as Figure 9 As shown, other conductive layers 21, spacer dielectric layers 22, and isolation dielectric layers 23 are formed sequentially until the capacitor body 20 is formed. The formation methods of other conductive layers 21, spacer dielectric layers 22, and isolation dielectric layers 23 can be referred to the relevant descriptions above.

[0068] In one embodiment, the preparation method further includes step S300, in which, as... Figure 10 As shown, a top dielectric layer 30 is formed. The top dielectric layer 30 is located on the side of the capacitor body 20 away from the base dielectric layer 10.

[0069] In one embodiment, the preparation method further includes step S400, in which, as... Figure 11 As shown, a first connection hole 411 is formed in the first connection area Q1. Along the first direction X, the first connection hole 411 penetrates the top dielectric layer 30, each first sub-conductive layer 21A and each spacer dielectric layer 22, and exposes the base dielectric layer 10. The second connection hole 421 is located in the second connection area Q2. Along the first direction X, the second connection hole 421 penetrates the top dielectric layer 30, each second sub-conductive layer 21B and each spacer dielectric layer 22, and exposes the base dielectric layer 10.

[0070] In one embodiment, the preparation method further includes step S500, in which, as... Figure 12As shown, a first conductive structure 412 is formed in the first connecting hole 411, and a second conductive structure 422 is formed in the second connecting hole 421. The first conductive structure 412 is electrically connected to the sidewall of the first sub-conductive layer 21A, and the second conductive structure 422 is electrically connected to the sidewall of the second sub-conductive layer 21B.

[0071] In one embodiment, the first conductive structure 412 includes a first conductive body 4121 and a first seed layer 4122, with the first conductive body 4121 filling the first connection hole 411. The first seed layer 4122 is located between the first conductive body 4121 and the inner wall of the first connection hole 411. The second conductive structure 422 includes a second conductive body 4221 and a second seed layer 4222. The second conductive body 4221 fills the second connection hole 421, and the second seed layer 4222 is located between the second conductive body 4221 and the inner wall of the second connection hole 421. The first seed layer 4122 and the second seed layer 4222 can be formed by atomic layer deposition (ALD) to achieve good coverage.

[0072] In one embodiment, the first conductive body 4121 and the second conductive body 4221 may be electroplated, and the conductive body material is electroplated on the first seed layer 4122 and the second seed layer 4222 respectively, and then chemical mechanical polishing (CMP) is performed to form the first conductive structure 412 and the second conductive structure 422 flush with the top dielectric layer 30.

[0073] In other embodiments, the first conductive structure 412 and the second conductive structure 422 may also be formed by directly filling a conductive body.

[0074] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A stacked capacitor, characterized in that, The stacked capacitors include: Base dielectric layer; A capacitor body located on one side of the base dielectric layer, the capacitor body comprising multiple stacked conductive layers and spacer dielectric layers located between each adjacent pair of conductive layers; in each conductive layer, in a first direction from the base dielectric layer to the capacitor body, the multiple conductive layers include sequentially alternating first sub-conductive layers and second sub-conductive layers; wherein, the stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a second direction; each first sub-conductive layer is located in the first connection region and the conductive layer stack region, and each second sub-conductive layer is located in the second connection region and the conductive layer stack region; Each of the first sub-conductive layers includes a first side facing the second connection region, and each of the second sub-conductive layers includes a second side facing the first connection region; the capacitor body further includes an isolation dielectric layer, and the first side of at least one of the first sub-conductive layers and / or the second side of at least one of the second sub-conductive layers is covered by the isolation dielectric layer.

2. The stacked capacitor according to claim 1, characterized in that, At least one of the first sub-conductive layers has a region on its surface away from the base dielectric layer adjacent to the first side surface covered by the isolation dielectric layer; and / or, at least one of the second sub-conductive layers has a region on its surface away from the base dielectric layer adjacent to the second side surface covered by the isolation dielectric layer.

3. The stacked capacitor according to claim 2, characterized in that, The surface of the isolation dielectric layer covering the surface of the first sub-conductive layer away from the base dielectric layer is substantially flush with the surface of the first sub-conductive layer away from the base dielectric layer; the surface of the isolation dielectric layer covering the surface of the second sub-conductive layer away from the base dielectric layer is substantially flush with the surface of the second sub-conductive layer away from the base dielectric layer.

4. The stacked capacitor according to claim 3, characterized in that, The material of the insulating dielectric layer covering the conductive layer is a metal oxide, the material of the conductive layer is a metal, and the insulating dielectric layer and the conductive layer contain the same metal element.

5. The stacked capacitor according to claim 1, characterized in that, The thickness of the isolation dielectric layer is 0.7 to 1.5 times the thickness of the spacer dielectric layer.

6. The stacked capacitor according to claim 1, characterized in that, Each of the conductive layers is a metal layer made of the same material.

7. The stacked capacitor according to claim 1, characterized in that, The thickness of the conductive layer is 10nm~100nm; in the conductive layer stack region, the thickness of the spacer dielectric layer located between two adjacent conductive layers is 5nm~50nm.

8. The stacked capacitor according to claim 1, characterized in that, The stacked capacitor also includes a top dielectric layer, a first connection hole, and a second connection hole; The top dielectric layer is located on the side of the capacitor body opposite to the base dielectric layer; the first connection hole is located in the first connection area, and along the first direction, the first connection hole penetrates the top dielectric layer, each of the first sub-conductive layers and each of the spacer dielectric layers, and exposes the base dielectric layer; the second connection hole is located in the second connection area, and along the first direction, the second connection hole penetrates the top dielectric layer, each of the second sub-conductive layers and each of the spacer dielectric layers, and exposes the base dielectric layer; The first connecting hole is provided with a first conductive structure, and the second connecting hole is provided with a second sub-conductive structure; the first conductive structure is electrically connected to the sidewall of the first sub-conductive layer; the second sub-conductive structure is electrically connected to the sidewall of the second sub-conductive layer.

9. A semiconductor device, characterized in that, The semiconductor device includes a stacked capacitor as described in any one of claims 1 to 8.

10. The semiconductor device according to claim 9, characterized in that, The semiconductor device further includes a chip, and the stacked capacitor is disposed outside the surface of the chip or inside the chip.

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