Stacked capacitor and semiconductor device

Abstract

The application provides a stacked capacitor and a semiconductor device. The stacked capacitor includes a base dielectric layer and a capacitor body located on one side of the base dielectric layer, the capacitor body including conductive layers and interval dielectric layers. In a first direction, the plurality of conductive layers include first sub-conductive layers and second sub-conductive layers alternately arranged in sequence. The stacked capacitor has a first connecting region, a conductive layer stacking region and a second connecting region arranged along a second direction. A first flat portion of the first sub-conductive layer is located in the first connecting region, and a second flat portion of the first sub-conductive layer is located in the conductive layer stacking region. A first flat portion of the second sub-conductive layer is located in the second connecting region, and a second flat portion of the second sub-conductive layer is located in the conductive layer stacking region. The second flat portion of each conductive layer includes a transition section at an end away from the first flat portion, and the distance between the transition section and the surface of the base dielectric layer gradually decreases in the direction from the first flat portion to the second flat portion.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a stacked capacitor and a semiconductor device. Background Technology

[0002] Capacitors are common and important passive electronic components in integrated circuits. Common capacitors include metal-oxide-semiconductor (MOS) capacitors, PN junction capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and metal-insulator-metal (MIM) capacitors. MIM capacitors are typically formed on a metal interconnect structure in the back-end of line (BEOL) process. This increases the distance between the MIM capacitor and the silicon substrate, thereby reducing the parasitic capacitance between the MIM capacitor and the substrate. Furthermore, the performance of MIM capacitors is less affected by frequency and temperature. In addition, MIM capacitors are formed during the metal interconnect process, making the MIM formation process compatible with existing integrated circuit technologies. Therefore, MIM capacitors have gradually become the mainstream type of passive capacitor. As Moore's Law continues to evolve, the requirements for capacitor density in integrated circuits are becoming increasingly stringent. This is particularly evident in high-performance chips such as CPUs, GPUs, and FPGAs; mobile chips including 5G modems, system-on-a-chip (SoC), power management chips (PMIC), and 2.5D / 3D chiplets, where there is a significant demand for high-density capacitors. Currently, a major mainstream structure for achieving high-density capacitors is stacked capacitors.

[0003] As the number of stacked capacitors increases, the continuity and reliability of the film layers are easily affected. How to improve the stability of step coverage and cross-layer connectivity of each film layer has become a core concern. Utility Model Content

[0004] This application provides a stacked capacitor and a semiconductor device.

[0005] A first aspect of this application provides a stacked capacitor, the stacked capacitor comprising: Base dielectric layer; A capacitor body located on one side of the base dielectric layer, the capacitor body comprising multiple stacked conductive layers and spacer dielectric layers located between each adjacent pair of conductive layers; in each conductive layer, in a first direction from the base dielectric layer to the capacitor body, the multiple conductive layers include sequentially alternating first sub-conductive layers and second sub-conductive layers; wherein, the stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a second direction; each first sub-conductive layer is located in the first connection region and the conductive layer stack region, and each second sub-conductive layer is located in the second connection region and the conductive layer stack region; Each of the conductive layers includes a first flat portion and a second flat portion connected together; the first flat portion of the first sub-conductive layer is located within the first connection region, and the second flat portion of the first sub-conductive layer is located within the conductive layer stack region; the first flat portion of the second sub-conductive layer is located within the second connection region, and the second flat portion of the second sub-conductive layer is located within the conductive layer stack region; the end of the second flat portion of each conductive layer away from the first flat portion includes a transition section, and the distance between the surface of the transition section away from the base dielectric layer and the base dielectric layer gradually decreases in the direction from the first flat portion to the second flat portion.

[0006] In some embodiments, the conductive layer of the capacitor body includes a first type of conductive layer with the smallest distance from the base dielectric layer and a plurality of second type of conductive layers located on the side of the first type of conductive layer away from the base dielectric layer; among two adjacent second type of conductive layers, the projection of the edge of the transition section of the second type of conductive layer with a larger distance from the base dielectric layer away from the first straight portion onto the base dielectric layer is a first projection line, and the projection of the edge of the second straight portion of the other second type of conductive layer away from the base dielectric layer toward the first straight portion onto the base dielectric layer is a second projection line; the first projection line coincides with the second projection line.

[0007] In some embodiments, the conductive layer of the capacitor body includes a first type of conductive layer with the smallest distance from the base dielectric layer and a plurality of second type of conductive layers located on the side of the first type of conductive layer away from the base dielectric layer; among two adjacent second type of conductive layers, the projection of the edge of the transition section of the second type of conductive layer with a larger distance from the base dielectric layer away from the first straight portion onto the base dielectric layer is a first projection line, and the projection of the edge of the second straight portion of the other second type of conductive layer away from the base dielectric layer toward the first straight portion onto the base dielectric layer is a second projection line, there is a gap between the first projection line and the second projection line, and the orthographic projection of the first projection line onto the base dielectric layer falls within the orthographic projection of the second straight portion of the second type of conductive layer closer to the base dielectric layer onto the base dielectric layer.

[0008] In some embodiments, each of the second type of conductive layers includes a connection portion located between the first flat portion and the second flat portion, and at least one of the connection portions includes a first sub-connection segment directly connected to the first flat portion, a second sub-connection segment directly connected to the second flat portion, and a third sub-connection segment located between the first sub-connection segment and the second sub-connection segment; from the direction from the first flat portion to the second flat portion, the distance between the first sub-connection segment and the second sub-connection segment and the base dielectric layer gradually increases, and the third sub-connection segment is flat; the orthographic projection of the third sub-connection segment on the base dielectric layer falls within the orthographic projection of the second flat portion located on its side facing the base dielectric layer and spaced apart by one conductive layer on the base dielectric layer.

[0009] In some embodiments, the width of the gap along the second direction is less than or equal to three times the thickness of the conductive layer.

[0010] In some embodiments, the surface of the transition section away from the base dielectric layer is a plane, and the angle between the plane and the plane containing the second direction is 50° to 70°.

[0011] In some embodiments, the thickness of the conductive layer is 10 nm to 100 nm; in the conductive layer stack region, the thickness of the spacer dielectric layer located between two adjacent conductive layers is 5 nm to 50 nm.

[0012] In some embodiments, the stacked capacitor further includes a top dielectric layer, a first connection hole, and a second connection hole; The top dielectric layer is located on the side of the capacitor body opposite to the base dielectric layer; the first connection hole is located in the first connection area, and along the first direction, the first connection hole penetrates the top dielectric layer, each of the first sub-conductive layers and each of the spacer dielectric layers, and exposes the base dielectric layer; the second connection hole is located in the second connection area, and along the first direction, the second connection hole penetrates the top dielectric layer, each of the second sub-conductive layers and each of the spacer dielectric layers, and exposes the base dielectric layer; The first connecting hole is provided with a first conductive structure, and the second connecting hole is provided with a second conductive structure; the first conductive structure is electrically connected to the sidewall of the first sub-conductive layer; the second conductive structure is electrically connected to the sidewall of the second sub-conductive layer.

[0013] A second aspect of this application provides a semiconductor device comprising the stacked capacitors described above.

[0014] In some embodiments, the semiconductor device further includes a chip, and the stacked capacitors are disposed outside the surface of the chip or inside the chip.

[0015] The stacked capacitor provided in this application embodiment has a transition section at the end of the second flat portion of each conductive layer away from the first flat portion. This allows the deposited material to more completely cover the relatively gentle transition section, effectively avoiding problems such as thinning of the deposited material, voids, or incomplete coverage that may occur due to excessively steep slopes at the edges of the conductive layers. Furthermore, as the number of conductive layers increases, a longer stepped structure forms at the edge region of the stacked conductive layers. The transition section can effectively reduce the overall aspect ratio of the stepped structure, avoiding the problem of decreased reliability of film layer connections as the number of conductive layers increases.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0018] Figure 1 This is a schematic diagram of the structure of a stacked capacitor provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a stacked capacitor provided in another embodiment of this application; Figure 3 This is a top view of a stacked capacitor provided in an embodiment of this application; Figures 4 to 16 This is a schematic diagram showing the structure of different processes corresponding to the fabrication of stacked capacitors according to an embodiment of this application. Detailed Implementation

[0019] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0020] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0021] The stacked capacitors and semiconductor devices of the present application embodiments are described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can complement or combine with each other.

[0022] This application provides a stacked capacitor, such as Figure 1 and Figure 2 As shown, the stacked capacitor includes a base dielectric layer 10 and a capacitor body 20 located on one side of the base dielectric layer. The capacitor body includes multiple stacked conductive layers 21 and spacer dielectric layers 22 located between each adjacent pair of conductive layers 21. In each conductive layer 21, along a first direction X from the base dielectric layer 10 to the capacitor body 20, the multiple conductive layers 21 include sequentially alternating first sub-conductive layers 21A and second sub-conductive layers 21B. The stacked capacitor has a first connection region Q1, a conductive layer stack region Q3, and a second connection region Q2 arranged along a second direction Y. Each first sub-conductive layer 21A is located in the first connection region Q1 and the conductive layer stack region Q3, and each second sub-conductive layer 21B is located in the second connection region Q2 and the conductive layer stack region Q3.

[0023] Each conductive layer 21 includes a first flat portion 211 and a second flat portion 212 connected together. The first flat portion 211 of the first sub-conductive layer 21A is located in the first connection region Q1, and the second flat portion 212 of the first sub-conductive layer 21A is located in the conductive layer stack region Q3.

[0024] The first straight portion 211 of the second sub-conductive layer 21B is located within the second connection region Q2, and the second horizontal portion 212 of the second sub-conductive layer 21B is located within the conductive layer stack region Q3. The end of the second straight portion 212 of each conductive layer away from the first straight portion 211 includes a transition section 2121. From the first straight portion 211 towards the second straight portion 212, the distance between the transition section 2121 and the surface of the base dielectric layer 10 gradually decreases.

[0025] The stacked capacitor provided in this application embodiment has a transition section 2121 at the end of the second straight portion 212 of each conductive layer 21 away from the first straight portion 211. The transition section 2121 makes the edge sidewall of the conductive layer 21 present an inclined shape with the distance from the base dielectric layer 10 gradually decreasing, rather than a vertical and steep cross section. When the spacer dielectric layer 22 and the next conductive layer 21 are deposited on top of the conductive layer 21, the deposited material can more completely cover the relatively gentle transition section 2121, effectively avoiding problems such as thinning of the deposited material, voids or incomplete coverage that may occur due to the excessively steep slope of the edge of the conductive layer 21.

[0026] Furthermore, as the number of conductive layers 21 increases, a longer stepped structure will be formed at the edge region of the conductive layer 21 stack. The transition section 2121 can effectively reduce the overall height-to-width ratio of the stepped structure, avoid the problem of decreased reliability of film connection after the number of conductive layers 21 is stacked up, and prevent problems such as interruption of film connection caused by material deposition defects.

[0027] In one embodiment, the material of the base dielectric layer 10 may be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride, etc., to provide a platform for the subsequent manufacturing of stacked capacitors (and MIM stacked capacitors).

[0028] It is understood that the stacked capacitor can be a capacitor structure formed inside the chip or on the chip surface. In the implementation where the stacked capacitor is formed inside the chip or on the chip surface, the base dielectric layer 10 can also be used to isolate the previous metal interconnect structure in the back-end of line (BEOL) process, that is, to electrically isolate the stacked capacitor from the chip.

[0029] In one embodiment, such as Figure 1 As shown, the conductive layer 21 of the capacitor body 20 includes a first type of conductive layer with the smallest distance from the base dielectric layer 10 and a plurality of second type conductive layers located on the side of the first type of conductive layer away from the base dielectric layer 10. In two adjacent second type conductive layers, the projection of the edge of the transition section 2121 of the second type conductive layer with the larger distance from the base dielectric layer 10 away from the first straight portion 211 onto the base dielectric layer 10 is a first projection line. The projection of the edge of the second straight portion 212 of the other second type conductive layer away from the base dielectric layer 10 towards the first straight portion 211 onto the base dielectric layer 10 is a second projection line. The first projection line coincides with the second projection line.

[0030] like Figure 1 As shown, the conductive layer 21 includes conductive layers 21a to 21d, and a spacer dielectric layer 22 is provided between adjacent conductive layers 21. Conductive layer 21a is bonded to the base dielectric layer 10 and is a first type of conductive layer, while conductive layers 21b to 21d are second type of conductive layers. Taking adjacent conductive layers 21b and 21c as examples, the first projection line of the edge of the transition section 2121 of conductive layer 21c away from the first straight portion 211 on the base dielectric layer 10 falls within the dashed line L1. Similarly, the second projection line of the edge of the second straight portion 212 of conductive layer 21b away from the base dielectric layer 10 (i.e., the upper surface of the second straight portion 212) towards the first straight portion 211 on the base dielectric layer 10 also falls within the dashed line L1.

[0031] With this configuration, in the first direction X, the projection of the effective area (i.e., the second flat portion 212) of each second type of conductive layer used to form a capacitor on the base dielectric layer 10 covers the effective area of ​​the conductive layer 21 below it as much as possible, so that the stacked capacitor has a high total capacitance value, avoids wasting the internal area of ​​the stacked capacitor, and is conducive to realizing high-density, miniaturized integration of the stacked capacitor.

[0032] In the above embodiments, the conductive layer 21 is 4 layers. In other embodiments, the conductive layer can also be multiple layers, such as 3 layers, 4 layers, 5 layers, 7 layers, 8 layers, etc.

[0033] In one embodiment, such as Figure 1 As shown, each type of second conductive layer includes a connecting portion 213 located between the first flat portion 211 and the second flat portion 212. From the first flat portion 211 to the second flat portion 212, the distance between the connecting portion 213 and the base dielectric layer 10 gradually increases. The first flat portion 211 located in the first connecting region Q1 and the second connecting region Q2 is lower in height than the second flat portion 212 located in the conductive layer stacking region Q3. The connecting portion 213 creates a smooth, sloping upward connection from the first flat portion 211 to the second flat portion 212, which helps ensure the uniformity and continuity of the conductive layer 21 during manufacturing deposition, and avoids stress concentration or film defects in the conductive layer 21.

[0034] In one embodiment, such as Figure 2 As shown, in two adjacent second-type conductive layers, the projection of the edge of the transition section 2121 of the second-type conductive layer that is farther from the first straight portion 211 on the base dielectric layer is the first projection line. The projection of the edge of the second straight portion 212 of the other second-type conductive layer that is farther from the base dielectric layer toward the first straight portion 211 on the base dielectric layer is the second projection line. There is a gap D between the first projection line and the second projection line, and the orthographic projection of the first projection line on the base dielectric layer 10 falls within the orthographic projection of the second straight portion 212 of the second-type conductive layer that is closer to the base dielectric layer 10 on the base dielectric layer 10.

[0035] like Figure 2As shown, taking adjacent conductive layers 21b and 21c as examples, the first projection line of the edge of the transition section 2121 of conductive layer 21c away from the first straight portion 211 on the base dielectric layer 10 falls within the dashed line L2. The second projection line of the edge of the second straight portion 212 of conductive layer 21b away from the surface of the base dielectric layer 10 (that is, the upper surface of the second straight portion 212) towards the first straight portion 211 on the base dielectric layer 10 falls within the dashed line L1. Furthermore, the orthographic projection of the first projection line on the base dielectric layer 10 falls within the orthographic projection of the second straight portion 212 of the second type of conductive layer closer to the base dielectric layer 10 on the base dielectric layer 10. That is, the orthographic projection of the dashed line L2 on the base dielectric layer 10 falls within the orthographic projection of the second straight portion 212 of conductive layer 21b on the base dielectric layer 10.

[0036] With the above settings, the aspect ratio of the stepped structure formed by the conductive layer 21 is smaller, which is beneficial to further reduce the slope of the stepped structure and avoid the phenomenon of film breakage or excessive thinness when the spacer dielectric layer 22 and the next conductive layer 21 are deposited on top of the conductive layer 21. This is beneficial to improve the reliability of subsequent film preparation.

[0037] In one embodiment, such as Figure 2 As shown, each of the second type of conductive layers includes a connecting portion 213 located between the first flat portion 211 and the second flat portion 212. At least one connecting portion 213 includes a first sub-connecting segment 2131 directly connected to the first flat portion 211, a second sub-connecting segment 2132 directly connected to the second flat portion 212, and a third sub-connecting segment 2133 located between the first sub-connecting segment 2131 and the second sub-connecting segment 2132. From the direction from the first flat portion 211 to the second flat portion 212, the distance between the first sub-connecting segment 2131 and the second sub-connecting segment 2132 and the base dielectric layer 10 gradually increases, and the third sub-connecting segment 2133 is flat. The orthographic projection of the third sub-connecting segment 2133 on the base dielectric layer 10 falls within the orthographic projection of the second flat portion 212 located on its side facing the base dielectric layer 10 and separated from it by a conductive layer 21 on the base dielectric layer 10.

[0038] like Figure 2 As shown, the first straight portion 211 of the conductive layer 21d is connected to the first connecting segment 2131, and is connected to the second connecting segment 2132 through the third connecting segment 2133. The second connecting segment 2132 is connected to the second straight portion 212. The orthographic projection of the third sub-connecting segment 2133 on the base dielectric layer 10 falls within the orthographic projection of the second straight portion 212 of the conductive layer 21b on the base dielectric layer 10.

[0039] With the above configuration, the first sub-connection segment 2131 serves as the starting ramp, the straight third sub-connection segment 2133 forms a horizontal transition platform, and the second sub-connection segment 2132 serves as the final ramp, connecting the first straight portion 211 to the higher second straight portion 212. This can prevent the conductive layer 21 from breaking or thinning, which is beneficial to improving the reliability of the stacked capacitor.

[0040] In one embodiment, such as Figure 2 As shown, the width of the gap D along the second direction Y is less than or equal to three times the thickness of the conductive layer 21. This setting can create a gently sloping stepped structure at the edge region of the conductive layer 21 stack, ensuring the continuity and reliability of each film layer, while also avoiding the loss of effective capacitance area due to an excessively wide gap D.

[0041] In one embodiment, such as Figure 1 and Figure 2 As shown, the surface of the transition section 2121 away from the base dielectric layer 10 is a plane, and the angle between the plane and the plane containing the second direction Y is 50°~70°. The angle can be, for example, 50°, 55°, 60°, 65°, 70°, etc.

[0042] In one embodiment, the conductive layer 21 is made of a metallic material, such as aluminum. Of course, in other embodiments, the conductive layer material can also be, but is not limited to, titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, gypsum, molybdenum, hafnium, and other etchable metals. In some embodiments, the material of each conductive layer 101 can be the same.

[0043] In one embodiment, the thickness of the conductive layer 21 is 10 nm to 100 nm. For example, the thickness of the conductive layer 21 can be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm. In some embodiments, the thickness of each conductive layer 21 can be the same.

[0044] In one embodiment, the material of the spacer dielectric layer 22 may be any one or a mixture of materials selected from, but not limited to, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN. In some embodiments, the thickness of each spacer dielectric layer 22 may be the same.

[0045] In one embodiment, in the conductive stack region Q3, the thickness of the spacer dielectric layer 22 located between two adjacent conductive layers 21 is 5 nm to 50 nm. The thickness of the spacer dielectric layer 22 can be, for example, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm. In some embodiments, the thickness of each spacer dielectric layer 22 can be the same.

[0046] It is understood that in some other embodiments, the materials of the conductive layers 21 may also be different. The thickness of the conductive layers 21 may also be different. The materials of the spacer dielectric layers 22 may also be different. The thickness of the spacer dielectric layers 22 may also be different.

[0047] In one embodiment, such as Figure 1 and Figure 2 As shown, the stacked capacitor also includes a top dielectric layer 30 located on the side of the capacitor body 20 facing away from the base dielectric layer 10. The material of the top dielectric layer 30 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0048] The top dielectric layer 30 is relatively thick, at least greater than the thickness of a spacer dielectric layer. The thickness of the top dielectric layer 30 can be greater than the thickness of a conductive layer.

[0049] For stacked capacitors that are away from the base dielectric layer 10 (which can be understood as the top of the stacked capacitors) and require other metal interconnect structures to be set later, the top dielectric layer 30 can be used to isolate the metal interconnect structures in the back-end of line (BEOL) process on the top of the stacked capacitors.

[0050] In one embodiment, such as Figure 1 and Figure 2 As shown, the stacked capacitor also includes a first connection hole 411 and a second connection hole 421. The first connection hole 411 is located in the first connection region Q1, and along the first direction X, the first connection hole 411 penetrates the top dielectric layer 30, each first sub-conductive layer 21A, and each spacer dielectric layer 22, and exposes the base dielectric layer 10. The second connection hole 421 is located in the second connection region Q2, and along the first direction X, the second connection hole 421 penetrates the top dielectric layer 30, each second sub-conductive layer 21B, and each spacer dielectric layer 22, and exposes the base dielectric layer 10.

[0051] A first conductive structure 412 is provided in the first connecting hole 411, and a second conductive structure 422 is provided in the second connecting hole 421. The first conductive structure 412 is electrically connected to the sidewall of the first sub-conductive layer 21A, and the second conductive structure 422 is electrically connected to the sidewall of the second sub-conductive layer 21B.

[0052] In one embodiment, the first conductive structure 412 includes a first conductive body 4121 and a first seed layer 4122, wherein the first conductive body 4121 fills the first connection hole 411. The first seed layer 4122 is located between the first conductive body 4121 and the inner wall of the first connection hole 411.

[0053] The second conductive structure 422 includes a second conductive body 4221 and a second seed layer 4222. The second conductive body 4221 fills the second connection hole 421, and the second seed layer 4222 is located between the second conductive body 4221 and the inner wall of the second connection hole 421.

[0054] In one embodiment, the materials of the first conductive body 4121 and the second conductive body 4221 may be metals such as copper (Cu) and tungsten (W). The materials of the first seed layer 4122 and the second seed layer 4222 may be metals such as TiN and TaN.

[0055] In one embodiment, such as Figure 3 As shown, there are multiple first conductive structures 412 and multiple second conductive structures 422, and the number of first conductive structures 412 and second conductive structures 422 is the same. This arrangement can increase the contact area between the first conductive structures 412 and second conductive structures 422 and the conductive layer, thereby reducing the contact resistance.

[0056] This application also provides a semiconductor device. The semiconductor device includes stacked capacitors as described above.

[0057] In some embodiments, the semiconductor device further includes a chip, and the stacked capacitors are disposed outside the chip surface or inside the chip.

[0058] Chips include, but are not limited to, high-performance chips such as CPU chips, GPU chips, FPGA chips, 5G modem chips, system-on-a-chip (SoC), power management chips (PMIC), and 2.5D / 3D chiplets.

[0059] This application also provides a method for fabricating stacked capacitors, the method comprising: Step S100: Provide a base dielectric layer; Step S200: A capacitor body is formed on one side of the base dielectric layer. The capacitor body includes multiple stacked conductive layers and a spacer dielectric layer located between each pair of adjacent conductive layers. In each conductive layer, in a first direction from the base dielectric layer to the capacitor body, the multiple conductive layers include sequentially alternating first sub-conductive layers and second sub-conductive layers. The stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a second direction. Each first sub-conductive layer is located in the first connection region and the conductive layer stack region, and each second sub-conductive layer is located in the second connection region and the conductive layer stack region. Each formed conductive layer includes a first flat portion and a second flat portion connected together; the first flat portion of the first sub-conductive layer is located within the first connection region, and the second flat portion of the first sub-conductive layer is located within the conductive layer stack region; the first flat portion of the second sub-conductive layer is located within the second connection region, and the second flat portion of the second sub-conductive layer is located within the conductive layer stack region; the end of the second flat portion of each formed conductive layer away from the first flat portion includes a transition section, and the distance between the surface of the transition section away from the base dielectric layer and the base dielectric layer gradually decreases in the direction from the first flat portion to the second flat portion.

[0060] In step S100, the base dielectric layer 10 can be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods.

[0061] In step S200, conductive material layers can be deposited layer by layer, and patterned using etching to form the corresponding conductive layers. The following is a combination of... Figures 4 to 13 The formation of the capacitor body is described in detail.

[0062] like Figure 4 As shown, a first conductive material layer 21a' is first deposited on the base dielectric layer 10. Figures 5 to 7 As shown, a mask layer 50 (such as photoresist) is disposed on the first conductive material layer 21a'. The photoresist above the area to be etched is etched to create the required openings. The conductive material layer is patterned by etching, and the conductive layer 21a is formed after removing the mask layer. The conductive material layer can be formed by deposition, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0063] Specifically, a transition section 2121 can be formed by controlling the lateral and longitudinal etching rates of the conductive material layer. Taking titanium nitride as an example, the temperature of the etching environment is increased to 80°C, the gas pressure is increased to 20 mTorr (millitor, a unit of gas pressure under vacuum), and CF4 (carbon tetrafluoride, the main gas of the etching reaction) with a flow rate of 60 sccm (standard cubic centimeters per minute) and O2 (oxygen, which helps to regulate the etching reaction characteristics) are introduced, while argon is not introduced. At the same time, the radio frequency power is reduced to 50W (the energy used to excite the gas to generate plasma). Through the coordinated control of these parameters, the ratio of longitudinal etching rate to lateral etching rate is reduced, which can weaken the directional bombardment of ions during the etching process, enhance the proportion of chemical reaction etching, and make the edge of the conductive material layer etched present a more inclined shape. From the first flat part to the second flat part, the distance between the surface of the transition section away from the base dielectric layer and the base dielectric layer gradually decreases.

[0064] After that, as Figure 8 As shown, a first spacer dielectric layer 22a and a second conductive material layer 21b' are formed on the conductive layer 21a. The first spacer dielectric layer 22a can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods. The first spacer dielectric layer 22a covers the surface of the conductive layer 21a away from the base dielectric layer 10, covers the transition section 2121 of the conductive layer 21a away from the base dielectric layer 10, and covers the area of ​​the base dielectric layer 10 exposed from the conductive layer 21a.

[0065] After that, as Figure 9 As shown, a conductive layer 21b is formed. The conductive layer 21b can be configured in the same way as the conductive layer 21a, as described above.

[0066] After that, as Figure 10 As shown, a second spacer dielectric layer 22b and a third conductive material layer 21c' are formed on the conductive layer 21b. A mask layer 50 (such as photoresist) is disposed on the first conductive material layer 21a', and the photoresist above the area to be etched is etched to form the required opening. The third conductive material layer 21c' is patterned by etching, and the conductive layer 21c is formed after the mask layer is removed.

[0067] Specifically, such as Figure 11 and Figure 12As shown, oxygen can be used to etch the photoresist, causing the edge region of the photoresist to shrink. Then, the third conductive material layer 21c' is patterned by etching to form the conductive layer 21c. The projection of the edge of the transition section 2121 of the conductive layer 21c away from the first flat portion 211 onto the base dielectric layer is the first projection line. The projection of the edge of the second flat portion 212 of the conductive layer 21b away from the base dielectric layer toward the first flat portion 211 onto the base dielectric layer is the second projection line. By controlling the degree of etching of the photoresist by oxygen, the width of the spacing D between the first projection line and the second projection line can be adjusted, or the first projection line and the second projection line can be made to coincide.

[0068] After that, as Figure 13 As shown, other conductive layers 21 and spacer dielectric layers 22 are formed sequentially until the capacitor body 20 is formed.

[0069] In one embodiment, the preparation method further includes step S300, in which, as... Figure 14 As shown, a top dielectric layer 30 is formed. The top dielectric layer 30 is located on the side of the capacitor body 20 away from the base dielectric layer 10.

[0070] In one embodiment, the preparation method further includes step S400, in which, as... Figure 15 As shown, a first connection hole 411 is formed in the first connection area Q1. Along the first direction X, the first connection hole 411 penetrates the top dielectric layer 30, each first sub-conductive layer 21A and each spacer dielectric layer 22, and exposes the base dielectric layer 10. The second connection hole 421 is located in the second connection area Q2. Along the first direction X, the second connection hole 421 penetrates the top dielectric layer 30, each second sub-conductive layer 21B and each spacer dielectric layer 22, and exposes the base dielectric layer 10.

[0071] In one embodiment, the preparation method further includes step S500, in which, as... Figure 16 As shown, a first conductive structure 412 is formed in the first connecting hole 411, and a second conductive structure 422 is formed in the second connecting hole 421. The first conductive structure 412 is electrically connected to the sidewall of the first sub-conductive layer 21A, and the second conductive structure 422 is electrically connected to the sidewall of the second sub-conductive layer 21B.

[0072] In one embodiment, the first conductive structure 412 includes a first conductive body 4121 and a first seed layer 4122, with the first conductive body 4121 filling the first connection hole 411. The first seed layer 4122 is located between the first conductive body 4121 and the inner wall of the first connection hole 411. The second conductive structure 422 includes a second conductive body 4221 and a second seed layer 4222. The second conductive body 4221 fills the second connection hole 421, and the second seed layer 4222 is located between the second conductive body 4221 and the inner wall of the second connection hole 421. The first seed layer 4122 and the second seed layer 4222 can be formed by atomic layer deposition (ALD) to achieve good coverage.

[0073] In one embodiment, the first conductive body 4121 and the second conductive body 4221 may be electroplated, and the conductive body material is electroplated on the first seed layer 4122 and the second seed layer 4222 respectively, and then chemical mechanical polishing (CMP) is performed to form the first conductive structure 412 and the second conductive structure 422 flush with the top dielectric layer 30.

[0074] In other embodiments, the first conductive structure 412 and the second conductive structure 422 may also be formed by directly filling a conductive body.

[0075] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A stacked capacitor, characterized in that, The stacked capacitors include: Base dielectric layer; A capacitor body located on one side of the base dielectric layer, the capacitor body comprising multiple stacked conductive layers and spacer dielectric layers located between each adjacent pair of conductive layers; in each conductive layer, in a first direction from the base dielectric layer to the capacitor body, the multiple conductive layers include sequentially alternating first sub-conductive layers and second sub-conductive layers; wherein, the stacked capacitor has a first connection region, a conductive layer stack region, and a second connection region arranged along a second direction; each first sub-conductive layer is located in the first connection region and the conductive layer stack region, and each second sub-conductive layer is located in the second connection region and the conductive layer stack region; Each of the conductive layers includes a first flat portion and a second flat portion connected together; the first flat portion of the first sub-conductive layer is located within the first connection region, and the second flat portion of the first sub-conductive layer is located within the conductive layer stack region; the first flat portion of the second sub-conductive layer is located within the second connection region, and the second flat portion of the second sub-conductive layer is located within the conductive layer stack region; the end of the second flat portion of each conductive layer away from the first flat portion includes a transition section, and the distance between the surface of the transition section away from the base dielectric layer and the base dielectric layer gradually decreases in the direction from the first flat portion to the second flat portion.

2. The stacked capacitor according to claim 1, characterized in that, The conductive layer of the capacitor body includes a first type of conductive layer with the smallest distance from the base dielectric layer and a plurality of second type conductive layers located on the side of the first type of conductive layer away from the base dielectric layer; among two adjacent second type conductive layers, the projection of the edge of the transition section of the second type conductive layer with a larger distance from the base dielectric layer away from the first straight portion onto the base dielectric layer is a first projection line, and the projection of the edge of the second straight portion of the other second type conductive layer away from the base dielectric layer toward the first straight portion onto the base dielectric layer is a second projection line; the first projection line coincides with the second projection line.

3. The stacked capacitor according to claim 1, characterized in that, The conductive layer of the capacitor body includes a first type of conductive layer with the smallest distance from the base dielectric layer and a plurality of second type of conductive layers located on the side of the first type of conductive layer away from the base dielectric layer; among two adjacent second type of conductive layers, the projection of the edge of the transition section of the second type of conductive layer with a larger distance from the base dielectric layer away from the first straight portion onto the base dielectric layer is a first projection line, and the projection of the edge of the second straight portion of the other second type of conductive layer away from the base dielectric layer toward the first straight portion onto the base dielectric layer is a second projection line. There is a gap between the first projection line and the second projection line, and the orthographic projection of the first projection line onto the base dielectric layer falls within the orthographic projection of the second straight portion of the second type of conductive layer closer to the base dielectric layer onto the base dielectric layer.

4. The stacked capacitor according to claim 3, characterized in that, Each type of conductive layer includes a connecting portion located between the first flat portion and the second flat portion. At least one of the connecting portions includes a first sub-connecting segment directly connected to the first flat portion, a second sub-connecting segment directly connected to the second flat portion, and a third sub-connecting segment located between the first sub-connecting segment and the second sub-connecting segment. From the first flat portion to the second flat portion, the distance between the first sub-connecting segment and the second sub-connecting segment and the base dielectric layer gradually increases, and the third sub-connecting segment is flat. The orthographic projection of the third sub-connecting segment on the base dielectric layer falls within the orthographic projection of the second flat portion located on its side facing the base dielectric layer and spaced apart by one conductive layer on the base dielectric layer.

5. The stacked capacitor according to claim 3, characterized in that, The width of the gap along the second direction is less than or equal to three times the thickness of the conductive layer.

6. The stacked capacitor according to claim 1, characterized in that, The surface of the transition section away from the base dielectric layer is a plane, and the angle between the plane and the plane containing the second direction is 50°~70°.

7. The stacked capacitor according to claim 1, characterized in that, The thickness of the conductive layer is 10nm~100nm; in the conductive layer stack region, the thickness of the spacer dielectric layer located between two adjacent conductive layers is 5nm~50nm.

8. The stacked capacitor according to claim 1, characterized in that, The stacked capacitor also includes a top dielectric layer, a first connection hole, and a second connection hole; The top dielectric layer is located on the side of the capacitor body opposite to the base dielectric layer; the first connection hole is located in the first connection area, and along the first direction, the first connection hole penetrates the top dielectric layer, each of the first sub-conductive layers and each of the spacer dielectric layers, and exposes the base dielectric layer; the second connection hole is located in the second connection area, and along the first direction, the second connection hole penetrates the top dielectric layer, each of the second sub-conductive layers and each of the spacer dielectric layers, and exposes the base dielectric layer; The first connecting hole is provided with a first conductive structure, and the second connecting hole is provided with a second conductive structure; the first conductive structure is electrically connected to the sidewall of the first sub-conductive layer; the second conductive structure is electrically connected to the sidewall of the second sub-conductive layer.

9. A semiconductor device, characterized in that, The semiconductor device includes a stacked capacitor as described in any one of claims 1 to 8.

10. The semiconductor device according to claim 9, characterized in that, The semiconductor device further includes a chip, and the stacked capacitor is disposed outside the surface of the chip or inside the chip.

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