Display panel and electronic device including the same

Abstract

The present disclosure relates to a display panel and a display device including the same. The display panel includes a base layer, a circuit layer disposed on the base layer and including a transistor, a display element layer disposed on the circuit layer and including a light emitting element, and an organic insulating layer disposed between the circuit layer and the display element layer. A plurality of first recessed patterns is defined on an upper surface of the organic insulating layer and does not permeate the organic insulating layer, the light emitting element includes a first electrode, a second electrode disposed on the first electrode, and a light emitting layer disposed between the first electrode and the second electrode, and a portion of the first electrode is disposed inside the plurality of first recessed patterns.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0050836, filed on April 16, 2024, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to display panels and display devices including the same, and more particularly, to display panels having increased luminous efficiency and display devices including the same. Background Technology

[0004] Display devices are used in various multimedia devices such as televisions, mobile phones, tablet computers, and game consoles to provide users with visual information. Recently, various types of flexible display devices that are foldable or bendable have been developed. Flexible display devices can deform in different ways, such as folding, rolling, or bending, and are therefore easy to carry.

[0005] Recently, various types of display devices, such as curved display devices, rollable display devices, and foldable display devices, require display panels with increased luminous efficiency. Summary of the Invention

[0006] This disclosure provides a display panel with improved luminous efficiency and a display device including the same.

[0007] Embodiments of the present invention provide a display panel, comprising: a substrate layer; a circuit layer disposed on the substrate layer and including transistors; a display element layer disposed on the circuit layer and including light-emitting elements; and an organic insulating layer disposed between the circuit layer and the display element layer. A plurality of first recessed patterns are defined on the upper surface of the organic insulating layer and do not penetrate the organic insulating layer. The light-emitting element includes a first electrode, a second electrode disposed on the first electrode, and a light-emitting layer disposed between the first electrode and the second electrode. A portion of the first electrode is disposed within the plurality of first recessed patterns.

[0008] In one embodiment, the upper surface of the organic insulating layer may include a top surface and an inner surface defining each of a plurality of first recessed patterns, and each of the plurality of first recessed patterns may be recessed to a first depth in the direction from the top surface to the circuit layer.

[0009] In an implementation, the first depth may be from about 0.01 micrometers (μm) to about 0.5 μm.

[0010] In one embodiment, the first electrode may include a first portion that contacts the top surface and a second portion that contacts the inner surface of each of a plurality of first recessed patterns.

[0011] In an implementation, the thickness of the first part may be substantially the same as the thickness of the second part.

[0012] In an implementation, the inner surface of each of the plurality of first recessed patterns may include a lower surface facing the bottom surface of the organic insulating layer and a side surface extending from the top surface toward the lower surface.

[0013] In one embodiment, the bottom surface of the organic insulating layer may contact the circuit layer, and the first minimum distance between the bottom and top surfaces of the organic insulating layer may be longer than the second minimum distance between the bottom and lower surfaces of the organic insulating layer.

[0014] In one embodiment, the lower surface and the side surface may form a first angle therebetween, and the first angle may be about 90 degrees to about 150 degrees.

[0015] In an embodiment, the substrate layer may include a light-emitting area corresponding to the light-emitting element and a non-light-emitting area adjacent to the light-emitting area, and a plurality of first recessed patterns may overlap with the light-emitting area.

[0016] In an embodiment, the display element layer may further include a pixel defining film that overlaps with the non-light-emitting area and is disposed on an organic insulating layer.

[0017] In one embodiment, the opening may be defined in a pixel defining film, and at least a portion of the first electrode may be exposed by the opening.

[0018] In one embodiment, a plurality of first recessed patterns may be spaced apart from each other in a first direction, and the distance between adjacent first recessed patterns in the first direction may be about 0.1 μm to about 10 μm.

[0019] In an embodiment, the first width of each of the plurality of first recessed patterns in a first direction may be from about 0.1 μm to about 10 μm.

[0020] In an embodiment, the light-emitting element may further include a hole transport region disposed between the first electrode and the light-emitting layer and an electron transport region disposed between the light-emitting layer and the second electrode, and the hole transport region may be directly disposed on the first electrode.

[0021] In this implementation, the hole transport region may include organic materials.

[0022] In an embodiment, the display panel may further include an encapsulation layer disposed on the display element layer.

[0023] In one embodiment, a plurality of second recessed patterns, each corresponding to a plurality of first recessed patterns, may be defined on the upper surface of the second electrode, and a portion of the encapsulation layer may fill each of the plurality of second recessed patterns.

[0024] In an embodiment of the present invention, an electronic device includes: a display panel including a light-emitting area and a non-light-emitting area adjacent to the light-emitting area; a power supply configured to provide power to the display panel; an optical layer disposed on the display panel; and a window disposed on the optical layer. The display panel includes: a substrate layer; a circuit layer disposed on the substrate layer and including transistors; a display element layer disposed on the circuit layer and including light-emitting elements; and an organic insulating layer disposed between the circuit layer and the display element layer. A plurality of first recessed patterns are defined on the upper surface of the organic insulating layer and do not penetrate the organic insulating layer. The light-emitting element includes a first electrode, a second electrode disposed on the first electrode, and a light-emitting layer disposed between the first electrode and the second electrode. A portion of the first electrode is disposed within the plurality of first recessed patterns.

[0025] In one embodiment, the electronic device may further include a sensor layer disposed between the display panel and the optical layer.

[0026] In an embodiment, the optical layer may include an organic pattern that overlaps with the non-light-emitting area and is disposed on the display panel, and a high refractive index layer covering the organic pattern, wherein the refractive index of the high refractive index layer may be higher than the refractive index of the organic pattern. Attached Figure Description

[0027] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0028] Figure 1A This is an assembly perspective view of a display device according to an embodiment of the present invention;

[0029] Figure 1B An exploded perspective view of a display device according to an embodiment of the present invention;

[0030] Figure 2 A plan view illustrating an enlarged portion of the display device according to an embodiment of the present invention;

[0031] Figure 3 A cross-sectional view illustrating a portion of a display module according to an embodiment of the present invention;

[0032] Figure 4 A cross-sectional view illustrating a portion of a display panel according to an embodiment of the present invention;

[0033] Figure 5 A cross-sectional view illustrating a light-emitting element according to an embodiment of the present invention;

[0034] Figure 6A cross-sectional view illustrating a portion of a display panel according to an embodiment of the present invention;

[0035] Figure 7 A plan view illustrating a portion of a light-emitting element according to an embodiment of the present invention; and

[0036] Figure 8 A block diagram illustrating an electronic device according to an embodiment. Detailed Implementation

[0037] In this specification, it will be understood that when an element (or area, layer, part, etc.) is referred to as being "on", "connected to", or "attached to" another element (or area, layer, part, etc.), it may be directly disposed on / directly connected to / directly attached to the other element (or area, layer, part, etc.), or there may be intermediary elements.

[0038] Throughout this specification, the same reference numerals or symbols refer to the same elements. Furthermore, for the purposes of effective description of the technical content, the thickness, scale, and dimensions of the elements have been enlarged in the accompanying drawings. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] For example, the terms "first" and "second" can be used to describe various components, but components should not be limited by these terms. These terms are used only for the purpose of distinguishing one component from others. For example, without departing from the scope of the invention, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0040] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “up” may be used herein to describe the relationship between one element or feature and another as illustrated in the figures. It will be understood that, in addition to the orientations depicted in the figures, the spatial relative terms are intended to also encompass different orientations of the device in use or operation.

[0041] It will be further understood that when the terms “includes” and / or “including” are used in this specification, they indicate the presence of the described features, numbers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components and / or groups thereof.

[0042] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly stated herein.

[0043] As used herein, “about” includes a stated value and means within an acceptable range of deviation from a particular value, determined by a person skilled in the art considering the measurement in question and the errors associated with the measurement of that particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of a stated value, or within ±10%, ±5%, or ±2% of a stated value. Embodiments of the invention will now be described with reference to the accompanying drawings.

[0044] Figure 1A This is an assembly perspective view of the display device DD according to an embodiment of the present invention. Figure 1B This is an exploded perspective view of a display device DD according to an embodiment of the present invention.

[0045] refer to Figure 1A and Figure 1B The display device DD can be activated in response to an electrical signal. The display device DD can display an image IM and sense external input. The display device DD can include various implementations. For example, the display device DD can include a computer (e.g., a tablet PC and a laptop computer) or a smart TV, etc. In this implementation, the display device DD is exemplarily illustrated as a smartphone.

[0046] The display device DD can display an image IM on a display surface FS parallel to each of the first direction DR1 and the second direction DR2, facing a third direction DR3. The display surface FS on which the image IM is displayed can correspond to the front surface of the display device DD and can also correspond to the front surface FS of the window WM. Hereinafter, the display surface and front surface of the display device DD, as well as the front surface of the window WM, will be represented by the same reference numeral "FS". The image IM can include both still images and moving images. Figure 1A In the image, a clock and several icons are used as examples of visual IM.

[0047] In this embodiment, the front (or upper) and rear (or lower) surfaces of each component are defined based on the orientation of the displayed image IM. The front and rear surfaces of each component may be opposite each other on a third direction DR3, and the normal direction of each of the front and rear surfaces of each component may be parallel to the third direction DR3. (See [reference to the image IM] of the display panel 100) Figure 3The spacing between the front and rear surfaces on the third-direction DR3 can correspond to the display panel 100 (see...). Figure 3 Thickness on the third-party DR3.

[0048] Meanwhile, the directions indicated from the first direction to the third direction DR1, DR2, and DR3 can be relative and can therefore be changed to other directions. Hereinafter, the first direction to the third direction can refer to the directions indicated from the first direction to the third direction DR1, DR2, and DR3 respectively, and can therefore be represented by the same reference numerals or symbols. Furthermore, in this specification, "in a plane" can mean "when viewed from the third direction DR3" (i.e., in a plan view).

[0049] A display device DD according to an embodiment of the present invention can sense user input applied from the outside. User input may include various types of external input, such as a part of the user's body, light, heat, or pressure. User input can be provided in various forms, and the display device DD can sense user input applied to the front, side, or rear surface of the display device DD, depending on its structure. The present invention is not limited to any one embodiment.

[0050] like Figure 1B As explained, the display device DD may include a window WM, a display module DM, and a housing HU. In this embodiment, the window WM and the housing HU are connected to each other to form the exterior of the display device DD. In this embodiment, the housing HU, the display module DM, and the window WM may be stacked sequentially along a third direction DR3.

[0051] The window WM provides the front surface FS of the display device DD. The front surface FS of the window WM defines the front surface of the display device DD mentioned above. The transmissive region TA can be an optically transparent region. For example, the transmissive region TA can be a region with a visible light transmittance of about 90% or more.

[0052] The border region BZA can be a region with relatively lower light transmittance than the transmission region TA. The border region BZA defines the shape of the transmission region TA. The border region BZA can be adjacent to the transmission region TA and can surround the transmission region TA.

[0053] The border area BZA may have a predetermined color. The border area BZA may cover the outer perimeter area NAA of the display module DM, and thus prevent the outer perimeter area NAA from being visible from the outside. However, this is illustrative, and according to an embodiment of the invention, the border area BZA may be omitted in the window WM.

[0054] The window WM may include optically transparent materials. The window WM may include an optically transparent insulating panel. For example, the window WM may be made of glass, plastic, or a combination thereof.

[0055] The window WM may further include functional layers, such as an anti-reflective layer or an anti-fingerprint layer. Although not explained, the window WM may further include a border pattern that overlaps with the aforementioned border area BZA.

[0056] The display module DM can display an image IM and sense external input. The image IM can be displayed on the front surface DS of the display module DM. The front surface DS of the display module DM may include an active area AA and a peripheral area NAA. The active area AA can be activated in response to an electrical signal.

[0057] In this embodiment, the effective area AA may be the area in which the image IM is displayed and external input is also sensed. The transmissive area TA may at least overlap with the effective area AA. For example, the transmissive area TA may overlap with the front surface or at least a portion of the effective area AA. Accordingly, the user can view the image IM or provide external input through the transmissive area TA. However, this is an exemplary illustration, and within the effective area AA, the area in which the image IM is displayed may be separated from the area in which external input is sensed. The invention is not limited to any one embodiment.

[0058] The peripheral area NAA can be the area covered by the border area BZA. The peripheral area NAA can be adjacent to the active area AA. The peripheral area NAA can surround the active area AA. The drive circuit or drive line used to drive the active area AA can be set in the peripheral area NAA.

[0059] The display module DM may include a display panel 100 (see...) Figure 3 ) and sensor layer 200 (see Figure 3 The image IM can be basically displayed on the display panel 100 (see...). Figure 3 On top of that, and external input can be essentially delivered by the sensor layer 200 (see...). Figure 3 ) sensing. Because the display module DM includes the display panel 100 (see Figure 3 ) and sensor layer 200 (see Figure 3 Therefore, displaying the image and sensing external input can be done simultaneously. This will be described in detail later.

[0060] The display device DD according to an embodiment may further include a driving circuit. The driving circuit may include a flexible printed circuit board and a main circuit board. The flexible printed circuit board may be electrically connected to the display module DM. The flexible printed circuit board may connect the display module DM and the main circuit board. However, this is illustrative, and the flexible printed circuit board according to the invention may not be connected to the main circuit board. The flexible printed circuit board may be a rigid board.

[0061] A flexible printed circuit board (PCB) can be connected to pads located in the peripheral area (NAA) of the display module (DM). The PCB provides electrical signals to the display module (DM) for driving it. These electrical signals can be generated by the PCB or by the main circuit board. The main circuit board may include various sub-driving circuits for driving the display module (DM) or connectors for power supply, etc. The main circuit board can be connected to the display module (DM) via the PCB.

[0062] at the same time, Figure 1B The illustration shows a display module DM in an unfolded state, but at least a portion of the display module DM is bendable. In this embodiment, a portion of the display module DM is bendable toward the rear surface of the display module DM, and the portion of the display module DM bent toward the rear surface of the display module DM may be the portion of the display module DM connected to the main circuit board. Accordingly, the main circuit board can be assembled and overlapped with the rear surface of the display module DM.

[0063] The housing HU can be attached to the window WM to define the exterior of the display device DD. The housing HU provides a predetermined internal space. The display module DM can be housed within the internal space.

[0064] The housing HU may comprise a material with relatively high rigidity. For example, the housing HU may comprise glass, plastic, or metal, or may comprise multiple frames and / or panels composed of combinations thereof. The housing HU provides stable protection for the components of the display device DD housed within the internal space from external impacts.

[0065] Figure 2 This is a plan view illustrating an enlarged portion of the display device DD according to an embodiment. As used herein, the plan view is taken in the display device DD (e.g., substrate 110, see...). Figure 4 The view in the thickness direction (i.e., the third direction DR3).

[0066] refer to Figure 2 According to an embodiment, the display device DD may include a plane having three light-emitting areas PXA-R, PXA-G, and PXA-B, and an adjacent non-light-emitting area NPXA. In an embodiment of the present invention, Figure 3 The three types of luminescent regions described in the text, PXA-R, PXA-G, and PXA-B, can cover the effective region AA (see...). Figure 1B Arranged repeatedly.

[0067] The non-emitting area NPXA can be disposed around the first to third emitting areas PXA-R, PXA-G, and PXA-B. The non-emitting area NPXA divides the first to third emitting areas PXA-R, PXA-G, and PXA-B. The non-emitting area NPXA can surround the first to third emitting areas PXA-R, PXA-G, and PXA-B. Within the non-emitting area NPXA, for example, a pixel-defining film PDL (see...) can be disposed. Figure 3 Structures such as those used to prevent color mixing between the first luminescent region and the third luminescent region PXA-R, PXA-G and PXA-B.

[0068] Figure 2 The illustration shows that the first to third light-emitting areas PXA-R, PXA-G, and PXA-B have the same planar shape in a planar view and each has a different planar area; however, embodiments of the present invention are not limited thereto. At least two of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have the same planar area. The planar area of ​​the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be set depending on the color of the light output.

[0069] Figure 2 The first to third light-emitting areas PXA-R, PXA-G, and PXA-B are illustrated to have rectangular shapes in a planar view, but the embodiments of the present invention are not limited thereto. The first to third light-emitting areas PXA-R, PXA-G, and PXA-B can have polygonal shapes (including basic polygonal shapes) of different shapes in the planar view (i.e., in the planar diagram), such as rhombuses or pentagons. In an embodiment, the first to third light-emitting areas PXA-R, PXA-G, and PXA-B can have rectangular shapes (basic rectangular shapes) with rounded corners in the planar view.

[0070] Figure 2 The illustration shows the second light-emitting area PXA-G arranged in the first row, and the first light-emitting area PXA-R and the third light-emitting area PXA-B arranged in the second row; however, the embodiments of the present invention are not limited thereto. The arrangement of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B can be modified differently. For example, the first to third light-emitting areas PXA-R, PXA-G, and PXA-B can be arranged in the same row.

[0071] exist Figure 2The display device DD according to the embodiments described herein exemplarily illustrates three light-emitting areas PXA-R, PXA-G, and PXA-B that emit red, green, and blue light. For example, the display device DD according to the embodiments may include red light-emitting area PXA-R, green light-emitting area PXA-G, and blue light-emitting area PXA-B that are distinct from each other. In this specification, the red light-emitting area PXA-R, green light-emitting area PXA-G, and blue light-emitting area PXA-B may be referred to as the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B, respectively.

[0072] Figure 3 This is a cross-sectional view of a portion of the display module DM according to an embodiment. Figure 3 Explanation along Figure 2 The cross section of the display module DM is captured by line I-I'.

[0073] refer to Figure 3 The display module DM according to the embodiment may include a display panel 100, a sensor layer 200 and an optical layer 300.

[0074] Display panel 100 may be a component that substantially generates an image. Display panel 100 may be a light-emitting display panel, and for example, display panel 100 may be an organic light-emitting display panel, an inorganic light-emitting display panel, a micro LED display panel, or a nano LED display panel.

[0075] The display panel 100 may include a substrate layer 110, a circuit layer 120, an organic insulating layer 130, a display element layer 140, and an encapsulation layer 150.

[0076] The substrate layer 110 may be a component for providing a substrate surface on which the circuit layer 120 is disposed. The substrate layer 110 may be a rigid substrate or a flexible substrate that is bendable, foldable, rollable, etc. The substrate layer 110 may be a glass substrate, a metal substrate, a plastic substrate, or a silicon substrate, etc. However, embodiments of the present invention are not limited thereto, and the substrate layer 110 may be an inorganic layer, an organic layer, or a composite material layer.

[0077] The substrate layer 110 may have a multilayer structure. For example, the substrate layer 110 may include a first synthetic resin layer, multiple or single inorganic layers disposed on the first synthetic resin layer, and a second synthetic resin layer disposed on the multiple or single inorganic layers. The first and second synthetic resin layers may each comprise a polyimide resin, and there are no particular limitations.

[0078] Circuit layer 120 may be disposed on substrate layer 110. Circuit layer 120 may include insulating layer, semiconductor pattern, conductive pattern, and signal lines, etc. (see...) Figure 4 ).

[0079] An organic insulating layer 130 may be disposed on the circuit layer 120. The organic insulating layer 130 may include: a general polymer comprising, for example, benzocyclobutene (“BCB”), polyimide, hexamethyldisiloxane (“HMDSO”), polymethyl methacrylate (“PMMA”), or polystyrene (“PS”), polymer derivatives having phenolic groups, acrylate polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and / or blends thereof.

[0080] The display element layer 140 may be disposed on the organic insulating layer 130. The display element layer 140 may include a pixel defining film PDL and a light-emitting element LD disposed between the pixel defining films PDL.

[0081] Light-emitting elements (LDs) may include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic light-emitting materials, quantum dots, quantum rods, micro-LEDs, or nano-LEDs. An LD may include a first electrode AE, an organic layer OL, and a second electrode CE. The organic layer OL may include a light-emitting layer EML (see...). Figure 5 ).

[0082] An opening OP is defined within a pixel-defining film PDL. The opening OP may expose at least a portion of the first electrode AE. Light-emitting regions PXA-R, PXA-G, and PXA-B may be defined corresponding to the first electrode AE ​​exposed by the respective opening OP. In a planar view, the non-light-emitting region NPXA may overlap with the pixel-defining film PDL.

[0083] Figure 3 This invention illustrates an embodiment in which the organic layer OL and the second electrode CE are provided as a common layer covering the three light-emitting regions PXA-R, PXA-G, and PXA-B, as well as the non-light-emitting region NPXA. However, embodiments of the invention are not limited thereto, and are related to... Figure 3 Unlike the previous embodiment, in another implementation, the organic layer OL and / or the second electrode CE can be provided by patterning within an opening OP defined in the pixel-defining film PDL. For example, in one embodiment, the hole transport region HTR included in the organic layer OL can be provided by patterning via inkjet printing (see...). Figure 5 ), EML of the light-emitting layer (see) Figure 5 ) and Electronic Transmission Zone (ETR) (see Figure 5 ).

[0084] An encapsulation layer 150 may be disposed on the display element layer 140. The encapsulation layer 150 protects the display element layer 140 from moisture, oxygen, and external impurities such as dust particles. The encapsulation layer 150 may include at least one inorganic layer. The encapsulation layer 150 may include a stacked structure of inorganic / organic / inorganic layers.

[0085] The sensor layer 200 may be disposed on the display panel 100. The sensor layer 200 can sense external input applied from the outside. The external input may be user input. User input may include various types of external input, such as a part of the user's body, light, heat, pen, or pressure.

[0086] The sensor layer 200 can be formed on the display panel 100 through a continuous process. In this case, the sensor layer 200 can be directly disposed on the display panel 100. Here, the term "directly disposed" can mean that no third component is disposed between the sensor layer 200 and the display panel 100. That is, no additional adhesive component is disposed between the sensor layer 200 and the display panel 100.

[0087] The sensor layer 200 may include sensing insulating layers IS-IL1 and IS-IL2, as well as conductive patterns MTL1 and MTL2. Sensing insulating layers IS-IL1 and IS-IL2 may each comprise inorganic materials.

[0088] A first conductive pattern MTL1 may be disposed on a first sensing insulating layer IS-IL1 and may be covered by a second sensing insulating layer IS-IL2. A second conductive pattern MTL2 may be disposed on a second sensing insulating layer IS-IL2. The second conductive pattern MTL2 may overlap with the pixel defining film PDL in a planar view. Accordingly, the second conductive pattern MTL2 may be spaced apart from the light-emitting areas PXA-R, PXA-G, and PXA-B, and may overlap with the non-light-emitting area NPXA.

[0089] A portion of the second conductive pattern MTL2 may pass through the second sensing insulating layer IS-IL2 and may be connected to the first conductive pattern MTL1. According to an embodiment, the second conductive pattern MTL2 may include grid lines overlapping the non-light-emitting area NPXA. The grid lines may extend in different diagonal directions relative to the first direction DR1 and the second direction DR2, and may define grid openings corresponding to openings OP defined in the pixel-defining film PDL.

[0090] The grid lines can have a multi-layered structure. For example, the grid lines may include a first layer and a third layer. The second layer may have higher conductivity than the first and third layers. The third layer may have lower external light reflectivity than the second layer. The first layer may be a titanium layer, the second layer may be an aluminum layer, and the third layer may be a titanium layer.

[0091] However, embodiments of the present invention are not limited thereto, and the second conductive pattern MTL2 having a multilayer structure may include at least two of a transparent conductive layer and a metal layer. The second conductive pattern MTL2 having a multilayer structure may include metal layers containing different metals. The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), poly(3,4-ethylenedioxythiophene) (PEDOT), metal nanowires, and graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum, and / or alloys thereof.

[0092] The optical layer 300 can be directly disposed on the sensor layer 200. The optical layer 300 can be formed on the sensor layer 200 through a continuous process. The optical layer 300 can control the direction of light incident from the display panel 100 and can improve the front brightness of the display device DD. The optical layer 300 can collect the light provided from the display panel 100, or can further expand the light generated in some areas of the display panel 100.

[0093] The optical layer 300 may include an organic pattern PP, a high refractive index layer AD1, and an adhesive layer AD2.

[0094] The organic pattern PP can overlap with the pixel-defined film PDL (or the non-emissive area NPXA) on a plane. Accordingly, the organic pattern PP can be spaced apart from the emissive areas PXA-R, PXA-G, and PXA-B, and can overlap with the non-emissive area NPXA. The organic pattern PP can cover the second conductive pattern MTL2. That is, the organic pattern PP can contact the second sensing insulating layer IS-IL2 that overlaps with the non-emissive area NPXA and the second conductive pattern MTL2.

[0095] The patterned opening P_OP can be defined within the organic pattern PP. The patterned opening P_OP can correspond to the opening OP defined in the pixel-defined film PDL. Accordingly, the patterned opening P_OP can correspond one-to-one with the light-emitting areas PXA-R, PXA-G, and PXA-B. According to the embodiment, the planar area of ​​the patterned opening P_OP can be larger than the planar area of ​​the opening OP.

[0096] Organic patterned PP may include acrylate resins, epoxide resins, siloxane resins, polyimide resins, or mixtures thereof. Organic patterned PP may include hollow silica particles. Organic patterned PP may have a refractive index of about 1.50 to about 1.54.

[0097] A high refractive index layer AD1 may be disposed on an organic pattern PP. The high refractive index layer AD1 may cover the second sensing insulating layer IS-IL2 exposed by the pattern opening P_OP and the organic pattern PP. The high refractive index layer AD1 may be an adhesive layer comprising a high refractive index material. For example, the high refractive index layer AD1 may comprise: a base layer containing an acrylate monomer and a high refractive index material included in the base layer. The high refractive index material may include at least any one of zirconium oxide, titanium oxide, and zinc oxide. The refractive index of the high refractive index layer AD1 according to an embodiment may be higher than the refractive index of the organic pattern PP. In this embodiment, the high refractive index layer AD1 may have a refractive index of about 1.55 to about 1.70.

[0098] The high refractive index layer AD1 may be a transparent adhesive layer including any of the pressure-sensitive adhesive film (“PSA”), optically transparent adhesive film (“OCA”), and optically transparent resin (“OCR”).

[0099] Adhesive layer AD2 may be disposed on high refractive index layer AD1. Adhesive layer AD2 may provide a flat surface for any component disposed on adhesive layer AD2. Adhesive layer AD2 may be a transparent adhesive layer including pressure-sensitive adhesive film (PSA), optically clear adhesive film (OCA), and optically clear resin (OCR).

[0100] However, the stacking structure of the optical layer 300 according to the embodiment is not limited to this, and the optical layer 300 may further include a functional layer disposed on the adhesive layer AD2, or may be a component that does not include the adhesive layer AD2. Optionally, with Figure 3 As described in the previous embodiment, the optical layer 300 according to another embodiment may include a high refractive index pattern that overlaps with the pixel defining film PDL on a plane (i.e., in a planar view) and a low refractive index layer covering the high refractive index pattern.

[0101] and Figure 3 Due to differences in interpretation, in another embodiment of the display module DM according to the present invention, the sensor layer 200 may be omitted. In this case, the optical layer 300 may be directly disposed on the display panel 100. In another embodiment of the display module DM, the optical layer 300 may be omitted. Optionally, in another embodiment of the display module DM, both the sensor layer 200 and the optical layer 300 may be omitted.

[0102] Although not explicitly stated, in embodiments of the present invention, the display device DD may further include an optical functional layer disposed between the optical layer 300 and the sensor layer 200. For example, the optical functional layer may reduce the reflectivity of external light incident from outside the display device DD. The optical functional layer may include a color filter. The color filter may have a predetermined arrangement. For example, the color filter may be arranged taking into account the emitted colors of light from the pixels included in the display panel 100. Additionally, the optical functional layer may further include a black matrix adjacent to the color filter.

[0103] Figure 4 A cross-sectional view illustrating a portion of a display panel 100 according to an embodiment of the present invention. Figure 4 This illustrates a partial cross-section of the display panel 100 with respect to a light-emitting element (LD). Figure 4 The text details a portion of the display panel 100, focusing on its connection to... Figure 3 A light-emitting element LD is formed by overlapping any one of the light-emitting regions PXA in the light-emitting regions PXA-R, PXA-G, and PXA-B. Figure 5 A cross-sectional view of the light-emitting element LD according to an embodiment is shown for illustrative purposes. The following will refer to... Figure 4 and Figure 5 The components of the display panel 100 in this embodiment are described in detail.

[0104] refer to Figure 4 The display panel 100 according to an embodiment may include a substrate layer 110. The substrate layer 110 may be a component for providing a substrate surface on which a circuit layer 120 is disposed. The substrate layer 110 may be a glass substrate, a metal substrate, a plastic substrate, or a silicon substrate, etc. However, the embodiments of the present invention are not limited thereto, and in another embodiment, the substrate layer 110 may be an inorganic layer, an organic layer, or a composite material layer.

[0105] A buffer layer 10br may be disposed on the substrate layer 110. The buffer layer 10br prevents metal atoms or impurities from diffusing from the substrate layer 110 to the first semiconductor pattern SP1 above it. The first semiconductor pattern SP1 may include the channel region AC1 of a silicon transistor S-TFT. The buffer layer 10br may control the heating rate during the crystallization process used to form the first semiconductor pattern SP1, and thus enable the first semiconductor pattern SP1 to be formed uniformly.

[0106] A first semiconductor pattern SP1 may be disposed on the buffer layer 10br. The first semiconductor pattern SP1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, or monocrystalline silicon. For example, the first semiconductor pattern SP1 may include low-temperature polycrystalline silicon.

[0107] Figure 4Only a portion of the first semiconductor pattern SP1 disposed on the buffer layer 10br is illustrated, and the first semiconductor pattern SP1 may also be disposed in another region. The first semiconductor pattern SP1 may be arranged across pixels according to specific rules. The first semiconductor pattern SP1 may have different electrical characteristics depending on whether it is doped. The first semiconductor pattern SP1 may have a first region with high conductivity and a second region with low conductivity. The first region may be doped with N-type dopant or P-type dopant. A P-type transistor may include a doped region doped with P-type dopant, and an N-type transistor may include a doped region doped with N-type dopant. The second region may be an undoped region or a region doped at a lower concentration than the first region.

[0108] The conductivity of the first region may be greater than that of the second region, and the first region may be used substantially as an electrode or signal line. The second region may substantially correspond to the active region (or channel) of the transistor. That is, a portion of the first semiconductor pattern SP1 may be the active region of the transistor, another portion may be the source or drain of the transistor, and yet another portion may be a connecting electrode or a connecting signal line.

[0109] The source region SE1 (or source electrode), channel region AC1 (or channel), and drain region DE1 (or drain electrode) of a silicon S-TFT can be formed by a first semiconductor pattern SP1. The source region SE1 and the drain region DE1 can extend from the channel region AC1 in opposite directions in cross-section.

[0110] Simultaneously, although not explicitly stated, a back metal layer may be disposed on the lower portion of the silicon transistor S-TFT and the lower portion of the oxide transistor O-TFT. The back metal layer may overlap with a pixel circuit (not shown) in a planar view and may block external light from reaching the pixel circuit (not shown). The back metal layer may be disposed between the substrate layer 110 and the buffer layer 10br. Optionally, the back metal layer may be disposed between the second insulating layer 20 and the third insulating layer 30. The back metal layer may include a reflective metal. For example, the back metal layer may include silver (Ag), Ag-containing alloys, molybdenum (Mo), Mo-containing alloys, aluminum (Al), Al-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), and p+-doped amorphous silicon, etc. The back metal layer may be connected to an electrode or wiring and may receive a constant voltage or signal therefrom. According to an embodiment of the invention, the back metal layer may be a floating electrode in the form of isolation from other electrodes or wiring. In an embodiment of the invention, an inorganic isolation layer may also be disposed between the substrate layer 110 and the buffer layer 10br.

[0111] A first insulating layer 10 may be disposed on a buffer layer 10br. The first insulating layer 10 may overlap with multiple pixels in a common manner and may cover a first semiconductor pattern SP1. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. In addition to the first insulating layer 10, the insulating layers of the circuit layer 120, which will be described later, may be inorganic layers and / or organic layers, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the aforementioned materials, but is not limited thereto.

[0112] The gate GT1 of the silicon transistor S-TFT may be disposed on the first insulating layer 10. The gate GT1 may be part of a metal pattern. The gate GT1 may overlap with the channel region AC1 in the planar view. The gate GT1 may be used as a mask in the process of doping the first semiconductor pattern SP1. The gate GT1 may include titanium (Ti), silver (Ag), Ag-containing alloys, molybdenum (Mo), Mo-containing alloys, aluminum (Al), Al-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but is not particularly limited thereto.

[0113] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate GT1. The third insulating layer 30 may be disposed on the second insulating layer 20. The second electrode CE20 of the storage capacitor Cst may be disposed between the second insulating layer 20 and the third insulating layer 30. In addition, the first electrode CE10 of the storage capacitor Cst may be disposed between the first insulating layer 10 and the second insulating layer 20.

[0114] A second semiconductor pattern SP2 may be disposed on the third insulating layer 30. The second semiconductor pattern SP2 may include the channel region AC2 of the oxide transistor O-TFT, which will be described later. The second semiconductor pattern SP2 may include an oxide semiconductor. The second semiconductor pattern SP2 may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3).

[0115] The oxide semiconductor may include multiple regions distinguished by whether the transparent conductive oxide is reduced. Regions where the transparent conductive oxide is reduced (hereinafter, reduced regions) may have greater conductivity than regions where the transparent conductive oxide is not reduced (hereinafter, non-reduced regions). Reduced regions may essentially serve as the source or drain of a transistor or as signal lines. Non-reduced regions may essentially correspond to the semiconductor regions (or active regions or channels) of a transistor. That is, one region of the second semiconductor pattern SP2 may be the semiconductor region of a transistor, another region may be the source / drain region of a transistor, and yet another region may be a signal transmission region.

[0116] The source region SE2 (or source electrode), channel region AC2 (or channel), and drain region DE2 (or drain electrode) of an oxide transistor (O-TFT) can be formed by a second semiconductor pattern SP2. The source region SE2 and the drain region DE2 can extend from the channel region AC2 in opposite directions in cross-section.

[0117] A fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may overlap with multiple pixels in a common manner and may cover the second semiconductor pattern SP2. Although not illustrated, in another embodiment, the fourth insulating layer 40 may be provided in the form of an insulating pattern that overlaps with the gate GT2 of the oxide transistor O-TFT in a planar view and exposes the source region SE2 and drain region DE2 of the oxide transistor O-TFT.

[0118] The gate GT2 of the oxide transistor O-TFT may be disposed on the fourth insulating layer 40. The gate GT2 of the oxide transistor O-TFT may be part of a metal pattern. The gate GT2 of the oxide transistor O-TFT may overlap with the channel region AC2.

[0119] A fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the gate GT2. A first connection electrode CNE1 may be disposed on the fifth insulating layer 50. The first connection electrode CNE1 may be connected to the drain region DE1 of the silicon transistor S-TFT through contact holes passing through the first insulating layer to the fifth insulating layers 10, 20, 30, 40 and 50.

[0120] A sixth insulating layer 60 may be disposed on the fifth insulating layer 50. A second connecting electrode CNE2 may be disposed on the sixth insulating layer 60. The second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 via a contact hole passing through the sixth insulating layer 60. A seventh insulating layer 70 may be disposed on the sixth insulating layer 60 and may cover the second connecting electrode CNE2.

[0121] An organic insulating layer 130 may be disposed on the seventh insulating layer 70. The upper surface of the organic insulating layer 130 may have a recessed shape. The organic insulating layer 130 will be described in detail later.

[0122] The sixth insulating layer 60, the seventh insulating layer 70, and the organic insulating layer 130 may be organic layers. For example, the sixth insulating layer 60, the seventh insulating layer 70, and the organic insulating layer 130 may each include: general polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS); polymer derivatives having phenolic groups; acrylate polymers; imide polymers; aryl ether polymers; amide polymers; fluorinated polymers; p-xylene polymers; vinyl alcohol polymers; or blends thereof.

[0123] The light-emitting element (LD) may include a first electrode AE, a second electrode CE, and an organic layer OL disposed between the first electrode AE ​​and the second electrode CE. The first electrode AE ​​may be a cathode or an anode, but embodiments of the present invention are not limited thereto. For example, when the first electrode AE ​​is an anode, the second electrode CE may be a cathode, and when the first electrode AE ​​is a cathode, the second electrode CE may be an anode.

[0124] The first electrode AE ​​of the light-emitting element LD can be disposed on the organic insulating layer 130. The second electrode CE of the light-emitting element LD can be disposed on the organic layer OL. The first electrode AE ​​and the second electrode CE of the light-emitting element LD can each be a (semi-)transmitting electrode or a reflective electrode. According to an embodiment of the present invention, the first electrode AE ​​and the second electrode CE of the light-emitting element LD can each include a reflective layer formed or having a multilayer structure such as LiF / Ca (a laminated structure of LiF and Ca) or LiF / Al (a laminated structure of LiF and Al) formed on the reflective layer, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the first electrode AE ​​of the light-emitting element LD may include a stacked structure of ITO / Ag / ITO.

[0125] A pixel-defining film (PDL) may be disposed on an organic insulating layer 130. The entire pixel-defining film PDL may comprise the same material and may be formed using the same process. The pixel-defining film PDL may have light-absorbing properties, and for example, the pixel-defining film PDL may be black. The pixel-defining film PDL may include a black colorant. The black colorant may include black dyes and / or black pigments. The black colorant may include carbon black, metals (such as chromium), or oxides thereof. The pixel-defining film PDL may correspond to a light-blocking pattern with light-blocking properties.

[0126] A pixel-defining film (PDL) can cover a portion of the first electrode AE ​​of a light-emitting element (LD). For example, an opening OP exposing a portion of the first electrode AE ​​of the LD can be defined in the pixel-defining film (PDL). The pixel-defining film (PDL) can increase the distance between the edge of the first electrode AE ​​and the second electrode CE in the LD. Accordingly, the pixel-defining film (PDL) can be used to prevent arcing, etc., at the edge of the first electrode AE.

[0127] refer to Figure 4 and Figure 5 According to the embodiments, the light-emitting element LD may include a first electrode AE, a hole transport region HTR, a light-emitting layer EML, an electron transport region ETR, and a second electrode CE stacked in sequence.

[0128] A hole transport region (HTR) may be provided on the first electrode (AE). The hole transport region (HTR) may be directly disposed on the first electrode (AE). The hole transport region (HTR) may include an organic material. The hole transport region (HTR) may include a hole transport layer and may further include a hole injection layer. A light-emitting layer (EML) may be provided on the hole transport region (HTR), and an electron transport region (ETR) may be provided on the light-emitting layer (EML). The electron transport region (ETR) may include an electron transport layer and may further include an electron injection layer. The light-emitting layer (EML) and the electron transport region (ETR) may be layers comprising organic or inorganic materials.

[0129] refer to Figure 4 The encapsulation layer 150 may be disposed on the display element layer 140. The encapsulation layer 150 may include a first inorganic encapsulation film, an organic encapsulation film and a second inorganic encapsulation film stacked in sequence, but the layers constituting the encapsulation layer 150 are not limited to these.

[0130] The first and second inorganic encapsulation films protect the display element layer 140 from moisture and oxygen, while the organic encapsulation film protects the display element layer 140 from external impurities (such as dust particles). The first and second inorganic encapsulation films may include silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide layers, etc. The organic encapsulation film may include, but is not limited to, acrylate-based organic layers.

[0131] Figure 6 To illustrate the display panel 100 according to an embodiment of the present invention (see... Figure 4 A cross-sectional view of a portion of ( ). Figure 6 In, corresponding to Figure 4 The cross-section of the AA' region explained in the text is enlarged and explained in more detail. Figure 7 A plan view illustrating a portion of a light-emitting element LD according to an embodiment of the present invention. Figure 7 Explanation Figure 4A plan view of a portion of a light-emitting element (LD) as illustrated in the diagram.

[0132] refer to Figure 6 In the display panel 100 according to the embodiment (see Figure 4 In the circuit layer 120, the organic insulating layer 130 can be disposed on the circuit layer 120, the display element layer 140 can be disposed on the organic insulating layer 130, and the encapsulation layer 150 can be disposed on the display element layer 140.

[0133] The bottom surface BS of the organic insulating layer 130 can contact the circuit layer 120, and the organic insulating layer 130 can be directly disposed on the circuit layer 120. The bottom surface BS of the organic insulating layer 130 can be disposed on the seventh insulating layer 70 of the circuit layer 120 (see...). Figure 4 The organic insulating layer 130 can substantially cover the upper part of the circuit layer 120.

[0134] The upper surface US of the organic insulating layer 130 may include a top surface TS facing the bottom surface BS of the organic insulating layer 130 on the third direction DR3. The top surface TS may have a first minimum distance h1 (i.e., height) from the bottom surface BS of the organic insulating layer 130 on the third direction DR3. The top surface TS may be flat and parallel to the plane defined by the first direction DR1 and the second direction DR2.

[0135] Multiple first recessed patterns DT1 may be defined on the upper surface US of the organic insulating layer 130. The first recessed patterns DT1 may have a shape that is recessed in a direction from the top surface TS towards the circuit layer 120. The first recessed patterns DT1 may have a shape that is recessed to a first depth D1 from the top surface TS in a direction opposite to the third direction DR3. In this specification, the first depth D1 may refer to the minimum distance in the third direction DR3 between the top surface TS and the lower surface GS, which will be described later. The first depth D1 may be from about 0.01 μm to about 0.5 μm. For example, the first depth D1 may be from about 0.05 μm to about 0.3 μm. The organic insulating layer 130 may be provided by forming a planar insulating layer on the circuit layer 120 and then forming the first recessed patterns DT1 on the upper surface of the planar insulating layer. The first recessed patterns DT1 may be formed by developing and photo-etching a planar insulating layer.

[0136] The upper surface US of the organic insulating layer 130 may include an inner surface IS defining a first recessed pattern DT1. The inner surface IS defining the first recessed pattern DT1 may include a lower surface GS facing the bottom surface BS of the organic insulating layer 130 in a third direction DR3 and a side surface SS extending from the top surface TS toward the lower surface GS. The lower surface GS may be flat and parallel to the plane defined by the first direction DR1 and the second direction DR2. The lower surface GS may have a second minimum distance h2 with the bottom surface BS of the organic insulating layer 130 in the third direction DR3, and the second minimum distance h2 may be shorter than the first minimum distance h1. The lower surface GS and the side surface SS may form a first angle therebetween, and the first angle may be from about 90 degrees to about 150 degrees. However, embodiments of the invention are not limited thereto, and the first recessed pattern DT1 may have various shapes, as long as the shape has a structure recessed from the top surface TS.

[0137] Multiple first recessed patterns DT1 may be spaced apart from each other on a plane. The multiple first recessed patterns DT1 may also be spaced apart from each other along a first direction DR1. Along the first direction DR1, the spacing d2 between two adjacent first recessed patterns DT1 may be approximately 0.1 μm to approximately 10 μm. For example, along the first direction DR1, the spacing d2 between two adjacent first recessed patterns DT1 may be approximately 1 μm to approximately 5 μm. Each first recessed pattern DT1 may have a first width d1 along the first direction DR1. The first width d1 may be approximately 0.1 μm to approximately 10 μm. For example, the first width d1 may be approximately 1 μm to approximately 5 μm. However, the first width d1 and the spacing d2 between two adjacent first recessed patterns DT1 along the first direction DR1 are not limited to the aforementioned numerical ranges and may have various values.

[0138] Multiple first recessed patterns DT1 may overlap with the light-emitting area PXA on a plane. Multiple first recessed patterns DT1 may overlap with the light-emitting area PXA on a plane (i.e., in a planar view) and may not overlap with the non-light-emitting area NPXA.

[0139] The display element layer 140 may be disposed on the organic insulating layer 130 and may include a light-emitting element LD (see Figure 4 Light-emitting element (LD) (see) Figure 4 It may include a first electrode AE ​​disposed on the organic insulating layer 130, an organic layer OL disposed on the first electrode AE, and a second electrode CE disposed on the organic layer OL.

[0140] A portion of the first electrode AE ​​may be disposed within the first recessed pattern DT1. The first electrode AE ​​may be directly disposed on the organic insulating layer 130. The first electrode AE ​​may be in contact with the upper surface US of the organic insulating layer 130.

[0141] The first electrode AE ​​may include a first portion P1 disposed on the top surface TS (or overlapping the top surface TS in a plan view) and a second portion P2 disposed inside the first recessed pattern DT1 (or overlapping the first recessed pattern DT1 in a plan view). The first portion P1 may contact the top surface TS, and the second portion P2 may contact the inner surface IS defining the first recessed pattern DT1. On the third direction DR3, the thickness T1 of the first portion P1 may be substantially the same as the thickness T2 of the second portion P2. Furthermore, in this specification, the term "substantially the same" includes not only cases where the thickness of the components is physically identical, but also cases where, despite being identical in design, there are differences occurring during the manufacturing process equivalent to tolerance ranges (e.g., within ±10%, ±5%, or ±2% of the stated value). That is, the thickness of the first electrode AE ​​may be substantially uniform in a cross-sectional view.

[0142] The organic layer OL may be disposed on the first electrode AE, and the organic layer OL may include hole transport regions HTR (see [reference needed]) stacked sequentially. Figure 5 ), EML of the light-emitting layer (see) Figure 5 ) and Electronic Transmission Zone (ETR) (see Figure 5 The organic layer OL can be directly deposited on the first electrode AE. Hole transport region HTR (see...) Figure 5 The organic layer OL can be directly disposed on the first electrode AE. The organic layer OL can be directly disposed on the first portion P1 of the first electrode AE, and can also be directly disposed on the second portion P2 of the first electrode AE. The upper surface of the organic layer OL can follow a step formed on the upper surface of the first electrode AE ​​disposed below the organic layer OL.

[0143] refer to Figure 6 and Figure 7 The second electrode CE may be disposed on the organic layer OL, and a plurality of second recessed patterns DT2 may be defined on the upper surface UL of the second electrode CE. In the region overlapping with the first recessed pattern DT1, a second recessed pattern DT2 recessed to a certain depth in a direction opposite to the third direction DR3 may be defined on the upper surface UL of the second electrode CE. The plurality of second recessed patterns DT2 may have recessed shapes respectively corresponding to the plurality of first recessed patterns DT1.

[0144] Multiple second recessed patterns DT2 can be spaced apart from each other in the first direction DR1 and the second direction DR2. The multiple second recessed patterns DT2 can overlap with the light-emitting area PXA in a plane. The multiple second recessed patterns DT2 can overlap with the light-emitting area PXA in a plane (i.e., in a planar view) and may not overlap with the non-light-emitting area NPXA. Meanwhile, in... Figure 7For convenience, this section illustrates 25 second recessed patterns DT2 defined in 5 rows and 5 columns within a light-emitting region PXA; however, the number and arrangement of multiple second recessed patterns DT2 are not limited to this. Furthermore, in Figure 7 For convenience, the planar shape of the second recessed pattern DT2 is described as square, but the shape of the second recessed pattern DT2 is not limited to this. The second recessed pattern DT2 can have various shapes.

[0145] An encapsulation layer 150 may be disposed on the display element layer 140, and the encapsulation layer 150 may be disposed on the second electrode CE. A portion of the encapsulation layer 150 may be disposed within a plurality of second recessed patterns DT2. A portion of the encapsulation layer 150 may fill each of the plurality of second recessed patterns DT2.

[0146] Although not explicitly stated, the display element layer 140 according to the embodiment may further include a capping layer. The light-emitting element LD may further include a capping layer disposed on the second electrode CE, and the upper surface of the capping layer may have non-uniformity. The upper surface of the capping layer may have a recessed pattern in an area overlapping with the first recessed pattern DT1 in a plan view, and the encapsulation layer 150 may fill the interior of the recessed pattern on the upper surface of the capping layer.

[0147] The upper surface UL of the second electrode CE can substantially represent the uppermost surface of the light-emitting element LD, and in this specification, the upper surface UL of the second electrode CE can be referred to as "the upper surface UL of the light-emitting element LD". The upper surface UL of the light-emitting element LD includes a plurality of second recessed patterns DT2, and therefore can be substantially non-uniform. Since the light-emitting element LD is stacked not only with uniform thickness on the top surface TS of the organic insulating layer 130, but also with uniform thickness on the inner surface IS of the first recessed pattern DT1 defining the organic insulating layer 130, the non-uniformity can be substantially limited to the upper surface UL of the light-emitting element LD. Because the upper surface UL of the light-emitting element LD includes non-uniformity, the display panel 100 according to an embodiment of the present invention (see Figure 4 The luminous efficiency of the display panel 100 according to the embodiment is such that even when the angle θ1 of the light LR emitted from the light-emitting element LD (e.g., organic layer OL) relative to the normal direction (i.e., third direction DR3) of the upper surface UL of the light-emitting element LD is about 30 degrees or greater, the luminous efficiency of the light-emitting element LD ... Figure 4 The light output can also be affected by the change in the light path caused by the non-uniformity of the upper surface UL of the light-emitting element LD (i.e., the second recessed pattern DT2). Figure 6As shown, the light is improved (i.e., increased) by reflecting total internal reflection from the upper surface UL to the side surface passing through the second recessed pattern DT2, whereas in the comparative example without the recessed pattern, the corresponding light is reflected on the upper surface, preventing light from passing through it. Accordingly, in the display panel according to an embodiment of the invention, the output of light generated from the light-emitting element can be increased, and the luminous efficiency can be improved. Because the display device according to an embodiment of the invention includes a display panel with improved optical properties, a display device with improved reliability can be provided.

[0148] Figure 8 A block diagram illustrating the electronic device 1000 according to an embodiment.

[0149] refer to Figure 8 In an embodiment, the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (“I / O”) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may correspond to... Figures 1A to 2 The electronic device 1000 may further include multiple ports for communicating with a video card, sound card, memory card, or Universal Serial Bus (“USB”) device. In one embodiment, the electronic device 1000 may be implemented as a television. In another embodiment, the electronic device 1000 may be implemented as a smartphone. However, the implementation is not limited thereto; in another embodiment, the electronic device 1000 may be implemented as a portable telephone, videophone, smart tablet, smartwatch, tablet personal computer (tablet “PC”), car navigation system, computer monitor, laptop computer, or head-mounted display (e.g., wearable display) (“HMD”), etc.

[0150] Processor 1010 can perform various computing functions. In embodiments, processor 1010 may be a microprocessor, a central processing unit (“CPU”), or an application processor (“AP”), etc. Processor 1010 may be connected to other components via address buses, control buses, or data buses, etc. In embodiments, processor 1010 may be connected to an expansion bus, such as a peripheral component interconnect (“PCI”) bus.

[0151] The memory device 1020 can store data for operation of the electronic device 1000. In embodiments, the memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, or a ferroelectric random access memory (“FRAM”) device) and / or at least one volatile memory device (such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, or a mobile DRAM device, etc.).

[0152] In one embodiment, storage device 1030 may include a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, or a CD-ROM device, etc. In another embodiment, I / O device 1040 may include input devices (such as a keyboard, keypad, mouse device, touchpad, or touch screen, etc.) and output devices (such as a printer or speaker, etc.).

[0153] Power supply 1050 provides power for the operation of electronic device 1000. Power supply 1050 also provides power to display device 1060. Display device 1060 can be connected to other components via a bus or other communication connection. In one embodiment, display device 1060 may be included in I / O device 1040.

[0154] According to the present invention, since the display panel includes a non-uniform upper surface of the light-emitting element, the luminous efficiency can be improved. Accordingly, the reliability of the display device including the display panel can be improved.

[0155] The embodiments have been described above with reference to them. However, those skilled in the art or those with ordinary skill in the related technical fields will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as described in the claims. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of this specification, but should be determined by the claims.

Claims

1. A display panel, characterized in that... include: basal layer; A circuit layer disposed on the substrate layer and including transistors; A display element layer disposed on the circuit layer and including light-emitting elements; as well as An organic insulating layer disposed between the circuit layer and the display element layer Multiple first recessed patterns are defined on the upper surface of the organic insulating layer. The light-emitting element includes a first electrode, a second electrode disposed on the first electrode, and a light-emitting layer disposed between the first electrode and the second electrode. A portion of the first electrode is disposed within the plurality of first recessed patterns.

2. The display panel according to claim 1, characterized in that... The upper surface of the organic insulating layer includes a top surface and an inner surface defining each of the plurality of first recessed patterns, and Each of the plurality of first recessed patterns is recessed to a depth in the direction from the top surface to the circuit layer.

3. The display panel according to claim 2, characterized in that... The depth is 0.01 μm to 0.5 μm.

4. The display panel according to claim 2, characterized in that... The first electrode includes a first portion that contacts the top surface and a second portion that contacts the inner surface of each of the plurality of first recessed patterns.

5. The display panel according to claim 4, characterized in that... The thickness of the first part is the same as the thickness of the second part.

6. The display panel according to claim 2, characterized in that... The inner surface of each of the plurality of first recessed patterns includes a lower surface facing the bottom surface of the organic insulating layer and a side surface extending from the top surface toward the lower surface.

7. The display panel according to claim 6, characterized in that... The bottom surface of the organic insulating layer is in contact with the circuit layer, and The first minimum distance between the bottom surface and the top surface of the organic insulating layer is longer than the second minimum distance between the bottom surface and the lower surface of the organic insulating layer.

8. The display panel according to claim 6, characterized in that... The lower surface and the side surface form a first angle, and The first angle is between 90 and 150 degrees.

9. The display panel according to claim 1, characterized in that... The plurality of first recessed patterns are spaced apart from each other in a first direction. The distance between adjacent first recessed patterns in the first direction is 0.1 μm to 10 μm, and Each of the plurality of first recessed patterns has a width of 0.1 μm to 10 μm in the first direction.

10. An electronic device, characterized in that... include: A display panel including a light-emitting area and a non-light-emitting area adjacent to the light-emitting area; A power supply configured to provide power to the display panel; An optical layer disposed on the display panel; and A window is provided on the optical layer. The display panel includes: basal layer A circuit layer disposed on the substrate layer and including transistors. A display element layer disposed on the circuit layer and including light-emitting elements, and An organic insulating layer disposed between the circuit layer and the display element layer Multiple first recessed patterns are defined on the upper surface of the organic insulating layer. The light-emitting element includes a first electrode, a second electrode disposed on the first electrode, and a light-emitting layer disposed between the first electrode and the second electrode. A portion of the first electrode is disposed within the plurality of first recessed patterns.

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