A semiconductor package structure

Abstract

The utility model relates to the technical field of semiconductor packaging, disclose a kind of semiconductor packaging structure, including first substrate, the chip board is equipped on the first substrate upper end surface, multiple pins are equipped on the two side walls of chip board, the heat conduction structure is equipped on the lower end surface of chip board, the packaging module is equipped on the upper end surface of chip board, the heat conduction structure includes heat conduction frame, the heat conduction frame is set on the lower end surface of chip board, the heat conduction frame two ends are respectively penetrated first substrate and reach the upper side wall of chip board, the upper end surface of chip board between the end of heat conduction frame is equipped with heat conduction seat, the upper end surface of heat conduction seat is equipped with multiple heat conduction columns, the heat conduction column includes first heat conduction cylinder.In the utility model, the gradient transition of heat conduction column effectively absorbs and disperses thermal stress, reduces packaging warping and solder cracking risk, realizes the more uniform temperature distribution of chip surface, avoids local hot spot, improves chip performance and life.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure. Background Technology

[0002] Semiconductors are a class of materials that lie between conductors and insulators, possessing unique electrical properties. They play a crucial role in modern electronic technology and are the core materials for manufacturing various electronic devices. Semiconductor packaging is a key link in connecting chips to external circuits, and its main purpose is to protect the chip, provide electrical connections, and achieve thermal management.

[0003] Some problems still exist in the use of existing semiconductor packaging structures. The difference in thermal expansion coefficient between different materials inside the package leads to the accumulation of thermal stress. There is a large difference in CTE between the chip and the substrate, which leads to problems such as package warping, solder joint cracking, and delamination. Therefore, those skilled in the art provide a semiconductor packaging structure to solve the problems mentioned in the background art. Utility Model Content

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a semiconductor packaging structure. The gradient transition of the heat-conducting pillars effectively absorbs and disperses thermal stress, reducing the risk of package warpage and solder joint cracking. The stress buffer design extends the package life.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a semiconductor packaging structure, comprising a first substrate, a chip plate disposed on the upper surface of the first substrate, a plurality of pins disposed on the side walls of the chip plate, a heat-conducting structure disposed on the lower surface of the chip plate, and a packaging module disposed on the upper surface of the chip plate;

[0006] The thermally conductive structure includes a thermally conductive frame, which is disposed on the lower end surface of the chip board. Both ends of the thermally conductive frame penetrate through the first substrate and extend to the upper side walls of the chip board. A thermally conductive seat is provided on the upper end surface of the chip board between the ends of the thermally conductive frame, and a plurality of thermally conductive pillars are provided on the upper end surface of the thermally conductive seat.

[0007] The heat-conducting pillar includes a first heat-conducting cylinder, a second heat-conducting cylinder is fixedly connected to the upper end face of the first heat-conducting cylinder, a third heat-conducting cylinder is fixedly connected to the upper end face of the second heat-conducting cylinder, and a fourth heat-conducting cylinder is fixedly connected to the upper end face of the third heat-conducting cylinder.

[0008] Through the above technical solutions, the gradient transition of the heat-conducting pillars effectively absorbs and disperses thermal stress, reduces the risk of package warpage and solder joint cracking, and the stress buffer design extends the package life.

[0009] Furthermore, each of the multiple heat-conducting pillars penetrates the packaging module and extends to the upper end of the packaging module, and a heat dissipation plate is provided at the end. The upper surface of the heat dissipation plate is provided with multiple through holes, and the multiple heat-conducting pillars respectively penetrate through the multiple through holes and extend to the upper end of the heat dissipation plate, and a heat-conducting plate is provided at the end.

[0010] With the above technical solution, the heat sink is located at the top of the packaging module and is used to further diffuse the heat conducted by the heat conduction pillar to the external environment. The heat conduction plate is located at the top of the heat sink and is in direct contact with the external heat sink, thereby improving the heat dissipation efficiency.

[0011] Furthermore, multiple microbumps are fixedly connected to the lower end face of the upper heat-conducting base on the chip board, and the multiple microbumps are arranged in a high density in the central region;

[0012] Through the above technical solution, multiple microbumps are distributed in an array, with a higher density in the central area and a sparser density in the edge area, in order to match the heat flow distribution of the chip.

[0013] Furthermore, the material of the plurality of microbumps is graphene solder;

[0014] Through the above technical solutions, graphene has extremely high thermal conductivity, which significantly reduces the contact thermal resistance between the chip and the substrate and improves the thermal conduction efficiency.

[0015] Furthermore, the first heat-conducting cylinder is made of chromium suboxide, the second heat-conducting cylinder is made of aluminum oxide, the third heat-conducting cylinder is made of titanium oxide, and the fourth heat-conducting cylinder is made of silicon dioxide.

[0016] Through the above technical solutions, the gradient transition effectively absorbs and disperses thermal stress, reducing the risk of package warpage and solder joint cracking.

[0017] Furthermore, the heat-conducting plate is fixedly connected to the upper end of the heat-conducting column by five screws, which are respectively located at the upper end of the heat-conducting column at the center position and at the upper ends of the heat-conducting columns at the four opposite corners.

[0018] The above technical solution effectively disperses stress from different directions, avoids stress concentration, and ensures a larger contact area between the heat-conducting plate and the heat-conducting column, thereby reducing contact thermal resistance.

[0019] This utility model has the following beneficial effects:

[0020] 1. In this utility model, the gradient transition of the heat-conducting pillars in the semiconductor packaging structure effectively absorbs and disperses thermal stress, reduces the risk of package warpage and solder joint cracking, achieves a more uniform temperature distribution on the chip surface, avoids local hot spots, improves chip performance and lifespan, and the stress buffer design extends the package lifespan.

[0021] 2. In this utility model, a high thermal conductivity graphene composite material is used, which significantly improves the interface heat conduction efficiency. The deformable micro-bump design can adapt to the deformation caused by thermal stress, avoid solder joint cracking, and the arrangement supports high-density interconnection, thereby improving the packaging integration.

[0022] 3. In this utility model, the multi-layer gradient transition layer absorbs thermal stress, and the micro-bumps further alleviate stress concentration through elastic deformation. The high toughness of the graphene composite solder, combined with the optimized elastic modulus of the gradient transition layer, improves the overall mechanical properties. Attached Figure Description

[0023] Figure 1 This is a perspective view of a semiconductor packaging structure proposed in this utility model;

[0024] Figure 2 This is a three-dimensional cross-sectional view of a semiconductor packaging structure proposed in this utility model;

[0025] Figure 3 This is a three-dimensional exploded view of a semiconductor packaging structure proposed in this utility model;

[0026] Figure 4 This is a three-dimensional exploded view of a semiconductor packaging structure proposed in this utility model from another perspective.

[0027] Legend:

[0028] 1. First substrate; 2. Pins; 3. Thermal conductive structure; 4. Chip board; 5. Packaging module;

[0029] 301. Heat-conducting plate; 302. Heat-conducting frame; 303. Heat-conducting base; 304. Heat-conducting pillar; 305. Heat sink; 306. Through hole; 307. Micro bump;

[0030] 3041, First thermally conductive cylinder; 3042, Second thermally conductive cylinder; 3043, Third thermally conductive cylinder; 3044, Fourth thermally conductive cylinder. Detailed Implementation

[0031] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0032] Reference Figures 1-4The present invention provides an embodiment of a semiconductor packaging structure, including a first substrate 1, a chip board 4 on the upper surface of the first substrate 1, a plurality of pins 2 on the two side walls of the chip board 4, a heat-conducting structure 3 on the lower surface of the chip board 4, and a packaging module 5 on the upper surface of the chip board 4.

[0033] The thermally conductive structure 3 includes a thermally conductive frame 302, which is disposed on the lower end surface of the chip board 4. Both ends of the thermally conductive frame 302 pass through the first substrate 1 and extend to the upper part of the two side walls of the chip board 4. A thermally conductive seat 303 is provided on the upper end surface of the chip board 4 between the ends of the thermally conductive frame 302. A plurality of thermally conductive pillars 304 are provided on the upper end surface of the thermally conductive seat 303.

[0034] The heat-conducting pillar 304 includes a first heat-conducting cylinder 3041, a second heat-conducting cylinder 3042 fixedly connected to the upper end face of the first heat-conducting cylinder 3041, a third heat-conducting cylinder 3043 fixedly connected to the upper end face of the second heat-conducting cylinder 3042, and a fourth heat-conducting cylinder 3044 fixedly connected to the upper end face of the third heat-conducting cylinder 3043. The gradient transition of the heat-conducting pillar 304 effectively absorbs and disperses thermal stress, reduces the risk of package warpage and solder joint cracking, and the stress buffer design extends the package life.

[0035] like Figure 2 , 3 As shown in Figure 4, multiple heat-conducting pillars 304 penetrate the packaging module 5 and extend to the upper end of the packaging module 5, with a heat sink 305 at the end. The upper surface of the heat sink 305 has multiple through holes 306. The multiple heat-conducting pillars 304 respectively penetrate the multiple through holes 306 and extend to the upper end of the heat sink 305, with a heat-conducting plate 301 at the end. The heat sink 305 is located at the upper end of the packaging module 5 and is used to further diffuse the heat conducted by the heat-conducting pillars 304 to the external environment. The heat sink 301 is located at the upper end of the heat sink 305 and is in direct contact with the external heat sink, thereby improving the heat dissipation efficiency.

[0036] Multiple microbumps 307 are fixedly connected to the lower end surface of the upper heat conduction seat 303 on the chip board 4. The multiple microbumps 307 are arranged in a high density in the central area and are distributed in an array. The density is higher in the central area and sparser in the edge area to match the heat flow distribution of the chip.

[0037] The multiple microbumps 307 are made of graphene solder. Graphene has extremely high thermal conductivity, which significantly reduces the contact thermal resistance between the chip and the substrate and improves the thermal conduction efficiency.

[0038] The first thermally conductive cylinder 3041 is made of chromium suboxide, the second thermally conductive cylinder 3042 is made of aluminum oxide, the third thermally conductive cylinder 3043 is made of titanium oxide, and the fourth thermally conductive cylinder 3044 is made of silicon dioxide. The gradient transition effectively absorbs and disperses thermal stress, reducing the risk of package warpage and solder joint cracking.

[0039] The heat-conducting plate 301 is fixedly connected to the upper end of the heat-conducting column 304 by five screws. The five screws are respectively set at the upper end of the heat-conducting column 304 at the center position and the upper ends of the heat-conducting columns 304 at the four opposite corners. The multi-point fixing method can effectively disperse the stress from different directions, avoid stress concentration, and ensure a larger contact area between the heat-conducting plate 301 and the heat-conducting column 304, thereby reducing the contact thermal resistance.

[0040] Working principle: The gradient transition of the thermal pillar 304 effectively absorbs and disperses thermal stress, reducing the risk of package warpage and solder joint cracking, achieving a more uniform temperature distribution on the chip surface, avoiding local hot spots, and improving chip performance and lifespan. The stress buffer design extends package lifespan. The microbump 307 uses a high thermal conductivity graphene composite material, significantly improving interface heat conduction efficiency. The deformable microbump 307 design can adapt to deformation caused by thermal stress, avoiding solder joint cracking. The arrangement supports high-density interconnection, improving package integration. The multi-layer gradient transition layer of the thermal pillar 304 absorbs thermal stress, and the microbump 307 further alleviates stress concentration through elastic deformation. The high toughness of the graphene composite solder, combined with the optimized elastic modulus of the gradient transition layer, improves overall mechanical properties.

[0041] Finally, it should be noted that the above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A semiconductor packaging structure, comprising a first substrate (1), characterized in that: The first substrate (1) has a chip board (4) on its upper surface, and multiple pins (2) are provided on both side walls of the chip board (4). The chip board (4) has a heat-conducting structure (3) on its lower surface and a packaging module (5) on its upper surface. The heat-conducting structure (3) includes a heat-conducting frame (302), which is disposed on the lower end surface of the chip board (4). The two ends of the heat-conducting frame (302) pass through the first substrate (1) and extend to the upper part of the two side walls of the chip board (4). A heat-conducting seat (303) is provided on the upper end surface of the chip board (4) between the ends of the heat-conducting frame (302). A plurality of heat-conducting pillars (304) are provided on the upper end surface of the heat-conducting seat (303). The heat-conducting column (304) includes a first heat-conducting cylinder (3041), a second heat-conducting cylinder (3042) is fixedly connected to the upper end face of the first heat-conducting cylinder (3041), a third heat-conducting cylinder (3043) is fixedly connected to the upper end face of the second heat-conducting cylinder (3042), and a fourth heat-conducting cylinder (3044) is fixedly connected to the upper end face of the third heat-conducting cylinder (3043).

2. The semiconductor packaging structure according to claim 1, characterized in that: The multiple heat-conducting pillars (304) all penetrate the encapsulation module (5) and extend to the upper end of the encapsulation module (5), and the ends are provided with heat dissipation plates (305). The upper surface of the heat dissipation plate (305) is provided with multiple through holes (306). The multiple heat-conducting pillars (304) respectively penetrate the multiple through holes (306) and extend to the upper end of the heat dissipation plate (305), and the ends are provided with heat-conducting plates (301).

3. A semiconductor packaging structure according to claim 1, characterized in that: Multiple micro-bumps (307) are fixedly connected to the lower end surface of the upper heat-conducting seat (303) of the chip board (4), and the multiple micro-bumps (307) are arranged in a high density in the central area.

4. A semiconductor packaging structure according to claim 3, characterized in that: The material of the multiple microbumps (307) is graphene solder.

5. A semiconductor packaging structure according to claim 1, characterized in that: The first thermally conductive cylinder (3041) is made of chromium suboxide, the second thermally conductive cylinder (3042) is made of aluminum oxide, the third thermally conductive cylinder (3043) is made of titanium oxide, and the fourth thermally conductive cylinder (3044) is made of silicon dioxide.

6. A semiconductor packaging structure according to claim 2, characterized in that: The heat-conducting plate (301) is fixedly connected to the upper end of the heat-conducting column (304) by five screws. The five screws are respectively located at the upper end of the heat-conducting column (304) at the center position and at the upper ends of the heat-conducting columns (304) at the four opposite corners.

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