Multilayer stacked chip package structure with dual wiring layers

Abstract

The utility model discloses a kind of multilayer stacked chip packaging structures with double wiring layers, including first heavy wiring layer, second heavy wiring layer, plastic package body, electrical connection component and chip unit, chip unit includes the bare crystal of sequentially stacking on first heavy wiring layer, and the functional chip fixed on first heavy wiring layer, electrical connection component includes the first lead wire of bare crystal and first heavy wiring layer electrically connected together, the first conductive column of protruding on first heavy wiring layer, the second conductive column of protruding on functional chip, plastic package body is encapsulated in its inside with chip unit and electrical connection component and exposes the top end of first, second conductive column, second heavy wiring layer is located at the top surface of plastic package body and is electrically connected with first, second conductive column.Compared with prior art, the utility model's multilayer stacked chip packaging structure is thin, and electrical connection stability is high, yield is high and cost is low.

Description

Technical Field

[0001] This utility model relates to semiconductor packaging, and more particularly to a multilayer stacked chip packaging structure. Background Technology

[0002] With the rapid pace of technological advancements in smart terminal devices, from large industrial equipment to consumer mobile terminals, integrated circuit memory chips—their core component—remain at the heart of technological evolution. In the 3D packaging process, traditional methods primarily employ wire bonding (WB) technology to achieve vertical interconnection of multi-layered chips via wires. This approach still dominates the stacking packaging of LPDDR memory and flash memory chips. It's worth noting that as mobile smart terminals evolve towards ultra-thinness and integration, this technological innovation trend and the evolution of consumer electronics product forms are driving each other: on the one hand, the demand for device miniaturization is forcing continuous breakthroughs in packaging technology; on the other hand, breakthroughs in advanced packaging technology are providing more possibilities for terminal product design. This synergistic evolution of technology and market demand is reshaping the entire electronics manufacturing industry.

[0003] Referring to Chinese patent CN119864345A, existing chip packaging, especially in dual-layer packaging structures, typically encapsulates the base chip between two redistribution layers and electrically connects it to the upper redistribution layer. Then, the functional chip is encapsulated on the side of the upper redistribution layer away from the lower redistribution layer. The functional chip and the base chip are stacked, requiring two separate encapsulation processes to form two packages, resulting in numerous packaging steps and a thick structure. Furthermore, existing technologies rely on the upper redistribution layer to electrically connect all components within the molding compound. This limits the insulating opening space on the bottom surface of the upper redistribution layer, making it highly susceptible to short circuits due to misalignment or tilting of electrical connectors within the molding compound, or excessively small gaps in the conductive patterns on the bottom surface of the upper redistribution layer.

[0004] Therefore, there is an urgent need for a multi-layer stacked chip packaging structure that can solve the above problems. Utility Model Content

[0005] The purpose of this invention is to provide a multi-layer stacked chip packaging structure with dual wiring layers, which is thin, low-cost, and has stable electrical connections.

[0006] To achieve the above objectives, this utility model provides a multi-layer stacked chip package structure with dual wiring layers, including a first wiring layer, a second wiring layer, a molding compound, electrical connection components, and chip units. The chip unit includes a plurality of bare dies stacked sequentially on the first wiring layer and a functional chip fixed on the first wiring layer. The electrical connection components include a first lead electrically connecting the bare dies and the first wiring layer, a first conductive post protruding from the first wiring layer, and a second conductive post protruding from the functional chip. The molding compound encapsulates the chip unit and the electrical connection components on the first wiring layer, with the top ends of the first and second conductive posts exposed on the top surface of the molding compound. The second wiring layer is located on the top surface of the molding compound and is electrically connected to the first and second conductive posts.

[0007] Preferably, the functional chip is a logic control chip, a sensor chip, or a SOC chip.

[0008] Preferably, the bare dies are multiple and staggered on the first wiring layer to form a fan-shaped stacked structure.

[0009] Preferably, the electrical connection component further includes a second lead electrically connected between the non-top-layer die and the functional chip.

[0010] Preferably, the first lead is electrically connected to the non-top layer die, and the electrical connection component further includes a metal bump protruding on the top layer die in the chip unit, the metal bump being exposed on the top surface of the molding compound away from the first redistribution layer, and the second redistribution layer is also electrically connected to the metal bump.

[0011] Preferably, the first and second conductive pillars comprise electroplated metal pillars. Compared to traditional vertical wire bonding technology, where mechanical misalignment during vertical wire bonding leads to reduced yield, the multilayer stacked chip packaging structure of this invention exhibits good electrical connection stability and a high yield.

[0012] Specifically, the metal pillar has a metal protective layer near the top of the second redistribution layer. This metal protective layer is a nickel layer or a nickel-gold composite layer, so that the conductive pillar has a copper-nickel composite structure or a copper-nickel-gold composite structure, thereby enhancing the oxidation resistance and welding performance of the conductive pillar.

[0013] Preferably, the second wiring layer has a conductive connection portion on the side away from the first wiring layer.

[0014] Preferably, the first wiring layer has a conductive connection portion on the side away from the second wiring layer. This solution allows both sides of the multilayer stacked chip package structure to be connected to the outside world, and multiple multilayer stacked chip package structures can be stacked and soldered together to achieve more layers of bare die stacking. When the multilayer stacked chip package structure is a memory, it can form a memory with a larger storage space.

[0015] Preferably, an insulating protective layer is formed on the side of the first and / or second wiring layers away from the molding compound. Specifically, the insulating protective layer is a polyimide layer or a silicon nitride layer.

[0016] Compared with existing technologies, in this invention, both the functional chip and the basic bare die are mounted between two redistribution layers, specifically on the first redistribution layer. This results in a thinner chip packaging unit, eliminates the need for multiple chip fixing and molding processes, and reduces manufacturing costs. Furthermore, the first and second redistribution layers of this invention handle some of the series and parallel connections within the chip unit. This allows for larger openings and gaps in the conductive patterns on the chip unit's side where the first and second redistribution layers connect, ensuring stable electrical connections and enabling higher integration density in the multi-layer stacked chip packaging structure. Attached Figure Description

[0017] Figure 1 This is a structural diagram of the multilayer stacked chip packaging structure in Embodiment 1 of this utility model.

[0018] Figure 2 This is a structural diagram of the multilayer stacked chip packaging structure in Embodiment 2 of this utility model. Detailed Implementation

[0019] To explain in detail the technical content, structural features, objectives, and effects of this utility model, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0020] Example 1: refer to Figure 1This utility model discloses a multi-layer stacked chip packaging structure with dual wiring layers, including a first wiring layer 51, a second wiring layer 52, a molding compound 40, an electrical connection component, and a chip unit 20. The chip unit 20 includes a plurality of bare dies 21 stacked sequentially on the first wiring layer 51, and a functional chip 22 fixed on the first wiring layer 51. The electrical connection component includes a first lead 31 that electrically connects the bare dies 21 and the first wiring layer 51, a first conductive post 32 protruding from the first wiring layer 51, and a second conductive post 34 protruding from the functional chip 22. The molding compound 40 encapsulates the chip unit 20 and the electrical connection component on the first wiring layer 51, and exposes the top ends of the first conductive post 32 and the second conductive post 34 on the top surface of the molding compound 40. The second wiring layer 52 is located on the top surface of the molding compound 40 and is electrically connected to the first conductive post 32 and the second conductive post 34. The functional chip 22 can be a logic control chip, a sensor chip, or a SOC chip, etc.

[0021] refer to Figure 1 Multiple bare dies 21 are stacked in a staggered manner on the first multiple wiring layer 51 to form a fan-shaped stacked structure. In this embodiment, the bare dies 21 are stacked with 4 layers. However, the bare dies 21 can also be stacked with 2, 3, 5, or even 8 layers, and are not limited to 4 layers. The bare dies 21 are memory chips. The bare dies 21 are attached to the first multiple wiring layer 51 by a DAF film, and multiple bare dies 21 are sequentially attached and fixed together by the DAF film. The multiple bare dies 21 can be stacked in a staggered manner in one direction or in different directions.

[0022] refer to Figure 1 The second redistribution layer 52 has a second conductive connection portion 61 on the side away from the molding compound 40. The second conductive connection portion 61 is a pad formed by metal bumps or metal dots. Solder balls can be provided on the second conductive connection portion 61 for electrical connection to the outside.

[0023] For the better option, refer to Figure 1 The first wiring layer 51, on the side away from the molding compound 40, is further supported by a silicon plate. This silicon plate is a silicon plate without conductive vias, which can effectively support the multilayer stacked chip package structure, improve the stability of the multilayer stacked chip package structure, and does not affect the heat dissipation of the multilayer stacked chip package structure. The thickness of the silicon plate is greater than 40 μm.

[0024] refer to Figure 1The electrical connection component further includes a second lead 35 electrically connecting the non-top-layer die 21 and the functional chip 22. The first lead 31 and the second lead 35 are conductive metal wires such as gold, silver, or copper. The arc height of the first lead 31 needs to be greater than or equal to the stacking spacing between the dies 21 to avoid the lower die 21 during wire bonding of the stacked dies. The highest point of the arc of the second lead 35 does not exceed the top of the stacked structure formed by multiple dies 21 to prevent accidental short circuits caused by accidental contact with the second redistribution layer 52 during its formation. In this embodiment, the arc height of the first lead 31 is greater than or equal to 100 μm.

[0025] In this embodiment, the bare die 21 is electrically connected together by making a first lead 31 between the bare die 21 and the first redistribution layer 51. Of course, alternatively, the bare dies 21 can also be electrically connected together by making leads between the bare dies 21.

[0026] In this embodiment, the non-top-layer die 21 leads the electrical signal to the first redistribution layer 51 through the first lead 31. After being connected in series and parallel through the first redistribution layer 51, the signal is led to the second redistribution layer 52 through the first conductive post 32. The top-layer die 21 guides the electrical signal to the second redistribution layer 52 through the metal bump 33. The electrical signal of the functional chip 22 is electrically connected to a die 21 through the second lead 35 and is also led to the second redistribution layer through the second conductive post 34. The second redistribution layer connects the electrical signals of the die 21 and the functional chip 22 in series and parallel and leads them to the second conductive connection portion 61, and then leads them out through the solder balls (not shown in the figure) on the second conductive connection portion 61.

[0027] refer to Figure 1 The first lead 31 is electrically connected to the non-top-layer bare die 21. The electrical connection assembly also includes a metal bump 33 on the electrode of the top-layer bare die 21 in the chip unit 20. The metal bump 33 is exposed on the top surface of the molding compound 40 away from the first redistribution layer 51. The second redistribution layer 52 has a conductive layer adjacent to the bottom surface of the molding compound 40 that contacts and is electrically connected to the metal bump 33. This conductive layer is also electrically connected to the first redistribution layer 51 and the functional chip 22 through a first conductive post 32 and a second conductive post 34. The metal bump 33 can be a bump made using bump fabrication technology or an implanted gold ball, etc.

[0028] The first conductive pillar 32 and the second conductive pillar 34 include electroplated metal pillars 320. These metal pillars 320 can be copper, titanium, or the like.

[0029] Among them, a metal transition layer 321 is also provided at the bottom end of the metal post 320 of the first conductive post 32. The metal transition layer 321 is sandwiched between the conductive post 32 and the first redistribution layer 51. The metal transition layer 321 is a Ti / Cu transition layer or a TiW / Cu transition layer, and the thickness of the metal transition layer is 50-200nm, which makes the adhesion between the metal post 320 and the first redistribution layer 51 better.

[0030] Specifically, the metal pillars 320 of the first conductive pillar 32 and the second conductive pillar 34 have a metal protective layer 322 near the top of the second redistribution layer 52. The metal protective layer 322 is a nickel layer or a nickel-gold composite layer, so that the conductive pillar 32 is a copper-nickel composite structure or a copper-nickel-gold composite structure, thereby enhancing the oxidation resistance and welding performance of the first conductive pillar 32 and the second conductive pillar 34.

[0031] Example 2: refer to Figure 2 Unlike Embodiment 1, in this embodiment, the side of the first redistribution layer 51 away from the molding compound 40 does not have a silicon substrate 10, but instead has a first conductive connection portion 62. The first conductive connection portion 62 is a pad formed by metal bumps or metal dots, and solder balls can be placed on the first conductive connection portion 62 for electrical connection with the outside.

[0032] The first conductive connection portion 62 on the first wiring layer 51 and the second conductive connection portion 61 on the second wiring layer 52 are positioned correspondingly, allowing multiple multilayer stacked chip package structures to be stacked together sequentially. In adjacent multilayer stacked chip package structures, the second conductive connection portion 61 of the next multilayer stacked chip package structure and the first conductive connection portion 62 of the previous multilayer stacked chip package structure are soldered together. When the multilayer stacked chip package structure is a storage multilayer stacked chip package structure (the bare die 21 is a memory chip), multiple multilayer stacked chip package structures form a larger capacity memory cell.

[0033] Preferably, an insulating protective layer (not shown) is formed on the side of the first rewiring layer 51 and / or the second rewiring layer 52 away from the molding compound 40. Specifically, the insulating protective layer is a polyimide layer or a silicon nitride layer.

[0034] Compared with the prior art, on the one hand, this invention uses conductive pillars (first conductive pillar 32 and second conductive pillar 34) instead of vertical wire bonding leads to connect the second redistribution layer 52, reducing the risk of yield loss in subsequent processes caused by mechanical misalignment of vertical leads in multi-layer stacked chip packaging structures. On the other hand, this invention uses second leads 35 to electrically connect the bare die 21 and the functional chip 22 together, eliminating the need for redistribution layer transfer, resulting in high connection stability. Combined with the second conductive pillar 34 to extract the electrical signals of the functional chip 22, the signal extraction path is effectively optimized, reducing signal interference. On the other hand, the first wiring layer 51 of this utility model is electrically connected to most of the bare dies 21 through the first lead 31. Then, the electrical signals of the bare dies 21 are regulated and led out to the second wiring layer 52 through the first conductive post 32. The second wiring layer 52 does not need to handle the series and parallel connection of most of the bare dies 21. It only needs to handle the second conductive post 34 led out from the top bare die 21 and the functional chip 33, as well as the electrical signals led out to the first conductive post 32 after being processed by the first wiring layer 51. This allows the openings and gaps in the conductive patterns on the side where the first wiring layer 51 and the second wiring layer 52 connect to the chip unit 20 to be made larger, ensuring the stability of the electrical connection. It also allows for a higher integration density of the multi-layer stacked chip package structure, effectively improving the integration density and reliability of the multi-layer stacked chip package structure.

[0035] The above-disclosed embodiments are merely preferred embodiments of the present utility model and should not be construed as limiting the scope of the present utility model. Therefore, any equivalent variations made in accordance with the scope of the present utility model shall still fall within the scope of the present utility model.

Claims

1. A multilayer stacked chip package structure with dual wiring layers, characterized in that: The device includes a first wiring layer, a second wiring layer, a molding compound, electrical connection components, and a chip unit. The chip unit includes a plurality of bare dies stacked sequentially on the first wiring layer and a functional chip fixed on the first wiring layer. The electrical connection components include a first lead electrically connecting the bare dies and the first wiring layer, a first conductive post protruding from the first wiring layer, and a second conductive post protruding from the functional chip. The molding compound encapsulates the chip unit and the electrical connection components on the first wiring layer, with the tops of the first and second conductive posts exposed on the top surface of the molding compound. The second wiring layer is located on the top surface of the molding compound and is electrically connected to the first and second conductive posts.

2. The multilayer stacked chip packaging structure as described in claim 1, characterized in that: The functional chip is a logic control chip, a sensor chip, or a SOC chip.

3. The multilayer stacked chip packaging structure as described in claim 1, characterized in that: The bare dies are multiple and staggered on the first wiring layer to form a fan-shaped stacked structure.

4. The multilayer stacked chip packaging structure as described in claim 1, characterized in that: The electrical connection assembly also includes a second lead electrically connecting the non-top-layer die and the functional chip.

5. The multilayer stacked chip packaging structure as described in claim 1, characterized in that: The first lead is electrically connected to the non-top layer bare die. The electrical connection component also includes a metal bump protruding on the top layer bare die in the chip unit. The metal bump is exposed on the top surface of the molding compound away from the first redistribution layer. The second redistribution layer is also electrically connected to the metal bump.

6. The multilayer stacked chip packaging structure as described in claim 1, characterized in that: The first and second conductive pillars comprise electroplated metal pillars.

7. The multilayer stacked chip packaging structure as described in claim 6, characterized in that: The metal pillar has a metal protective layer near the top of the second redistribution layer, which is a nickel layer or a nickel-gold composite layer.

8. The multilayer stacked chip packaging structure as described in claim 1, characterized in that: The second wiring layer has a conductive connection on the side away from the first wiring layer.

9. The multilayer stacked chip packaging structure as described in claim 1 or 8, characterized in that: The first wiring layer has a conductive connection on the side away from the second wiring layer.

10. The multilayer stacked chip packaging structure as described in claim 1, characterized in that: An insulating protective layer is formed on the side of the first and / or second wiring layers away from the encapsulation.

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