Double-sided heat dissipating power module with multi-chip parallel arrangement

Abstract

The utility model relates to double -sided heat dissipation power module of multi -chip parallel arrangement, including substrate assembly, chip component, metal connecting assembly, bonding wire and terminal, wherein substrate assembly includes first base plate and second base plate, and first base plate and second base plate set up metal connecting assembly and chip component in height direction, chip component is connected with first base plate upper surface, and metal connecting assembly is connected with chip component, second base plate lower surface, wherein chip component contains at least 20 chip monomer, terminal and first base plate upper surface are connected, and stretch out from both ends, wherein first terminal and second terminal are along the height direction laminated setting, effectively reduce circulation area, with reduce parasitic inductance, and then reduce switching energy loss, further improve module thermal performance.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor power device technology, and in particular to a double-sided heat dissipation power module with multiple chips arranged in parallel. Background Technology

[0002] Power modules are power electronic devices widely used in various power equipment, such as communication equipment, electric vehicles, and power supply equipment. Their basic principle is to use high-frequency switching to control the power supply, thereby controlling voltage and current. However, traditional silicon-based power modules are increasingly unable to meet the demands of high-power applications for high temperature and high power density. In contrast, SiC power modules, due to their low switching losses, high switching speed, and high-temperature resistance, can significantly improve efficiency and reduce energy consumption, contributing to system miniaturization, high efficiency, and low weight.

[0003] SiC power modules typically employ a multi-chip parallel configuration to meet high-power applications. Wire bonding is commonly used to achieve electrical connections between chips and between chips and the substrate, which introduces significant parasitic parameters, such as parasitic inductance. These large parasitic parameters can lead to reliability issues during module operation, such as voltage overshoot and voltage oscillation. Furthermore, the uneven distribution of stray inductance in the multi-chip parallel module layout can cause current sharing problems, significantly limiting the high-frequency performance of SiC modules. In addition, in traditional packaging, single-sided substrate heat dissipation cannot simultaneously meet the requirements of high power density and high heat dissipation capacity. At high temperatures, the module's performance and reliability degrade, thus affecting system lifespan. In contrast, double-sided heat dissipation modules provide two heat dissipation paths for the SiC chips, improving both power electrical and thermal performance. Utility Model Content

[0004] The purpose of this utility model patent is to provide a double-sided heat dissipation power module with multiple chips arranged in parallel, including a substrate assembly (1), a chip assembly (2), a metal connection assembly (3), bonding wires (4), and terminals (5); wherein,

[0005] The substrate assembly (1) includes a first substrate (11) and a second substrate (12). The first substrate (11) and the second substrate (12) are provided with the metal connection assembly (3) and the chip assembly (2) in the height direction. The first substrate (11) includes a first conductive layer (111), a first ceramic layer (112), and a first heat dissipation layer (113). The first conductive layer (111) is used to connect with the chip assembly (2) and form a circuit between the first substrate (11) and the second substrate (12). The first heat dissipation layer (113) is used to connect a copper base plate or a first heat sink (56). The second substrate (12) includes a second conductive layer (121), a second ceramic layer (122), and a second heat dissipation layer (123). The second conductive layer (121) is connected to the chip assembly (2) through the metal connection assembly (3) to form a circuit. The second heat dissipation layer (123) is used to connect a second heat sink (57).

[0006] The chip assembly (2) is disposed on the upper surface of the first substrate (11) and includes multiple parallel upper bridge arm chips (21) and multiple parallel lower bridge arm chips (22). The upper bridge arm chips (21) are arranged in parallel on one side of the first substrate (11); the lower bridge arm chips (22) are arranged in parallel on the other side of the first substrate (11) corresponding to the upper bridge arm chips (21), so that the chip assembly is arranged in parallel and mirror symmetrical distribution.

[0007] The metal connection components (3) are all disposed between the first substrate (11) and the second substrate (12) for connecting the second substrate (12) with the source stage of the chip assembly (2), the upper surface of the first substrate (11) and the lower surface of the second substrate (12);

[0008] The terminal (5) includes a positive terminal (51), a negative terminal (52), an AC terminal (53), a gate control terminal (54), and a Kelvin source control terminal (55), all of which are laid on the upper surface of the first substrate (11).

[0009] Specifically, the first conductive layer (111) is divided into a first power circuit region (1111), a Kelvin source circuit region (1112), a gate circuit region (1113), and an NTC placement region (1114). The first power circuit region (1111), the Kelvin source circuit region (1112), the gate circuit region (1113), and the NTC placement region (1114) are divided into multiple independent circuits. The second conductive layer (121) contains multiple second power circuit regions (1211), and the second power circuit regions (1211) are divided into multiple independent circuits (1211-A~1211-F).

[0010] Specifically, the terminals include a positive terminal (51), a negative terminal (52), an AC terminal (53), two gate control terminals (54), and two Kelvin source control terminals (55), wherein,

[0011] The positive terminal (51) and the negative terminal (52) are respectively connected to the first conductive layer 111 on the first substrate 111 to form a circuit; the positive terminal (51) and the negative terminal (52) are arranged at intervals along the height; the positive terminal (51) and the negative terminal (52) have a partial area overlap when projected onto the first substrate (11).

[0012] The AC terminal (53) is connected to the first conductive layer (111) on the upper surface of the first substrate (11), extends from the side of the first substrate (11), and is on the other side corresponding to the positive terminal (51) and the negative terminal (52);

[0013] Two gate control terminals (54) are respectively connected to the gate circuit region (1113) on the first substrate (11).

[0014] Two Kelvin source control terminals (55) are respectively connected to the Kelvin source circuit region (1112) on the first substrate (11), and each gate control terminal (54) and each Kelvin source control terminal (55) are arranged in parallel and close to each other, and extend from the opposite long edge of the first substrate (11) along the height direction.

[0015] Specifically, the upper bridge arm chip (21) includes parallel MOS transistor chips (M1~M10), and the lower bridge arm chip (22) includes parallel MOS transistor chips (M11~M20), wherein,

[0016] The positive terminal of the chip assembly is simultaneously led out from the drain of the MOS transistor chip (M1~M10);

[0017] The AC terminals of the chip assembly are simultaneously led out from the source of the MOS transistor chip (M1~M10) and the drain of the MOS transistor chip (M11~M20);

[0018] The negative terminal of the chip assembly is simultaneously led out from the source of the MOS transistor chip (M11~M20).

[0019] Furthermore, the bonding wire (4) is used to connect the gate of the chip assembly (2) and the gate circuit region (1113) on the upper surface of the first substrate (11), and the Kelvin source of the chip assembly (2) and the Kelvin source circuit region (1112) on the upper surface of the first substrate.

[0020] Specifically, the metal connection assembly (3) includes a chip connection block (31) and a substrate connection block (32), wherein

[0021] The chip connection block (31) connects the first conductive layer (111) of the first substrate (11) to the source electrode on the upper surface of the chip assembly (2) in the height direction;

[0022] The substrate connecting block (32) connects the first conductive layer (111) on the first substrate (11) and the second conductive layer (121) on the second substrate (12) in the height direction.

[0023] Furthermore, the thickness of the chip connector block (31) is less than that of the substrate connector block (32).

[0024] Specifically, the two gate control terminals (54) include a first gate control terminal (541) and a second gate control terminal (542) disposed on the first substrate (11), wherein the first gate control terminal (541) corresponds to the gate of the MOS transistor chip (M1~M10) and the second gate control terminal (542) corresponds to the MOS die (M11~M20).

[0025] The two Kelvin source control terminals (55) include a first Kelvin source control terminal (551) and a second Kelvin source control terminal (552) disposed on the first substrate (11), wherein the first Kelvin source control terminal (551) corresponds to the Kelvin source of the MOS transistor chip (M1~M10), and the second Kelvin source control terminal (552) corresponds to the MOS transistor chip (M11~M20).

[0026] The first gate control terminal (541) and the first Kelvin source control terminal (551) are designed to be parallel and adjacent to each other, extending from the opposite long edge of the first substrate (11) along the height direction;

[0027] The second gate control terminal (542) and the second Kelvin source control terminal (552) are designed to be parallel and adjacent to each other, extending from the opposite long edge of the first substrate (11) along the height direction.

[0028] Compared with the prior art, the multi-chip parallel arrangement double-sided heat dissipation power module of this utility model has the following advantages:

[0029] (1) By symmetrically and uniformly arranging multiple SiCMOSFET power chips on the upper and lower opposite substrates, combined with the first substrate, the second substrate, the metal connection components, and the terminal layout design, the mutual inductance between adjacent parallel circulating circuits of the power module cancels out, which greatly reduces the parasitic inductance of the power module and reduces the heat loss of the module.

[0030] (2) At the same time, the heat dissipation path is increased on the first substrate and the second substrate that are opposite each other, and the heat dissipation capacity of the module is improved;

[0031] (3) Further multi-chip symmetrical arrangement design reduces module size and weight, and improves power density. Attached Figure Description

[0032] Figure 1 This is an internal schematic diagram of the double-sided heat dissipation power module with multiple chips arranged in parallel according to Example 1.

[0033] Figure 2 This is a schematic diagram of the structure on the first substrate in Example 1;

[0034] Figure 3 This is a schematic diagram of the structure on the second substrate in Example 1;

[0035] Figure 4 This is a schematic diagram of the chip and terminal connection in Example 1;

[0036] Figure 5 This is a schematic diagram of the circuit distribution of the first conductive layer in Example 1;

[0037] Figure 6 This is a schematic diagram of adjacent circulating loops in Example 1;

[0038] Figure 7 This is an external schematic diagram of the double-sided heat dissipation power module with multiple chips arranged in parallel, as shown in Example 1.

[0039] Figure 8 This is an exploded view of the multi-chip parallel arrangement double-sided heat dissipation power module of Embodiment 1. Detailed Implementation

[0040] The specific embodiments of this utility model patent will be further described in detail below with reference to the accompanying drawings.

[0041] Example 1

[0042] like Figure 1 , Figure 7 and Figure 8 As shown, the double-sided heat dissipation power module with multiple chips arranged in parallel includes a substrate assembly 1, a chip assembly 2, a metal connection assembly 3, a bonding wire 4, and a terminal 5.

[0043] The substrate assembly 1 includes a first substrate 111 and a second substrate 12, wherein the first substrate 111 and the second substrate 12 are provided with a metal connection assembly 3 and a chip assembly 2 in the height direction.

[0044] The first substrate 111 includes a first conductive layer 111, a first ceramic layer 112, and a first heat dissipation layer 113. The first conductive layer 111 is used to connect with the chip assembly 2 and form a circuit between the first substrate 111 and the second substrate 12. The first heat dissipation layer 113 is used to connect a copper base plate or a first heat sink 56.

[0045] like Figure 2 As shown, the second substrate 12 includes a second conductive layer 121, a second ceramic layer 122, and a second heat dissipation layer 123. The second conductive layer 121 is connected to the chip assembly 2 through a metal connection assembly 3 to form a circuit. The second heat dissipation layer 123 is used to connect the second heat sink 57.

[0046] By using the first and second substrates that are positioned vertically opposite each other, a heat dissipation path is added, thus improving the module's heat dissipation capability.

[0047] The chip assembly 2 is disposed on the upper surface of the first substrate 11 and includes multiple parallel upper bridge arm chips 21 and multiple parallel lower bridge arm chips 22. The upper bridge arm chips 21 are arranged in parallel on one side of the first substrate 111; the lower bridge arm chips 22 are arranged in parallel on the other side of the first substrate 111 corresponding to the upper bridge arm chips 21, so that the chip assembly is arranged in parallel and mirror symmetrical distribution to reduce loop noise.

[0048] The metal connection components 3 are all disposed between the first substrate 111 and the second substrate 12, and are used to connect the second substrate 12 with the source stage of the chip assembly 2, the upper surface of the first substrate 111 and the lower surface of the second substrate 12.

[0049] The terminal 5 includes a positive terminal 51, a negative terminal 52, an AC terminal 53, a gate control terminal 54, and a Kelvin source control terminal 55, all of which are laid on the upper surface of the first substrate 111.

[0050] In this embodiment, the first conductive layer 111 is divided into a first power circuit region 1111, a Kelvin source circuit region 1112, a gate circuit region 1113, and an NTC placement region 1114. The first power circuit region 1111, Kelvin source circuit region 1112, gate circuit region 1113, and NTC placement region 1114 are further divided into multiple independent circuits. The second conductive layer 121 includes multiple second power circuit regions 1211, which are further divided into multiple independent circuits 1211-A to 1211-F, such as... Figure 6 The red lines represent different independent circuits that need to form a loop.

[0051] In this embodiment, the terminals include a positive terminal 51, a negative terminal 52, an AC terminal 53, two gate control terminals 54, and two Kelvin source control terminals 55.

[0052] The positive terminal 51 and the negative terminal 52 are respectively connected to the first conductive layer 111 on the first substrate 111 to form a circuit; the positive terminal 51 and the negative terminal 52 are spaced apart along the height; the positive terminal 51 and the negative terminal 52 have partial area overlap when projected onto the first substrate 111, and the area overlap reduces the stray inductance of the module.

[0053] The AC terminal 53 is connected to the first conductive layer 111 on the upper surface of the first substrate 111, extends from the side of the first substrate 111, and is on the other side corresponding to the positive terminal 51 and the negative terminal 52.

[0054] Two gate control terminals 54 are respectively connected to the gate circuit region 1113 on the first substrate 111;

[0055] Two Kelvin source control terminals 55 are respectively connected to the Kelvin source circuit region 1112 on the first substrate 111, and each gate control terminal 54 and each Kelvin source control terminal 55 are arranged in parallel and close to each other, and extend from the opposite long edge of the first substrate 111 along the height direction.

[0056] Specifically, in this embodiment, the upper bridge arm chip 21 includes parallel MOS transistor chips M1~M10, and the lower bridge arm chip 22 includes parallel MOS transistor chips M11~M20, wherein...

[0057] The positive terminal of the chip assembly is simultaneously led out from the drain of the MOS transistor chips M1~M10;

[0058] The AC terminals of the chip assembly are simultaneously led out from the source of the MOS transistor chips M1~M10 and the drain of the MOS transistor chips M11~M20;

[0059] The negative terminal of the chip assembly is simultaneously led out from the source of the MOS transistor chips M11~M20.

[0060] Specifically, in this embodiment, the bonding wire 4 is used to connect the gate of the chip assembly 2 and the gate circuit region 1113 on the upper surface of the first substrate 111, as well as the Kelvin source of the chip assembly 2 and the Kelvin source circuit region 1112 on the upper surface of the first substrate.

[0061] In this embodiment, the metal connection component 3 includes a chip connection block 31 and a substrate connection block 32, wherein

[0062] The chip connection block 31 connects the first conductive layer 111 of the first substrate 111 to the source electrode on the upper surface of the chip assembly 2 in the height direction;

[0063] The substrate connecting block 32 connects the first conductive layer 111 on the first substrate 111 and the second conductive layer 121 on the second substrate 12 in the height direction.

[0064] In this embodiment, the thickness of the chip connector block 31 is less than that of the substrate connector block 32. Both connector blocks 31 and 32 are metal blocks made of Cu or molybdenum copper. The thickness of the connector block placed on the chip is definitely lower than that placed directly on the substrate, and the chip is also placed on the substrate.

[0065] In this embodiment, as Figure 4 As shown, the two gate control terminals 54 include a first gate control terminal 541 and a second gate control terminal 542 disposed on the first substrate 11, wherein the first gate control terminal 541 corresponds to the gate of the MOS transistor chip M1~M10, and the second gate control terminal 542 corresponds to the MOS dies M11~M20.

[0066] The two Kelvin source control terminals 55 include a first Kelvin source control terminal 551 and a second Kelvin source control terminal 552 disposed on the first substrate 111, wherein the first Kelvin source control terminal 551 corresponds to the Kelvin source of the MOS transistor chips M1~M10, and the second Kelvin source control terminal 552 corresponds to the MOS transistor chips M11~M20;

[0067] The first gate control terminal 541 and the first Kelvin source control terminal 551 are designed to be parallel and close to each other (the two are close to each other), and extend from the opposite long side edge of the first substrate 111 along the height direction.

[0068] The second gate control terminal 542 and the second Kelvin source control terminal 552 are designed to be parallel and adjacent to each other, extending from the opposite long edge of the first substrate 111 along the height direction.

[0069] The working principle of this application relates to a double-sided heat dissipation power module with multiple chips arranged in parallel, including a substrate assembly, a chip assembly, a metal connection assembly, bonding wires, and terminals. The substrate assembly includes a first substrate and a second substrate, with the metal connection assembly and the chip assembly disposed on the first substrate and the second substrate in the height direction. The chip assembly is connected to the upper surface of the first substrate, and the metal connection assembly is connected to the chip assembly and the lower surface of the second substrate. The chip assembly contains at least 20 individual chips. The terminals are connected to the upper surface of the first substrate and extend from both ends. The first terminal and the second terminal are stacked along the height direction, which effectively reduces the circulating current area and parasitic inductance, thereby reducing switching energy loss and further improving the thermal performance of the module.

Claims

1. A double-sided heat dissipation power module with multiple chips arranged in parallel, characterized in that, It includes a substrate assembly (1), a chip assembly (2), a metal connection assembly (3), bonding wires (4), and terminals (5); wherein, The substrate assembly (1) includes a first substrate (11) and a second substrate (12). The first substrate (11) and the second substrate (12) are provided with the metal connection assembly (3) and the chip assembly (2) in the height direction. The first substrate (11) includes a first conductive layer (111), a first ceramic layer (112), and a first heat dissipation layer (113). The first conductive layer (111) is used to connect with the chip assembly (2) and form a circuit between the first substrate (11) and the second substrate (12). The first heat dissipation layer (113) is used to connect a copper base plate or a first heat sink (56). The second substrate (12) includes a second conductive layer (121), a second ceramic layer (122), and a second heat dissipation layer (123). The second conductive layer (121) is connected to the chip assembly (2) through the metal connection assembly (3) to form a circuit. The second heat dissipation layer (123) is used to connect a second heat sink (57). The chip assembly (2) is disposed on the upper surface of the first substrate (11) and includes multiple parallel upper bridge arm chips (21) and multiple parallel lower bridge arm chips (22). The upper bridge arm chips (21) are arranged in parallel on one side of the first substrate (11); the lower bridge arm chips (22) are arranged in parallel on the other side of the first substrate (11) corresponding to the upper bridge arm chips (21), so that the chip assembly is arranged in parallel and mirror symmetrical distribution. The metal connection components (3) are all disposed between the first substrate (11) and the second substrate (12) for connecting the second substrate (12) with the source stage of the chip assembly (2), the upper surface of the first substrate (11) and the lower surface of the second substrate (12); The terminal (5) includes a positive terminal (51), a negative terminal (52), an AC terminal (53), a gate control terminal (54), and a Kelvin source control terminal (55), all of which are laid on the upper surface of the first substrate (11).

2. The multi-chip parallel arrangement double-sided heat dissipation power module as described in claim 1, characterized in that, The first conductive layer (111) is divided into a first power circuit region (1111), a Kelvin source circuit region (1112), a gate circuit region (1113), and an NTC placement region (1114). The first power circuit region (1111), the Kelvin source circuit region (1112), the gate circuit region (1113), and the NTC placement region (1114) are divided into multiple independent circuits. The second conductive layer (121) contains multiple second power circuit regions (1211). The second power circuit regions (1211) are divided into multiple independent circuits (1211-A~1211-F).

3. The multi-chip parallel arrangement double-sided heat dissipation power module as described in claim 2, characterized in that, The terminals include a positive terminal (51), a negative terminal (52), an AC terminal (53), two gate control terminals (54), and two Kelvin source control terminals (55), wherein, The positive terminal (51) and the negative terminal (52) are respectively connected to the first conductive layer (111) on the first substrate (11) to form a circuit; the positive terminal (51) and the negative terminal (52) are arranged at intervals along the height; the positive terminal (51) and the negative terminal (52) have a partial area overlap when projected onto the first substrate (11). The AC terminal (53) is connected to the first conductive layer (111) on the upper surface of the first substrate (11), extends from the side of the first substrate (11), and is on the other side corresponding to the positive terminal (51) and the negative terminal (52); Two gate control terminals (54) are respectively connected to the gate circuit region (1113) on the first substrate (11). Two Kelvin source control terminals (55) are respectively connected to the Kelvin source circuit region (1112) on the first substrate (11), and each gate control terminal (54) and each Kelvin source control terminal (55) are arranged in parallel and close to each other, and extend from the opposite long edge of the first substrate (11) along the height direction.

4. The multi-chip parallel arrangement double-sided heat dissipation power module as described in claim 3, characterized in that, The upper bridge arm chip (21) includes parallel MOS transistor chips (M1~M10), and the lower bridge arm chip (22) includes parallel MOS transistor chips (M11~M20), wherein, The positive terminal of the chip assembly is simultaneously led out from the drain of the MOS transistor chip (M1~M10); The AC terminals of the chip assembly are simultaneously led out from the source of the MOS transistor chip (M1~M10) and the drain of the MOS transistor chip (M11~M20); The negative terminal of the chip assembly is simultaneously led out from the source of the MOS transistor chip (M11~M20).

5. The multi-chip parallel arrangement double-sided heat dissipation power module as described in claim 2, characterized in that, The bonding wire (4) is used to connect the gate of the chip assembly (2) and the gate circuit region (1113) on the upper surface of the first substrate (11), as well as the Kelvin source of the chip assembly (2) and the Kelvin source circuit region (1112) on the upper surface of the first substrate.

6. The multi-chip parallel arrangement double-sided heat dissipation power module as described in claim 1, characterized in that, The metal connection assembly (3) includes a chip connection block (31) and a substrate connection block (32), wherein The chip connection block (31) connects the first conductive layer (111) of the first substrate (11) to the source electrode on the upper surface of the chip assembly (2) in the height direction; The substrate connecting block (32) connects the first conductive layer (111) on the first substrate (11) and the second conductive layer (121) on the second substrate (12) in the height direction.

7. The multi-chip parallel arrangement double-sided heat dissipation power module as described in claim 6, characterized in that, The thickness of the chip connector block (31) is less than that of the substrate connector block (32).

8. The multi-chip parallel arrangement double-sided heat dissipation power module as described in claim 4, characterized in that, The two gate control terminals (54) include a first gate control terminal (541) and a second gate control terminal (542) disposed on the first substrate (11), wherein the first gate control terminal (541) corresponds to the gate of the MOS transistor chip (M1~M10) and the second gate control terminal (542) corresponds to the MOS die (M11~M20). The two Kelvin source control terminals (55) include a first Kelvin source control terminal (551) and a second Kelvin source control terminal (552) disposed on the first substrate (11), wherein the first Kelvin source control terminal (551) corresponds to the Kelvin source of the MOS transistor chip (M1~M10), and the second Kelvin source control terminal (552) corresponds to the MOS transistor chip (M11~M20). The first gate control terminal (541) and the first Kelvin source control terminal (551) are designed to be parallel and adjacent to each other, extending from the opposite long edge of the first substrate (11) along the height direction; The second gate control terminal (542) and the second Kelvin source control terminal (552) are designed to be parallel and adjacent to each other, extending from the opposite long edge of the first substrate (11) along the height direction.

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