A temperature cycle resistant stepped metal silicon carbide power chip and assembly

Abstract

The utility model provides a kind of temperature cycle resistant ladder metal silicon carbide power chip and assembly, it is related to silicon carbide power chip technical field.The chip successively includes from bottom to top: silicon carbide substrate layer, silicon carbide epitaxial layer and metal electrode layer;Metal electrode layer includes multiple mutually isolated metal electrodes;The thickness of metal electrode edge gradually decreases along the direction away from metal electrode center;Metal electrode layer is covered with dielectric layer;Dielectric layer covers each metal electrode, and the silicon carbide epitaxial layer exposed between metal electrode;Polyimide film layer is covered above dielectric layer.The utility model can gradually change by setting metal electrode as edge thickness, gently transition electrode and the height difference of peripheral area, avoid forming abrupt step, reduce the risk of dielectric layer cracking, reduce the possibility of water vapor invading chip interior through crack, finally improve the long-term working reliability of silicon carbide power chip.

Description

Technical Field

[0001] This utility model relates to the field of silicon carbide power chip technology, and in particular to a silicon carbide power chip and component with temperature-resistant cycling stepped metal. Background Technology

[0002] Silicon carbide power devices are an important branch of power electronic devices. They are power electronic devices based on silicon carbide materials and specifically optimized for high-power and high-voltage scenarios. With the continuous development of power electronic devices, they are facing an increasing demand for high reliability, mainly due to the following reasons: (1) The power electronics field is constantly facing the demand for increased power density, which usually represents the power control capability per unit volume. This demand leads to an increase in the current density of power chips and the packaging density of power modules, resulting in higher temperatures and temperature gradients during packaging. (2) New application areas define harsher environments for power packaging, such as the hybrid traction system of automobiles, where the cooling system for power electronic devices is an internal combustion engine cooling system with a coolant temperature as high as 120°C. This demand broadens the operating temperature range, with the highest temperature from T j =150℃ increased to T j =175℃, even T j =200℃.

[0003] Temperature cycling testing is a core method for verifying the structural integrity, electrical performance stability, and long-term reliability of silicon carbide power devices under drastic temperature fluctuations. Water vapor is typically introduced during temperature cycling testing to simulate a humid and high-temperature environment. The polyimide and dielectric layers covering the top of the silicon carbide power device can block some water vapor intrusion. However, the surface of a silicon carbide power chip is not flat. For example, the metal electrodes of high-power devices are usually thick, forming significant steps on the surface of the silicon carbide power chip. The dielectric layer at these metal electrode steps experiences high stress due to the change in step height, making it highly susceptible to fracture. Water vapor that penetrates the polyimide can then enter the internal structure of the chip through these fractures, reducing the reliability of the silicon carbide power chip. Utility Model Content

[0004] This invention provides a silicon carbide power chip and component with a temperature cycling stepped metal to solve the problem that the dielectric layer on the surface of the silicon carbide power chip is prone to breakage and has low reliability during temperature cycling tests.

[0005] In a first aspect, this utility model provides a silicon carbide power chip with a temperature-resistant, cycle-resistant stepped metal, comprising, from bottom to top: a silicon carbide substrate layer, a silicon carbide epitaxial layer, and a metal electrode layer; the metal electrode layer includes a plurality of mutually isolated metal electrodes; the thickness of the metal electrode edges gradually decreases in the direction away from the center of the metal electrodes; a dielectric layer is covered on the metal electrode layer; the dielectric layer covers each metal electrode and the silicon carbide epitaxial layer exposed between the metal electrodes; a polyimide thin film layer is covered on the dielectric layer.

[0006] In one possible implementation, the longitudinal cross-sectional shape of the edge of the metal electrode is stepped.

[0007] In one possible implementation, the metal electrode comprises multiple layers of metal; the lateral dimension of each metal layer decreases progressively from bottom to top.

[0008] In one possible implementation, the material of the metal electrode includes titanium nickel, titanium nitride tungsten molybdenum, or aluminum copper silver.

[0009] In one possible implementation, the dielectric layer includes a first dielectric layer and a second dielectric layer; the first dielectric layer fills the space between the metal electrodes; the thickness of the first dielectric layer is the same as the thickness of the metal electrodes; and the second dielectric layer covers the metal electrodes and the first dielectric layer.

[0010] In one possible implementation, the density of the second dielectric layer is greater than the density of the first dielectric layer.

[0011] In one possible implementation, the thickness of the metal electrode ranges from 3 micrometers to 6 micrometers.

[0012] In one possible implementation, the silicon carbide substrate is n-type doped 4H-SiC.

[0013] In one possible implementation, the thickness of the polyimide film layer ranges from 4 micrometers to 10 micrometers.

[0014] Secondly, this utility model embodiment provides a silicon carbide power component, including a silicon carbide power chip with a temperature-resistant cycling stepped metal as described in any of the above possible implementations.

[0015] This invention provides a silicon carbide power chip with a temperature-cycle-resistant stepped metal. By setting the metal electrodes to have a gradually changing edge thickness, the height difference between the electrodes and the surrounding area can be smoothly transitioned, avoiding the formation of steep steps. This smooth transition allows the covering dielectric layer to adhere evenly, reducing local thickness unevenness of the dielectric layer caused by steep steps, thus making the deformation of the dielectric layer smoother under temperature cycling and other scenarios. Smoother deformation of the dielectric layer results in a more uniform stress distribution within the layer, preventing stress concentration at the locations corresponding to steep steps. Less stress concentration can significantly reduce the risk of dielectric layer cracking, reduce the possibility of moisture intruding into the chip through cracks, and ultimately improve the long-term operational reliability of the silicon carbide power chip. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of the silicon carbide power chip provided in this embodiment of the utility model; Figure 2 This is a schematic diagram of the structure of the silicon carbide power chip with temperature-resistant cycling stepped metal provided in this embodiment of the present invention; Figure 3 This is a schematic diagram of another temperature-resistant, cycle-resistant, stepped metal silicon carbide power chip provided in this embodiment of the present invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.

[0018] The term "comprising" and any other variations thereof in the specification, claims, and accompanying drawings of this invention mean "including but not limited to," and are intended to cover a non-exclusive inclusion, not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order.

[0019] The implementation of this utility model will be described in detail below with reference to the accompanying drawings: Temperature and humidity cycling testing is a core reliability verification method for electronic components such as silicon carbide power devices. By alternately applying environmental stresses with different combinations of temperature and humidity, it simulates the temperature and humidity alternation scenarios that devices may encounter in real-world applications. The aim is to accelerate the exposure of potential failure problems caused by the synergistic effect of temperature and humidity, and to assess their long-term stability. Unlike temperature cycling testing, which only assesses temperature stress, temperature and humidity cycling testing leverages the penetrability of humidity and the stress effect of temperature changes: at high temperatures, the gaps between materials expand, making it easier for moisture to penetrate; at low temperatures, the gaps contract, moisture is trapped and undergoes oxidation or corrosion reactions with the material. At the same time, the thermal stress generated by temperature alternation exacerbates interface damage, thereby quickly exposing potential failures that are difficult to detect at room temperature.

[0020] In the silicon carbide power chip structure, the core functions of polyimide (PI) and the dielectric layer are insulation protection, stress buffering, and environmental barrier, in order to meet the high power and extreme environment requirements of SiC chips.

[0021] Figure 1 This is a schematic diagram of the structure of the silicon carbide power chip provided in this embodiment of the utility model; Figure 1 This is a schematic diagram of a longitudinal section structure perpendicular to the substrate plane. (Refer to...) Figure 1 A silicon carbide power chip comprises a silicon carbide substrate layer 1, a silicon carbide epitaxial layer 2, a metal electrode layer 3, a dielectric layer 4, and polyimide 5. Power devices need to carry large currents, therefore the metal electrodes are relatively thick, typically 1μm to 5μm. The thicker metal electrodes result in higher step heights. This leads to morphological distortion of the polyimide thin film and dielectric layer covering the metal electrode steps (see reference). Figure 1 The area within the dashed circle (the part inside the circle) experiences significant stress changes during high and low temperature cycling, making it more prone to fracture. A fractured dielectric layer can no longer act as a barrier, allowing moisture to penetrate during reliability testing or use, thus reducing the reliability of the silicon carbide power chip.

[0022] This invention, by setting the metal electrode to have a gradually changing edge thickness, can smoothly transition the height difference between the electrode and the surrounding area, avoid the formation of steep steps, reduce the risk of dielectric layer cracking, reduce the possibility of moisture intruding into the chip through cracks, and ultimately improve the long-term operational reliability of silicon carbide power chips.

[0023] Figure 2 This is a schematic diagram of the structure of the silicon carbide power chip with temperature-resistant cycling stepped metal provided in this embodiment of the invention. (Refer to...) Figure 2The chip comprises, from bottom to top, a silicon carbide substrate layer 1, a silicon carbide epitaxial layer 2, and a metal electrode layer 3; the metal electrode layer 3 includes a plurality of mutually isolated metal electrodes; the thickness of the metal electrode edges gradually decreases in the direction away from the center of the metal electrode; a dielectric layer 4 covers the metal electrode layer 3; the dielectric layer 4 covers each metal electrode and the exposed silicon carbide epitaxial layer 2 between the metal electrodes; and a polyimide thin film layer 5 covers the dielectric layer 4.

[0024] In some embodiments, the chip comprises, from bottom to top, a silicon carbide substrate layer 1, a silicon carbide epitaxial layer 2, and a metal electrode layer 3.

[0025] The silicon carbide substrate 1 serves as a physical support, supporting the structural layers above it, such as epitaxial layers and electrode layers.

[0026] For example, the silicon carbide substrate 1 is n-type doped 4H-SiC. For example, the thickness of the silicon carbide substrate 1 ranges from 300 micrometers to 500 micrometers.

[0027] The core function of the silicon carbide epitaxial layer 2 is to realize the switching, rectification, or voltage regulation functions of power devices. By forming specific doping distributions through epitaxial growth, such as the channel region, drift region, or source / drain region of a MOSFET, the breakdown voltage and conduction performance of the chip are directly determined.

[0028] The metal electrode layer 3 serves as a bridge connecting the chip and external circuits, enabling the introduction or extraction of current. For example, in a SiC MOSFET, the gate electrode receives the control signal, while the source electrode extracts the load current.

[0029] In some embodiments, the metal electrode layer 3 includes a plurality of mutually isolated metal electrodes.

[0030] Different metal electrodes need to independently perform different functions, such as control signals, load current, etc.

[0031] For example, the silicon carbide epitaxial layer 2 includes a source region, a drain region, and a gate region; correspondingly, the source region is provided with a source electrode, the drain region is provided with a drain electrode, and the gate region is provided with a gate electrode.

[0032] In some embodiments, the thickness of the metal electrode edge gradually decreases in the direction away from the center of the metal electrode.

[0033] The gradual transition structure at the edge of the metal electrode replaces steep steps with a thickness gradient, alleviating the interfacial stress between the electrode and the surrounding dielectric layer 4. The vertical projection of the metal electrode is divided into two parts: a central part, occupying the majority of the area, for example, 90%; and an edge part, occupying a minority of the area, for example, 10%. The central part of the metal electrode maintains the designed thickness, while the edge thickness does not suddenly drop to 0, but gradually thins through a transition region, eventually connecting with the surface of the surrounding silicon carbide epitaxial layer 2, forming a sloped edge shape.

[0034] If the edge of the metal electrode is a steep vertical structure with a sudden change in thickness, the dielectric layer 4 covering it will form a region of abrupt change in thickness at the step. For example, the dielectric layer 4 is thicker at the top and bottom of the step, and thinner in the middle of the step. During temperature cycling, this uneven thickness will lead to significant differences in the thermal expansion and contraction of the dielectric layer 4, and the corner of the step will become a stress concentration point, which is very likely to cause cracking of the dielectric layer 4.

[0035] The gradient edge design, with its sloping transition, ensures uniform coverage by the upper dielectric layer 4, resulting in a smooth thickness change. This minimizes the deformation of the dielectric layer 4 during temperature variations, evenly distributing stress in the transition zone and preventing localized stress overload. Structurally, this reduces the risk of dielectric layer 4 fracture. Furthermore, the gradient edge makes it easier for the dielectric layer 4 to completely fill the electrode gaps, reducing edge bubbles or voids.

[0036] In some embodiments, a dielectric layer 4 is covered on the metal electrode layer 3; the dielectric layer 4 covers each metal electrode and the silicon carbide epitaxial layer 2 exposed between the metal electrodes.

[0037] In this embodiment, the dielectric layer 4 forms a full-coverage enclosure for the metal electrodes and the exposed epitaxial layer, achieving electrical isolation and environmental protection.

[0038] Covering the metal electrodes can isolate different functional electrodes and prevent short circuits between electrodes caused by air breakdown or impurity conductivity. Especially for high-voltage chips, the dielectric layer can withstand lateral voltage and ensure the reliability of insulation between electrodes.

[0039] The silicon carbide epitaxial layer 2 exposed between the electrodes is covered. The epitaxial layer is the functional core area of ​​the chip, such as the channel region and drift region of a MOSFET. If directly exposed, it is easily corroded by moisture and contaminants, which can lead to surface state deterioration, such as increased leakage current or the formation of unnecessary conductive channels with the metal electrodes. The dielectric layer 4 forms a physical barrier to protect the electrical performance stability of the epitaxial layer surface.

[0040] For example, a dielectric layer 4 is grown on the metal electrode layer 3 by PECVD.

[0041] In some embodiments, a polyimide film layer 5 is coated on the dielectric layer 4.

[0042] For example, the thickness of the polyimide film layer 5 ranges from 4 micrometers to 10 micrometers.

[0043] This embodiment of the invention uses a metal electrode with a gradually changing edge thickness to smoothly transition the height difference between the electrode and the surrounding area, avoiding the formation of steep steps. This smooth transition allows the covering dielectric layer 4 to adhere evenly, reducing local thickness unevenness of the dielectric layer 4 caused by steep steps, thus making the deformation of the dielectric layer 4 more gradual under temperature cycling and other scenarios. The gradual deformation of the dielectric layer 4 results in a more uniform stress distribution within the layer, preventing stress concentration at the locations corresponding to steep steps. Less stress concentration significantly reduces the risk of cracking of the dielectric layer 4, reduces the possibility of moisture intruding into the chip through cracks, and ultimately improves the long-term operational reliability of the silicon carbide power chip.

[0044] It should be noted that after reliability testing, windows can be opened in the protective layer above the metal electrodes to expose part of the surface of the metal electrodes for circuit lead-out of the silicon carbide power chip.

[0045] In one possible implementation, the longitudinal cross-sectional shape of the edge of the metal electrode is a slope shape.

[0046] In one possible implementation, the longitudinal cross-sectional shape of the edge of the metal electrode is stepped.

[0047] For example, the longitudinal section of the metal electrode edge is a section cut along a direction perpendicular to the chip surface.

[0048] In this embodiment, the stepped edge is smoothly transitioned through multiple layers, so that the dielectric layer 4 can be uniformly covered layer by layer along the steps, avoiding abrupt changes in thickness and reducing stress concentration points; reducing interface defects between the metal electrode and the dielectric layer 4, such as bubbles and gaps, improving the bonding stability between the two, and thus reducing the risk of moisture intrusion.

[0049] In one possible implementation, the metal electrode comprises multiple layers of metal; the lateral dimension of each metal layer decreases progressively from bottom to top.

[0050] In this embodiment, the longitudinal section of the metal electrode edge presents a multi-step shape. By gradually reducing the lateral dimension of the metal layer from bottom to top, an orderly stepped transition is formed at the electrode edge, rather than a vertical and steep edge.

[0051] Taking a three-layer metal electrode as an example, from bottom to top, it consists of: a bottom contact layer (Ti / Ni), a middle barrier layer (TaN), and a top transport layer (Al / Cu). The bottom contact layer contacts the epitaxial layer, has the largest lateral dimension, and covers the entire contact area of ​​the electrode. The middle barrier layer only covers the core area of ​​the bottom contact layer, has a smaller lateral dimension than the bottom layer, and its edge forms the first step with the bottom layer edge, with the step height equal to the thickness of the middle metal layer. The top transport layer only covers the central area of ​​the middle barrier layer, has a smaller lateral dimension than the middle layer, and its edge forms the second step with the middle layer edge, with the step height equal to the thickness of the top metal layer. Ultimately, the longitudinal section of the electrode edge exhibits a stepped shape that is wider at the bottom and narrower at the top, with each layer receding inwards, rather than a single vertical cross-section.

[0052] From a process implementation perspective, the lateral dimensions of each metal layer can be precisely controlled through multiple photolithography and etching processes to achieve stepped edges, and the edge peeling problem during the etching of a single layer of thick metal can also be avoided.

[0053] In one possible implementation, the material of the metal electrode includes titanium nickel, titanium nitride tungsten molybdenum, or aluminum copper silver.

[0054] For example, the bottom metal is Ti / Ni, the middle metal is TiN / W / Mo, and the top metal is Al / Cu / Ag.

[0055] Figure 3 This is a schematic diagram of another temperature-resistant, cycle-resistant, stepped-metal silicon carbide power chip provided in this embodiment of the invention. (Refer to...) Figure 3 In one possible implementation, the dielectric layer 4 includes a first dielectric layer 41 and a second dielectric layer 42; the first dielectric layer 41 fills the space between the metal electrodes; the thickness of the first dielectric layer 41 is the same as the thickness of the metal electrodes; and the second dielectric layer 42 covers the metal electrodes and the first dielectric layer 41.

[0056] This embodiment of the invention eliminates interface steps and reduces local stress at the interface between the first dielectric layer 41 and the metal electrode by making the first dielectric layer 41 and the metal electrode have the same thickness and be coplanar. A second dielectric layer 42 is then covered on the first dielectric layer 41 and the metal electrode. The second dielectric layer 42 is a uniformly high integral in the same plane, with uniform stress distribution everywhere. Even if subjected to stress from the upper and lower layers, it is not easy to break and can effectively block moisture intrusion, ultimately improving the chip's temperature cycle reliability.

[0057] In one possible implementation, the density of the second dielectric layer 42 is greater than the density of the first dielectric layer 41.

[0058] The first dielectric layer 41 is designed with a low density to meet the requirements for filling the gaps between electrodes. The core purpose of the first dielectric layer 41 is to fill the gaps between electrodes, and it needs to be coplanar with the electrodes and of equal thickness. Low-density materials have better gap-filling properties, making it easier to penetrate into the tiny electrode gaps during the deposition process, avoiding the formation of bubbles or voids. At the same time, the lower density can better accommodate the slight deformation of the metal electrodes, reducing stress cracking at the filling interface.

[0059] The second dielectric layer 42 enhances environmental barrier and insulation reliability with high density. The second dielectric layer 42 needs to cover the top layer of the chip, directly facing stress changes and environmental corrosion. High density means extremely low film porosity, effectively blocking moisture and impurity ions from entering, preventing oxidation of the underlying metal electrodes and moisture absorption failure of the first dielectric layer 41; high density also corresponds to higher volume resistivity and tensile strength, which not only improves the overall high-voltage resistance of the chip, preventing dielectric breakdown under high voltage, but also resists thermal stress shocks during temperature cycling, reducing the risk of film cracking.

[0060] In one possible implementation, the first dielectric layer 41 is made of silicon oxide; the second dielectric layer 42 is made of silicon nitride.

[0061] In one possible implementation, the thickness of the metal electrode ranges from 3 micrometers to 6 micrometers.

[0062] In one possible implementation, the silicon carbide substrate 1 is n-type doped 4H-SiC.

[0063] In one possible implementation, the thickness of the polyimide film layer 5 ranges from 4 micrometers to 10 micrometers.

[0064] The following examples illustrate the fabrication process of a silicon carbide power chip with a temperature-resistant bilayer dielectric.

[0065] In one possible implementation, the preparation method includes: Step 1: Perform preparation operations such as ion implantation, oxidation, etching, and ohmic contact on silicon carbide wafers.

[0066] Step 2: Metal electrode fabrication. Metal deposition is performed on a silicon carbide wafer. Before metal deposition, the wafer is cleaned to remove contaminants from its surface.

[0067] Step 3: Deposit a multilayer metal on the surface of the silicon carbide wafer. The metal can be Ti / Al, Ti / Ta / Al, Ti / Pt / Au or other combinations, with a thickness of 3μm~6μm.

[0068] Step 4: Photolithography defines the metal deposition area. A layer of photoresist is coated on the surface of the wafer. The thickness of the photoresist is 2μm~8μm. The areas where no metal electrodes need to be prepared are exposed and developed to expose the metal surface.

[0069] Step 5: Use metal etching to etch the areas where metal electrodes are not needed. Repeat steps 4 and 5, performing multiple photolithography and etching processes to form a stepped shape. After etching, remove the photoresist.

[0070] Step 6: Deposition of the first dielectric layer. PECVD dielectric deposition is performed on the surface of the metal-etched wafer. The deposited dielectric is Si3N4, SiO2, or other types, with a thickness of 4μm to 7μm. For example, the thickness of the first dielectric layer is the same as the thickness of the metal electrode.

[0071] Step 7: Photolithography defines the dielectric deposition area. A layer of photoresist with a thickness of 2μm~8μm is coated on the wafer surface. Areas where dielectric deposition is not desired are exposed and developed to reveal the surface of the dielectric above the metal electrode. The areas where dielectric deposition is not desired are removed using etching or etching methods. After removal, the photoresist is removed. The metal electrode and the first dielectric layer become coplanar. Alternatively, mechanical and chemical polishing can be used to achieve coplanarity.

[0072] Step 8: Deposit a second dielectric layer on the wafer surface. The deposited dielectric is Si3N4, SiO2, or other types, with a thickness of 0.5 μm to 3 μm.

[0073] Step 9: Apply polyimide adhesive to the surface of the wafer to protect it with a thickness of 4μm~10μm.

[0074] In one possible implementation, this invention provides a silicon carbide power component, including a silicon carbide power chip with a temperature-resistant cycling stepped metal as described in any of the above possible implementations.

[0075] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A silicon carbide power chip with a temperature-resistant, cycle-resistant stepped metal, characterized in that, From bottom to top, it includes: a silicon carbide substrate layer, a silicon carbide epitaxial layer, and a metal electrode layer; The metal electrode layer includes a plurality of mutually isolated metal electrodes; The thickness of the edge of the metal electrode gradually decreases in the direction away from the center of the metal electrode; A dielectric layer is covered on the metal electrode layer; the dielectric layer covers each metal electrode and the silicon carbide epitaxial layer exposed between the metal electrodes. A polyimide film layer is coated on top of the dielectric layer.

2. The silicon carbide power chip with temperature-resistant cycling stepped metal as described in claim 1, characterized in that, The longitudinal cross-sectional shape of the edge of the metal electrode is stepped.

3. The silicon carbide power chip with temperature-resistant cycling stepped metal as described in claim 2, characterized in that, The metal electrode comprises multiple layers of metal; the lateral dimension of each metal layer decreases progressively from bottom to top.

4. The silicon carbide power chip with temperature-resistant cycling stepped metal as described in claim 1, characterized in that, The dielectric layer includes a first dielectric layer and a second dielectric layer; The first dielectric layer is filled between the metal electrodes; the thickness of the first dielectric layer is the same as the thickness of the metal electrodes. The second dielectric layer covers the metal electrode and the first dielectric layer.

5. The silicon carbide power chip with temperature-resistant cycling stepped metal as described in claim 4, characterized in that, The density of the second dielectric layer is greater than the density of the first dielectric layer.

6. The silicon carbide power chip with temperature-resistant cycling stepped metal as described in claim 1, characterized in that, The thickness of the metal electrode ranges from 3 micrometers to 6 micrometers.

7. The silicon carbide power chip with temperature-resistant cycling stepped metal as described in claim 1, characterized in that, The silicon carbide substrate is n-type doped 4H-SiC.

8. The silicon carbide power chip with temperature-resistant cycling stepped metal as described in claim 1, characterized in that, The thickness of the polyimide film layer ranges from 4 micrometers to 10 micrometers.

9. A silicon carbide power module, characterized in that, Silicon carbide power chips comprising temperature-resistant cycling stepped metals as described in any one of claims 1 to 8.

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