Discrete device package structure, package module

Abstract

The utility model provides a kind of discrete device packaging structure and a packaging module.In the discrete device packaging structure, lead frame includes fin and multiple pins, the back electrode of power chip is attached on fin, front electrode is connected with corresponding pin by conductive structure, plastic package covers power chip, plastic package has opposite first surface and second surface, the surface of fin away from power chip and second surface are same in orientation and at least part of plastic package is exposed, pin is partially exposed plastic package;Wherein, when discrete device packaging structure is attached on substrate, the first surface of plastic package is oriented substrate, the surface of fin away from power chip and the second surface of plastic package are all back to substrate, pin is welded on substrate.In this way, top heat dissipation can be achieved, and the heat dissipation capacity of product is improved.The packaging module includes the discrete device packaging structure described above.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a discrete device packaging structure and a packaging module. Background Technology

[0002] Power semiconductors are the core components of power electronics for power conversion and circuit control. In recent years, power devices such as MOSFETs and IGBTs have developed rapidly towards higher power density, and their current and voltage capabilities have also increased significantly. The high voltage and high current requirements for discrete devices are becoming increasingly stringent, and the application environment is also placing higher demands on packaging.

[0003] Figure 1 This is a top view of a traditional discrete device packaging structure. Figure 2 This is a side view of a traditional discrete device package structure. Figure 3 This is a bottom view of a traditional discrete device packaging structure. Figure 4 This is a front view of a traditional discrete device package structure. (Reference) Figures 1 to 4 As shown, in a traditional discrete device surface mount packaging structure, the high-potential electrode on the back of the chip (not shown) is connected to the heat sink 11 in the lead frame. Part of the heat sink 11 is exposed from the molded body 12 and is led out as an electrode. The front electrode of the chip is bonded to the corresponding pin 13 through wire bonding, and the end of the pin 13 outside the molded body 12 extends into the plane where the heat sink 11 is located. Figure 5 This is a schematic diagram of a traditional discrete device package structure mounted on a PCB substrate. (Reference) Figure 3 and Figure 5 As shown, the molding compound 12 has a first surface 12a and a second surface 12b facing each other. The heat sink 11 is flush with the first surface 12a of the molding compound 12. In traditional discrete device packaging structures, when mounted on a PCB substrate 20, the first surface 12a of the molding compound 12 faces the PCB substrate 20 and the second surface 12b faces away from the PCB substrate 20. The heat sink 11 and leads 13 are both soldered to the PCB substrate 20, so the packaging structure mainly dissipates heat through the copper foil on the PCB substrate 20. However, the heat dissipation capacity of the copper foil on the PCB substrate is limited, resulting in ineffective heat dissipation of the chip inside the packaging structure, significantly reducing product performance. Furthermore, as... Figure 1 As shown, in the traditional discrete device package structure, all pins 13 are located on the same side of the molded body 12. The distance between each pin 13 is very close, the creepage distance is short, which poses a risk of voltage breakdown for high voltage products. In addition, the bonding positions are limited, and the products have insufficient high current capability. Utility Model Content

[0004] One of the purposes of this invention is to provide a discrete device packaging structure and a packaging module that can improve the heat dissipation capacity and performance of the product.

[0005] To achieve the above objectives, this utility model provides a discrete device packaging structure. The discrete device packaging structure includes: a lead frame comprising a heat sink and multiple pins; a power chip having opposing front and back sides, the back side of the chip having a back electrode, and the front side of the chip having at least one front electrode, the back electrode being mounted on the heat sink, and the front electrode being connected to the corresponding pins via a conductive structure; and a molding compound covering the front and sidewalls of the power chip and partially encapsulating the lead frame, the molding compound having opposing first and second surfaces, the surface of the heat sink away from the power chip facing the same direction as the second surface and at least partially exposed within the molding compound, and the pins partially exposed within the molding compound; wherein, when the discrete device packaging structure is mounted on a substrate, the first surface of the molding compound faces the substrate, the surface of the heat sink away from the power chip and the second surface of the molding compound both face away from the substrate, and the pins are soldered to the substrate.

[0006] Optionally, the plurality of pins include high-potential pins and low-potential pins. The molding compound has opposing first and second sidewalls. The high-potential pin extends from the first sidewall of the molding compound, and the low-potential pin extends from the second sidewall of the molding compound. The high-potential pin is connected to the heat sink, and the electrode on the front side of the chip is connected to the corresponding low-potential pin through the conductive structure.

[0007] Optionally, the second surface of the encapsulation has a groove located between the heat sink and the second sidewall.

[0008] Optionally, the distance between the root of the pin located in the sidewall of the molding compound and the surface of the heat sink away from the power chip is greater than or equal to 2 mm.

[0009] Optionally, the portion of the pin outside the molding compound extends from the middle of the sidewall of the molding compound and bends toward the first surface of the molding compound.

[0010] Optionally, a heat sink is provided on the second surface of the encapsulation, and the heat sink is connected to the heat sink fins.

[0011] Optionally, the power chip includes a MOSFET, the back electrode is a drain electrode, and the front electrode includes a source electrode and a gate electrode spaced apart. The source electrode and the gate electrode are respectively connected to the corresponding pins through conductive structures.

[0012] Optionally, the power chip includes an IGBT, the back electrode is a collector, and the front electrode includes an emitter and a gate electrode spaced apart. The emitter and the gate electrode are respectively connected to the corresponding pins through conductive structures.

[0013] Optionally, the power chip includes an SBD, a JBS, or an FRD.

[0014] This invention also provides a packaging module. The packaging module includes a substrate and a discrete device packaging structure as described above, which is mounted on the substrate.

[0015] In the discrete device packaging structure provided by this utility model, the lead frame includes a heat sink and multiple pins. The power chip has opposing front and back sides. The back side of the chip has a back electrode, and the front side of the chip has at least one front electrode. The back electrode is mounted on the heat sink. The front electrode is connected to the corresponding pin through a conductive structure. A molding compound covers the front and sidewalls of the power chip and partially encapsulates the lead frame. The molding compound has opposing first and second surfaces. The surface of the heat sink away from the power chip faces the same direction as the second surface of the molding compound, and the surface of the heat sink away from the power chip is further... A small portion of the molding compound is exposed, and the pin portion is also exposed. When the discrete device package structure is mounted on the substrate, the pins are soldered to the substrate. The first surface of the molding compound faces the substrate, while the surface of the heat sink away from the power chip and the second surface of the molding compound both face away from the substrate. This allows the heat sink connected to the high-potential electrode of the chip to dissipate heat directly without relying on the substrate, achieving top-level heat dissipation of the package structure. This improves the heat dissipation capacity of the package structure and enhances product performance. Furthermore, this discrete device package structure has high compatibility with existing production lines, helping to save manufacturing costs.

[0016] Furthermore, the multiple pins include high-potential pins and low-potential pins. The molding compound has opposing first and second sidewalls. The high-potential pin extends from the first sidewall of the molding compound, and the low-potential pin extends from the second sidewall. The high-potential pin is connected to the heat sink. The electrode on the front side of the chip is connected to the corresponding low-potential pin through the conductive structure. Compared to having the high and low potential pins on the same side of the molding compound, the high and low potential pins of the package structure are respectively arranged on both sides of the molding compound. This increases the creepage distance between the pins, which meets the electrical isolation requirements of high-voltage products. It also increases the space for conductive bonding, thus increasing the bonding area and enhancing the product's high-current capability. Attached Figure Description

[0017] Figure 1 This is a top view of a traditional discrete device packaging structure.

[0018] Figure 2 This is a side view of a traditional discrete device package structure.

[0019] Figure 3 This is a bottom view of a traditional discrete device packaging structure.

[0020] Figure 4 This is a front view of a traditional discrete device packaging structure.

[0021] Figure 5 This is a schematic diagram of a traditional discrete device package structure mounted on a PCB substrate.

[0022] Figure 6 This is a top view of the internal structure of a discrete device packaging structure provided in an embodiment of the present invention.

[0023] Figure 7 This is a side view of the internal structure of a discrete device packaging structure provided in an embodiment of the present invention.

[0024] Figure 8 This is a top view of a discrete device packaging structure provided in an embodiment of the present invention.

[0025] Figure 9 This is a left-side view of a discrete device packaging structure provided in an embodiment of the present invention.

[0026] Figure 10 This is a bottom view of a discrete device packaging structure provided in an embodiment of the present invention.

[0027] Figure 11 This is a rear view of a discrete device package structure provided in an embodiment of the present invention.

[0028] Figure 12 This is a front view of a discrete device package structure provided in an embodiment of the present invention.

[0029] Figure 13 This is a schematic diagram of a discrete device packaging structure mounted on a substrate according to an embodiment of the present invention.

[0030] Figure 14 This is a schematic diagram of a heat sink being added to a heat sink in one embodiment of the present invention.

[0031] Figure 15 This is a schematic diagram of electrode connections in a discrete device package structure provided in an embodiment of the present invention, where the power chip includes a MOSFET.

[0032] Figure 16The circuit diagram of the power chip including MOSFET provided by this utility model.

[0033] Figure 17 This is a schematic diagram of electrode connections in a discrete device package structure provided in an embodiment of the present invention, where the power chip includes an IGBT and an FRD.

[0034] Figure 18 The circuit diagram of the power chip including IGBT provided by this utility model.

[0035] Figure 19 This is a schematic diagram of electrode connections in a discrete device package structure provided in an embodiment of the present invention, where the power chip includes an FRD, JBS, or SBD.

[0036] Figure 20 Circuit diagrams of power chips including FRD, JBS or SBD provided for this utility model.

[0037] Figure 21 This is a top view of a discrete device packaging structure provided in another embodiment of the present invention.

[0038] Explanation of reference numerals in the attached figures: 11-Heat sink; 12-Molded package; 12a-First surface; 12b-Second surface; 13-Pin; 101-Heat sink; 102a-High potential pin; 102b-First pin; 102c-Second pin; 102d-Third pin; 200-Power chip; 300-Lead; 400-Molded package; 400a-First surface; 400b-Second surface; 400c-First sidewall; 400d-Second sidewall; 401-Groove; 500-Substrate; 600-Heat sink. Detailed Implementation

[0039] The discrete device packaging structure and packaging module proposed in this utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.

[0040] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly stated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly stated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly stated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly stated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly stated.

[0041] Figure 6 This is a top view of the internal structure of a discrete device packaging structure provided in an embodiment of the present invention. Figure 7 This is a side view of the internal structure of a discrete device packaging structure provided in an embodiment of the present invention. Figure 8 This is a top view of a discrete device packaging structure provided in an embodiment of the present invention. Figure 9 This is a left-side view of a discrete device packaging structure provided in an embodiment of the present invention. Figure 10 This is a bottom view of a discrete device packaging structure provided in an embodiment of the present invention. Figure 11 This is a rear view of a discrete device package structure provided in an embodiment of the present invention. Figure 12 This is a front view of a discrete device package structure provided in an embodiment of the present invention. Figure 13 This is a schematic diagram of a discrete device packaging structure mounted on a substrate according to an embodiment of the present invention.

[0042] refer to Figures 6 to 13As shown, the discrete device package structure provided in this embodiment includes a lead frame, a power chip 200, and a molding compound 400. The lead frame includes a heat sink 101 and multiple pins. The power chip 200 has opposing front and back sides. The back side of the chip 200 has a back electrode, and the front side of the chip 200 has at least one front electrode. The potential of the back electrode is higher than that of the front electrode. The back electrode is mounted on the heat sink 101, and the front electrode is connected to the corresponding pins through a conductive structure. The molding compound 400 covers the front and sidewalls of the power chip 200 and partially encapsulates the lead frame. The molding compound 400 has opposing first surfaces 400a and second surfaces 400b. The surface of the heat sink 101 away from the power chip 200 (i.e., the surface of the heat sink 101 without the chip mounted) faces the same direction as the second surface 400b, and at least part of the surface of the heat sink 101 away from the power chip 200 is exposed in the molding compound 400. The pins are partially exposed in the molding compound 400.

[0043] Among them, reference Figure 6 , Figure 7 and Figure 13 As shown, when the discrete device package structure is mounted on the substrate 500, the first surface 400a of the molding compound 400 faces the substrate 500, the surface of the heat sink 101 away from the power chip 200 and the second surface 400b of the molding compound 400 both face away from the substrate 500, and the pins are soldered to the substrate 500. In this way, the heat sink 101 connected to the high-potential electrode (i.e., the back electrode) of the chip 200 can dissipate heat directly without relying on the substrate 500 for heat dissipation, realizing top heat dissipation of the package structure, which helps to improve the heat dissipation capacity of the package structure and improve the performance of the product.

[0044] Specifically, the heat sink 101 is made of a metal material with excellent heat dissipation performance, including but not limited to copper (Cu), copper alloys, and iron-nickel alloys. The material of the pins can be the same as that of the heat sink 101.

[0045] refer to Figure 6 As shown, in this embodiment, multiple pins are distributed on opposite sides of the heat sink 101. For example, the multiple pins may include a high-potential pin 102a and a low-potential pin, which are respectively disposed on opposite sides of the heat sink 101.

[0046] In this embodiment, as Figure 6As shown, the number of high-potential pins 102a includes, but is not limited to, two. High-potential pins 102a can be directly connected to one side of the heat sink 101. Low-potential pins are arranged on the other side of the heat sink 101 and are not directly connected to the heat sink 101. Low-potential pins can include a first pin 102b, a second pin 102c, and a third pin 102d. The number of first pins 102b, second pins 102c, and third pins 102d can all be one or more. For example, the number of first pins 102b can be five. The five first pins 102b can be connected to the ends of the heat sink 101. The number of second pins 102c and third pins 102d is one.

[0047] Figure 21 This is a top view of a discrete device package structure provided in another embodiment of the present invention. In another embodiment of this application, such as... Figure 21 As shown, the high-potential pins 102a and low-potential pins on both sides of the heat sink 101, or the two sides of the molding compound 400, can be symmetrically arranged, but are not limited thereto. For example, the number of high-potential pins 102a extending from the first sidewall 400c of the molding compound 400 can be seven, and all seven high-potential pins 102a can be directly connected to the heat sink 101. The number of low-potential pins extending from the second sidewall 400d of the molding compound 400 can also be seven, that is, the low-potential pins include a third pin 102d, a second pin 102c, and five first pins 102b arranged in sequence. The low-potential pins are not directly connected to the heat sink 101.

[0048] It should be noted that the total number of pins in the discrete device package structure and the number of pins arranged on each side of the plastic package 400 can be adjusted according to product requirements.

[0049] refer to Figure 6 and Figure 7 As shown, the power chip 200 is mounted on the surface of the heat sink 101, the back electrode of the chip 200 is mounted on the heat sink 101, and the front electrode of the chip 200 is connected to the corresponding low-potential pin through a conductive structure.

[0050] For example, the conductive structure can be lead 300 or a copper clip, but is not limited to these. Lead 300 can be copper wire, aluminum wire, silver wire, or gold wire, etc. The following explanation uses lead 300 as an example of the conductive structure.

[0051] For example, the power chip 200 may include a metal-oxide-semiconductor transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), and / or a fast recovery diode (FRD).

[0052] Figure 15 This is a schematic diagram of electrode connections in a discrete device package structure provided in an embodiment of the present invention, where the power chip includes a MOSFET. Figure 16 A circuit diagram of a power chip including a MOSFET provided by this utility model. In one embodiment, as shown... Figure 15 and Figure 16 As shown, the power chip 200 includes a MOSFET. The back electrode of the power chip 200 is a drain electrode, and the front electrode includes a source electrode and a gate electrode spaced apart. The source electrode and the gate electrode are respectively connected to the corresponding pins through conductive structures. That is, the source electrode can be electrically connected to multiple first pins 102b through multiple leads 300, and the gate electrode is electrically connected to a third pin 102d through leads 300. In this case, the first pin 102b serves as the source pin (S), the third pin 102d serves as the gate electrode pin (G), and the high-potential pin 102a serves as the drain pin (D). In this embodiment, the source electrode of the power chip 200 can also be connected to a second pin 102c through leads 300. The second pin 102c is located between the third pin 102d and the first pin 102b. In this case, the second pin 102c is a Kelvin pin (K). The Kelvin pin is used to transmit electrical signals, and the source pin is used to transmit current. This allows the transmission of electrical signals and current to be separated, which is beneficial to improving the switching efficiency of the power chip.

[0053] Figure 17 This is a schematic diagram of electrode connections in a discrete device package structure provided in an embodiment of the present invention, where the power chip includes an IGBT and an FRD. Figure 18 A circuit diagram of a power chip including an IGBT is provided for this utility model. In one embodiment, as shown... Figure 17 and Figure 18 As shown, the power chip 200 includes an IGBT, the back electrode is the collector, and the front electrode of the chip 200 may include an emitter and a gate electrode spaced apart. The emitter and gate electrodes are respectively connected to corresponding low-potential pins through conductive structures. That is, the emitter can be electrically connected to multiple first pins 102b through multiple leads 300, and the gate electrode is electrically connected to a third pin 102d through a lead 300. In this case, the first pin 102b serves as the emitter pin (E), the third pin 102d serves as the gate pin (G), and the high-potential pin 102a serves as the collector pin (C). The emitter of the power chip 200 can also be connected to a second pin 102c through a lead 300. The second pin 102c is located between the third pin 102d and the first pin 102b. In this case, the second pin 102c is a Kelvin pin (K).

[0054] Continue to refer to Figure 17As shown, when the power chip includes an IGBT, it may also include an FRD. The anode of the FRD can be connected to the first pin 102b through a conductive structure, and the cathode of the FRD is attached to the heat sink 101.

[0055] Figure 19 This is a schematic diagram of electrode connections in a discrete device package structure provided in an embodiment of the present invention, where the power chip includes an FRD, JBS, or SBD. Figure 20 Circuit diagrams of power chips including FRD, JBS, or SBD provided for this utility model. In one embodiment, refer to... Figure 19 and Figure 20 As shown, when the power chip 200 includes FRD, JBS or SBD, its back electrode is the cathode. The back electrode is attached to the heat sink 101. The chip has a front electrode on the front side. The front electrode is the anode and is connected to the first pin 102b through the lead 300. At this time, the high potential pin 102a is the cathode pin, the first pin 102b is the anode pin, and the second pin 102c and the third pin 102d can be empty pins.

[0056] refer to Figures 6 to 13 As shown, the molding compound 400 covers the front and sidewalls of the power chip 200 and partially encapsulates the lead frame. The molding compound 400 has opposing first surfaces 400a and second surfaces 400b. The surface of the heat sink 101 away from the power chip 200 (i.e., the surface of the heat sink 101 without the chip mounted) faces the same direction as the second surface 400b of the molding compound 400. At least part of the surface of the heat sink 101 away from the power chip 200 is exposed to the molding compound 400 so that the heat sink 101 can directly dissipate heat. The pin portion is exposed to the molding compound 400.

[0057] For example, the surface of the heat sink 101 away from the power chip 200 can be flush with the second surface 400b of the molding compound 400 within the process tolerance range.

[0058] In this embodiment, reference Figures 6 to 10 As shown, the molding compound 400 has a first sidewall 400c and a second sidewall 400d opposite each other. A high-potential pin 102a can extend from the molding compound 400 from the first sidewall 400c, and a low-potential pin can extend from the molding compound 400 from the second sidewall 400d.

[0059] It should be noted that, compared with the high and low potential pins being located on the same side of the molding compound, the high and low potential pins of the discrete device package structure in this embodiment are respectively arranged on both sides of the molding compound 400. This can increase the creepage distance between the pins, that is, the creepage distance between the pins is longer, which can meet the electrical isolation requirements of high voltage products. In addition, this can also increase the space for conductive structure bonding, that is, increase the area of ​​conductive structure bonding, which is beneficial to enhancing the high current capability of the product.

[0060] In one embodiment of this application, as Figure 8 and Figure 9 As shown, the second surface 400b of the molding compound 400 has a groove 401. The groove 401 is located between the heat sink 101 and the second sidewall 400d, or in other words, the groove 401 is located between the end of the low-potential pin exposed in the molding compound 400 and the heat sink 101. In this way, adding the groove 401 between the low-potential pin and the heat sink 101 can increase the creepage distance between the low-potential pin and the heat sink 101, which is beneficial to improving the reliability of the discrete device package structure.

[0061] For example, the recess 401 may extend along the direction of the arrangement of the plurality of low-potential pins, or extend along the width direction of the second sidewall 400d of the molding compound 400. Figure 8 The groove 401 extends horizontally. The depth of the groove 401 can be greater than or equal to 0.3 mm and less than or equal to 1 mm, for example, 0.5 mm, but is not limited to this. The depth of the groove 401 can be set according to specific circumstances.

[0062] refer to Figure 9 As shown, the distance H between the root of the pin in the sidewall of the molding compound 400 and the surface of the heat sink 101 away from the power chip 200 can be greater than or equal to 2 mm. This satisfies the electrical isolation requirements between the pin and the heat sink 101, and allows for certain creepage requirements even when a heat sink is added above the heat sink 101 and the second surface 400b of the molding compound. The value of H is not limited to 2 mm and can be adjusted as needed. For example, the roots of multiple pins of the lead frame near the power chip 200 (or the roots located in the sidewall of the molding compound 400) can be located in the same plane, but are not limited to this.

[0063] Figure 14 This is a schematic diagram illustrating the addition of a heat sink to a heat sink in one embodiment of the present invention. Figure 14 As shown, in one embodiment of this application, a heat sink 600 can be provided on the second surface 400b of the molding compound 400. The heat sink 600 is connected to the heat sink 101, and adding the heat sink 600 helps to further improve the heat dissipation performance of the product. For example, refer to... Figure 14As shown, the radiator 600 may include a base plate and a plurality of vertically spaced heat dissipation fins, the bottoms of which are connected to the base plate, but not limited thereto. The structural shape of the radiator 600 can be designed according to actual needs. For example, the radiator 600 may be welded to the heat sink 101, but is not limited thereto. The materials of the radiator 600 include, but are not limited to, metals.

[0064] refer to Figure 7 and Figure 9 As shown, in some embodiments of this application, the portion of all pins located outside the molding compound 400 can extend from the middle of the sidewall of the molding compound 400 and bend toward the first surface 400a of the molding compound 400, that is, the exposed ends of all pins are bent toward the direction away from the heat sink 101. In this way, when the discrete device package structure is mounted on the substrate, it is convenient to connect the pins to the substrate, and the heat sink 101 can be exposed on the surface of the molding compound 400 away from the substrate to achieve top heat dissipation.

[0065] refer to Figure 7 and Figure 13 As shown, when the discrete device package structure is mounted on the substrate 500, the first surface 400a of the molding compound 400 faces the substrate 500, the surface of the heat sink 101 away from the power chip 200 and the second surface 400b of the molding compound both face away from the substrate 500. That is, the first surface 400a of the molding compound serves as the bottom surface close to the substrate 500 and the second surface 400b serves as the top surface away from the substrate 500, and the leads are soldered to the substrate 500.

[0066] For example, substrate 500 may be a printed circuit board (PCB), but is not limited to this. Substrate 500 may also be other substrates such as a ceramic substrate.

[0067] For example, the molded body 400 of the discrete device package structure can be fixed to the substrate 500 by adhesive layer, or the discrete device package structure can be fixed by soldering the pins, but is not limited thereto.

[0068] This embodiment also provides a packaging module, which includes a substrate 500 and a discrete device packaging structure as described above mounted on the substrate 500.

[0069] like Figure 14 As shown, the encapsulation module may also include a heat sink 600, which may be disposed on the second surface 400b of the molding compound 400, and the heat sink 600 is connected to the heat sink 101.

[0070] In the discrete device packaging structure provided by this utility model, the lead frame includes a heat sink 101 and multiple pins. The power chip 200 has opposing front and back sides. The back side of the chip has a back electrode, and the front side of the chip has at least one front electrode. The back electrode is mounted on the heat sink, and the front electrode is connected to the corresponding pins through a conductive structure. A molding compound 400 covers the front and sidewalls of the power chip 200 and partially encapsulates the lead frame. The molding compound 400 has opposing first surfaces 400a and second surfaces 400b. The surface of the heat sink 101 away from the power chip 200 faces the same direction as the second surface 400b of the molding compound 400, and the surface of the heat sink 101 away from the power chip 200 is... A small portion of the molding compound 400 is exposed, and the pin portion is also exposed. When the discrete device package structure is mounted on the substrate 500, the pins are soldered to the substrate 500. The first surface 400a of the molding compound 400 faces the substrate 500, while the surface of the heat sink 101 away from the power chip 200 and the second surface 400b of the molding compound 400 both face away from the substrate 500. This allows the heat sink connected to the high-potential electrode of the chip to dissipate heat directly without relying on the substrate 500, achieving top-level heat dissipation of the package structure. This improves the heat dissipation capacity of the package structure and enhances product performance. Furthermore, this discrete device package structure has high compatibility with existing production lines, helping to save manufacturing costs.

[0071] Furthermore, the multiple pins include a high-potential pin 102a and a low-potential pin. The molding compound 400 has opposing first sidewalls 400c and second sidewalls 400d. The high-potential pin 102a extends from the first sidewall 400c of the molding compound 400, and the low-potential pin extends from the second sidewall 400d of the molding compound 400. Compared to having the high and low potential pins on the same side of the molding compound, the high and low potential pins of the package structure are respectively arranged on both sides of the molding compound 400. This increases the creepage distance between the pins, i.e., the creepage distance between the pins is longer, which can meet the electrical isolation requirements of high-voltage products. This also increases the space for conductive bonding, for example, increasing the bonding area of ​​the conductive structure, which is beneficial for enhancing the high-current capability of the product.

[0072] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. Any person skilled in the art can make possible changes and modifications to the technical solution of the present utility model by using the methods and techniques disclosed above without departing from the spirit and scope of the present utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present utility model without departing from the content of the technical solution of the present utility model shall fall within the protection scope of the technical solution of the present utility model.

Claims

1. A discrete device packaging structure, characterized in that, include: A lead frame, which includes a heat sink and multiple pins; A power chip has a front and a back side, the back side of the chip has a back electrode, the front side of the chip has at least one front electrode, the back electrode is attached to the heat sink, and the front electrode is connected to the corresponding pin through a conductive structure. as well as A molding compound covering the front and sidewalls of the power chip and encapsulating a portion of the lead frame, the molding compound having opposing first and second surfaces, the surface of the heat sink away from the power chip facing the same direction as the second surface and at least partially exposed through the molding compound, and the pins partially exposed through the molding compound; When the discrete device package structure is mounted on the substrate, the first surface of the molding compound faces the substrate, the surface of the heat sink away from the power chip and the second surface of the molding compound both face away from the substrate, and the pins are soldered onto the substrate.

2. The discrete device packaging structure as described in claim 1, characterized in that, The plurality of pins include high-potential pins and low-potential pins. The molding compound has opposing first and second sidewalls. The high-potential pin extends from the first sidewall of the molding compound, and the low-potential pin extends from the second sidewall of the molding compound. The high-potential pin is connected to the heat sink. The electrode on the front side of the chip is connected to the corresponding low-potential pin through the conductive structure.

3. The discrete device packaging structure as described in claim 2, characterized in that, The second surface of the encapsulation has a groove located between the heat sink and the second sidewall.

4. The discrete device packaging structure as described in claim 1, characterized in that, The distance between the root of the pin located in the sidewall of the molding compound and the surface of the heat sink away from the power chip is greater than or equal to 2 mm.

5. The discrete device packaging structure as described in claim 1, characterized in that, The portion of the pin located outside the molding compound extends from the middle of the sidewall of the molding compound and bends toward the first surface of the molding compound.

6. The discrete device packaging structure as described in claim 1, characterized in that, A heat sink is provided on the second surface of the encapsulation, and the heat sink is connected to the heat sink fins.

7. The discrete device packaging structure as described in claim 1, characterized in that, The power chip includes a MOSFET, the back electrode is a drain electrode, and the front electrode includes a source electrode and a gate electrode spaced apart. The source electrode and the gate electrode are respectively connected to the corresponding pins through conductive structures.

8. The discrete device packaging structure as described in claim 1, characterized in that, The power chip includes an IGBT, the back electrode is a collector, and the front electrode includes an emitter and a gate electrode spaced apart. The emitter and the gate electrode are respectively connected to the corresponding pins through conductive structures.

9. The discrete device packaging structure as described in claim 1, characterized in that, The power chip includes SBD, JBS, or FRD.

10. A packaging module, characterized in that, It includes a substrate and a discrete device package structure as described in any one of claims 1 to 9 mounted on the substrate.

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