Multi-core package structure and semiconductor device

Abstract

The present disclosure provides a multi-die package structure, comprising: a plurality of first die groups; each first die group comprises a plurality of first dies arranged horizontally; at least one second die group arranged below the first die groups, each second die group comprises a plurality of second dies stacked vertically; and the second dies in the second die groups electrically connect at least any two first dies in the first die groups. The present disclosure also provides a semiconductor device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a multi-chip packaging structure and semiconductor device. Background Technology

[0002] With the rapid development of the semiconductor industry, market demand for chips with high integration and powerful computing capabilities continues to rise. Especially in cutting-edge technology fields such as high-performance computing (HPC), artificial intelligence (AI), and high-end graphics processing, the need for larger package sizes and higher integration is becoming increasingly urgent. The market demands larger chip areas, while chip sizes cannot exceed the photomask size. Therefore, the industry is gradually turning to chiplet technology, breaking down complex chips into multiple small chips, which are interconnected in a flat manner. However, flat interconnection increases the package size. Although vertical stacking technology can reduce the package size, vertical stacking requires a high degree of matching between the sizes of different chip layers, limiting the sensitivity of chip design. Therefore, how to achieve efficient, low-power, and highly integrated die-to-die interconnect (D2D) is key to improving the overall performance of computing systems. Summary of the Invention

[0003] This disclosure provides a multi-chip packaging structure and a semiconductor device.

[0004] In a first aspect, embodiments of this disclosure provide a multi-core packaging structure, including:

[0005] Multiple first core groups; each first core group includes multiple first cores arranged horizontally.

[0006] At least one second core group is disposed below the first core group, the second core group comprising a plurality of vertically stacked second cores;

[0007] The second core in the second core group electrically connects at least any two of the first cores in the first core group.

[0008] Secondly, embodiments of this disclosure provide a semiconductor device including a multi-chip package structure, wherein the multi-chip package structure includes any one of the multi-chip package structures provided in the embodiments of this disclosure.

[0009] The multi-chip packaging structure provided in this disclosure includes a first chip group comprising a plurality of horizontally arranged first chips, and a second chip group comprising a plurality of vertically stacked second chips. Since the first and second chips are vertically stacked, the integration of the packaging structure is improved and the area of ​​the packaging structure is reduced. Moreover, the second chips in the second chip group can electrically connect any two first chip groups within the plurality of first chip groups, without being limited by the size layer of the first and second chips, thereby improving the sensitivity of the multi-chip packaging design and shortening the interconnection path between the first chip groups, which can improve the transmission efficiency between the first chips and reduce power consumption. Attached Figure Description

[0010] In the accompanying drawings of the embodiments disclosed herein:

[0011] Figure 1 This is a cross-sectional schematic diagram of a multi-core packaging structure provided in an embodiment of the present disclosure;

[0012] Figure 2 This is a top perspective view of a portion of a multi-core packaging structure provided in an embodiment of the present disclosure;

[0013] Figure 3 A top view of the multi-core packaging structure provided in the embodiments of this disclosure;

[0014] Figure 4 This is a schematic diagram of the interconnection between the first core group and the second core group in an embodiment of this disclosure;

[0015] Figure 5 This is a schematic diagram illustrating the functional interaction between the active module in the second chip group and the first chip group in an embodiment of this disclosure.

[0016] Figure 6 A flowchart illustrating a method for fabricating a multi-core packaging structure provided in this embodiment of the disclosure;

[0017] Figure 7-19 This is a schematic diagram of the structure at different stages of the manufacturing process of multi-core packaging provided in the embodiments of this disclosure.

[0018] In the attached diagram:

[0019] 1-First chip, 2-Second chip, 21, 22-Second chip wafer, 2a, 2b, 2c, 2d-Router sub-module, 3-Adapter board, 31-First redistribution layer, 41-First bonding structure, 42-Second bonding structure, 43-Third bonding structure, 53-Fourth bonding structure, 54-Carrier board, 5-Dielectric layer, 51-Fifth bonding structure, 52-Large conductive pillar, 61-Second redistribution layer, 71-First through-silicon via, 72-Second through-silicon via, 8-Substrate, 9-Passive chip, 91-Passive device. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of this disclosure, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0021] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0022] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0023] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0024] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0025] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0026] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0027] In packaging technology, 2.5D packaging lies between 2D and 3D. It arranges multiple chips horizontally on an interposer, utilizing high-density wires on the interposer to achieve high-speed communication between the chips. However, 2.5D packaging results in longer interconnect paths, inevitably leading to larger package sizes. 3D packaging technology stacks multiple chips vertically to achieve electrical interconnection. Compared to traditional 2D packaging, 3D packaging shortens the interconnect paths, achieving more efficient signal transmission and a more compact structure. However, 3D packaging requires a high degree of chip size matching; the dimensions of upper and lower layers of chips must be highly consistent, significantly increasing the difficulty of interconnection and limiting design flexibility.

[0028] In a first aspect, embodiments of this disclosure provide a multi-core packaging structure.

[0029] Figure 1 This is a cross-sectional schematic diagram of a multi-core packaging structure provided in an embodiment of this disclosure. Figure 1 As shown, the multi-core packaging structure provided in this embodiment includes:

[0030] The first core group includes a plurality of first cores 1 arranged horizontally. This disclosure does not limit the number of first core groups or the number of first cores within a single first core group.

[0031] At least one second core group is disposed below the first core group, i.e., the first core group is on top and the second core group is below. The second core group includes a plurality of vertically stacked second cores 2. This disclosure does not limit the number of second core groups or the number of second cores 2 within a second core group.

[0032] The second core 2 in the second core group electrically connects at least any two first cores 1 in the first core group. (Not every core in the second core group has this function.)

[0033] In some embodiments, a functional module (not shown in the figure) is provided in the second core 2. The functional module provides corresponding functions to the first core 1 and the second core 2. Therefore, the first core 1 does not need to be provided with some auxiliary functional modules. The limited space is used to set up the main functional module, which improves the service capability of the main function of the first core 1. The auxiliary functional modules are set in the second core 2 and are used by the first core 1 and the second core 2. This saves the space of the first core 1 and improves the utilization rate of the auxiliary functional modules.

[0034] Because the first and second chip groups are interconnected vertically, size limitations are reduced, significantly increasing the flexibility of package design. In areas where vertical interconnection is not required, other, lower-cost interconnection methods can be used, thereby effectively reducing overall package cost.

[0035] In some instances, the second core group includes active cores and / or passive cores.

[0036] The common modules of multiple first cores in the first core group can be arranged in the second core group. No common functional modules are set in the first core group. The common functional modules interact with the multiple first cores in the first core group through vertical interconnection. For example, integrating a clock module in the second core group can provide a clock signal for the second core group, and can also synchronously provide clock signals for the first cores in multiple first core groups. This can significantly shorten the clock tree length and improve transmission efficiency.

[0037] In some embodiments, on the plane where the first core group is located, the projection of the first core group electrically connected to the second core group at least partially overlaps with the projection of the second core group.

[0038] Figure 2 This is a top perspective view of a portion of a multi-core packaging structure provided in an embodiment of the present disclosure. Figure 3 This is a top view of a multi-core packaging structure provided in an embodiment of this disclosure. Figure 2 and Figure 3 The multi-chip package structure includes five first chip groups (Die1-Die5) and five second chip groups (Die6-Die10). Each first chip group (Die1-Die5) includes multiple first chips 1, and each second chip group (Die6-Die10) includes multiple second chips 2. The second chip group (Die6) electrically connects the first chip groups (Die1, Die2, Die3, and Die4). On the plane of the multi-chip package structure, a portion of the projection of the second chip group (Die6) overlaps with the projections of the first chip groups (Die1, Die2, Die3, and Die4), respectively.

[0039] The second core group Die6 includes routing submodules 2a, 2b, 2c, and 2d. Routing submodule 2a electrically connects the second core group Die6 to the first core group Die1, routing submodule 2b electrically connects the second core group Die6 to the first core group Die2, routing submodule 2c electrically connects the second core group Die6 to the first core group Die3, and routing submodule 2d electrically connects the second core group Die6 to the first core group Die4.

[0040] In another implementation, the second core group can be an interconnection between any two core groups from a plurality of first core groups. Figure 4 This is a schematic diagram illustrating the interconnection between the first and second core groups in an embodiment of this disclosure. Figure 4 As shown, the sixth core group Die6 is provided with a first functional module D1, a second functional module D2, a third functional module D3, a fourth functional module D4, a fifth functional module D5 and a sixth functional module D6, which are used to interconnect the first core groups in pairs.

[0041] Combination Figure 3 and Figure 4 As shown, the third core group Die3 and the fourth core group Die4 are interconnected through the first functional module D1.

[0042] The second core group Die2 and the fourth core group Die4 are interconnected through the second functional module D2.

[0043] The first chip group Die1 and the second chip group Die2 are interconnected through the third functional module D3.

[0044] The first chip group Die1 and the third chip group Die3 are interconnected through the fourth functional module D4.

[0045] The first core group Die1 and the fourth core group Die4 are interconnected through the fifth functional module D5.

[0046] The second core group (Die2) and the third core group (Die3) are interconnected through the sixth functional module (D6).

[0047] Figure 5 This is a schematic diagram illustrating the functional interaction between the active module in the second chip group and the first chip group in an embodiment of this disclosure. Figure 5 As shown, active module Y1 and the fourth chip group Die4, active module Y2 and the second chip group Die2, active module Y3 and the first chip group Die1, and active module Y4 and the fifth chip group Die5 can all achieve functional interaction through vertical interconnection. For example, active modules Y1-Y4 are memory modules, while Die2-Die5 are logic units, realizing heterogeneous integration of memory and logic in a multi-chip package structure.

[0048] like Figure 1As shown, the multi-core packaging structure also includes an adapter board 3. The second core group is embedded in the adapter board 3. A first rewiring layer 31 is provided in the adapter board 3 near the first core group. At least one second core 2 in the second core group is electrically connected to the first rewiring layer 31, and at least two first cores 1 in the first core group are electrically connected to the first rewiring layer 31, which enhances the flexibility and functionality of communication between cores.

[0049] In some embodiments, two adjacent second cores 2 within a second core group are electrically connected by a first bonding structure 41.

[0050] In some embodiments, the first core 1 is electrically connected to the first redistribution layer 31 via the second bonding structure 42.

[0051] In some embodiments, the adapter board 3 further includes: a dielectric layer 5, a second core assembly embedded in the dielectric layer 5, a fifth bonding structure 51 provided in the thickness direction of the dielectric layer 5, a first end of the fifth bonding structure 51 being electrically connected to the first redistribution layer 31, and a second end being electrically connected to the second core assembly 2.

[0052] In some embodiments, the multi-core package structure further includes a second wiring layer 61 and a large conductive post 52. The second wiring layer 61 is disposed on the side of the adapter plate 3 away from the first core assembly, and the second wiring layer 61 is electrically connected to the second core 2. The first end of the large conductive post 52 is electrically connected to the first wiring layer 31, and the second end is electrically connected to the second wiring layer 61.

[0053] In some embodiments, the multi-core packaging structure further includes a substrate 8, wherein the adapter plate 3 is electrically connected to the wires on the substrate 8 via a third bonding structure 43.

[0054] In some embodiments, the multi-chip package structure further includes: a passive chip 9, a second through-silicon via 72, and a fourth bonding structure 53, wherein the passive chip 9 is embedded within the adapter plate 3, such as within the dielectric layer 5. In some disclosed embodiments, the passive chip 9 includes, but is not limited to, a passive device 91, which includes, but is not limited to, a capacitor.

[0055] The first end of the second through-silicon via 72 is electrically connected to the passive chip 9, and the second end is electrically connected to the second redistribution layer 61. The first end of the fourth bonding structure 53 is electrically connected to the first redistribution layer 31, and the second end is electrically connected to the passive chip 9.

[0056] In some embodiments, when the second core group includes active cores and passive cores, the active cores are electrically connected to the passive cores, the first core 1, and the substrate 8.

[0057] In some embodiments, the topmost core in the second core group is a passive core, and at least one of the remaining cores is an active core.

[0058] In the embodiments disclosed herein, the first bonding structure 41, the second bonding structure 42, the fifth bonding structure 51, and the fourth bonding structure 53 may employ processes such as hybrid bonding, bump bonding, and wire bonding, while the third bonding structure 43 may employ processes such as micro-bump bonding, solder ball bonding, and wire bonding.

[0059] In this embodiment, the second chip group interconnects any two first chip groups and accesses the on-chip topology network of the first chip group through a routing algorithm. Data is sent to the corresponding routing node and then to the target chip. A flow control mechanism is used to manage the flow based on the size and traffic volume of the specific first chip group, avoiding competition and conflicts for interconnection resources. In this embodiment, the second chip group can be used to implement functions such as system initialization, configuration distribution, event synchronization, interrupt handling, mode switching, power management, and interconnect rewiring.

[0060] To better understand the fabrication method of the multi-core packaging structure provided in this disclosure, a detailed introduction is given, in which the first core group is described.

[0061] Figure 6 This is a flowchart illustrating a method for fabricating a multi-core packaging structure according to an embodiment of the present disclosure. Figure 7-19 This is a schematic diagram of the structure at different stages in the fabrication of a multi-core package, provided as an embodiment of the present disclosure.

[0062] The method for fabricating a multi-core packaging structure provided in this disclosure includes:

[0063] Step S401: Obtain the first chip wafer group and the second chip wafer group.

[0064] The first chip wafer group comprises multiple first chip wafers A1, B1, C1, and D1. These first chip wafers are diced to obtain first chips. For example, dicing first chip wafer A1 yields multiple first chip Die1, dicing first chip wafer B1 yields multiple first chip Die2, dicing first chip wafer C1 yields multiple Die3, and dicing first chip wafer D1 yields multiple first chip Die4. The second chip wafer group comprises multiple second chip wafers. Dicing these second chip wafers yields second chips. For example, dicing second chip wafer B1 yields the upper-layer second chip in the second chip group, and dicing second chip wafer B2 yields the lower-layer second chip 22. Second chip wafers B1 and B2 are vertically stacked to form a second chip wafer group. Dicing the second chip wafer group yields a second chip group.

[0065] like Figure 7 As shown, the second chip wafer group includes vertically stacked second chip wafers 21 and 22.

[0066] Step S402: Prepare a fifth bonding structure on top of the second core wafer assembly.

[0067] like Figure 8 As shown, a fifth bonding structure 51 is fabricated above the second core wafer assembly.

[0068] Step S403: Flip the second chip wafer assembly and perform a thinning process on the second chip wafer assembly, such as... Figure 9 As shown.

[0069] Step S404: The second chip wafer group is cut to obtain multiple second chip groups, such as... Figure 10 As shown.

[0070] Step S405: Prepare large conductive pillars on the surface of the carrier plate.

[0071] Large conductive pillars 52 are electroplated on the surface of the carrier plate 54, such as Figure 11 As shown.

[0072] Step S406: Attach the second core assembly to the surface of the carrier plate.

[0073] The second core assembly and the passive core 9 are attached to and fixed to the surface of the carrier plate 54. Each second core assembly includes multiple second cores 2, such as... Figure 12 As shown.

[0074] Step S407: Fill the surface of the carrier board with insulating material to obtain a smooth dielectric layer, such as... Figure 13 As shown.

[0075] Step S408: A first redistribution layer is formed on the surface of the dielectric layer.

[0076] like Figure 14 As shown, a first redistribution layer 31 is formed on the first surface of the dielectric layer 5.

[0077] Step S409: A first bonding structure is formed on the first surface of the first overlay layer to form an adapter board.

[0078] like Figure 15 As shown, a second bonding structure 42 is formed on the first surface of the first redistribution layer 31 to form an adapter board.

[0079] In step S410, the first core assembly is bonded to the surface of the adapter plate, and the first core is electrically connected to the first bonding structure.

[0080] like Figure 16As shown, the first core assembly is bonded to the surface of the adapter plate 3, and the first core 1 is electrically connected to the second bonding structure 42.

[0081] Step S411: Flip the adapter plate.

[0082] like Figure 17 As shown, flip the adapter plate.

[0083] Step S412: Prepare a second redistribution layer on the second surface of the adapter board.

[0084] like Figure 18 As shown, a second redistribution layer 61 is prepared on the second surface of the adapter board.

[0085] Step S413: A third bonding structure is formed on the first surface of the adapter plate.

[0086] like Figure 19 As shown, a third bonding structure 43 is formed on the first surface of the adapter plate.

[0087] Step S414: The adapter board is electrically connected to the substrate through the third bonding structure.

[0088] It should be noted that although the above-described method for fabricating multi-core packaging structures only introduces one process flow, multi-core packaging structures can also be fabricated using other process flows.

[0089] The multi-chip packaging structure provided in this disclosure includes a first chip group comprising a plurality of horizontally arranged first chips, and a second chip group comprising a plurality of vertically stacked second chips. Since the first and second chips are vertically stacked, the integration of the packaging structure is improved and the area of ​​the packaging structure is reduced. Moreover, the second chips in the second chip group can electrically connect any two first chip groups within the plurality of first chip groups, without being limited by the size layer of the first and second chips, thereby improving the sensitivity of the multi-chip packaging design and shortening the interconnection path between the first chip groups, which can improve the transmission efficiency between the first chips and reduce power consumption.

[0090] The multi-core packaging structure of this disclosure supports a communication architecture that integrates point-to-point interconnection and packet-switched routing interconnection. It breaks the size limitation of a single-core photomask, expands the scale of on-chip networks, and supports the physical implementation of three-dimensional on-chip networks. The structure of the second core group is compatible and can be reused for different first core groups, exhibiting strong scalability and suitability for diverse application scenarios.

[0091] In some embodiments, the multi-chip package structure includes a power management chip, an I / O chip, and a logic chip. A first chip group includes a logic chip and an I / O chip, which are interconnected and communicate with each other through a second chip group. The second chip group includes a power management chip and a passive chip. The passive chip is responsible for the interconnection between the logic chip and the I / O chip and integrates capacitors to effectively reduce power supply noise. Simultaneously, the power management chip precisely regulates the system operating voltage to ensure stable operation of the overall system.

[0092] In some embodiments, the multi-chip package structure includes storage chips, logic chips, and I / O chips. A first chip group includes logic chips and I / O chips, which are interconnected through a second chip group for data transmission. The second chip group includes multiple storage chips and one passive chip. The passive chip not only handles the interconnection between the logic and I / O chips but also integrates decoupling capacitors to effectively suppress power supply noise. The storage chips provide the system with high-speed, high-capacity data storage, significantly improving the overall system performance.

[0093] In some embodiments, the multi-chip package structure includes an optical chip, a logic chip, and an I / O chip. A first chip group includes logic chips and I / O chips, and a second chip group includes optical chips and passive chips. The passive chips integrate deep-channel capacitors. In some embodiments, the first chip group includes optical chips and I / O chips, and the second chip group includes logic chips and passive chips. The passive chips integrate deep-channel capacitors. This architecture not only integrates the power integrity advantages of deep-channel capacitors but also achieves package-level optical interconnection through optoelectronic co-design, constructing a groundbreaking optoelectronic heterogeneous integration architecture.

[0094] In some embodiments, the multi-chip package structure includes multiple logic chips. The first chip group consists of multiple logic chips with the same or different architectures. The second chip group includes a multi-chip routing node and a central control unit, which is responsible for providing multi-chip switching interconnection and performing system transactions, such as system initialization, configuration distribution, multi-chip synchronization, interrupt handling, status monitoring and switching, power mode management, etc. It can expand the scale of on-chip network, adapt to the co-packaging of logic chips with various functional architectures, and realize the system within the multi-chip package efficiently, flexibly and at low cost.

[0095] Secondly, embodiments of this disclosure provide a semiconductor device.

[0096] The semiconductor device provided in this disclosure includes a multi-chip package structure, which includes any one of the multi-chip package structures provided in this disclosure. To save space, the multi-chip package structure will not be described in detail here.

[0097] The semiconductor device provided in this disclosure has a high degree of integration and shortens the interconnection path between different chip groups. Therefore, it can improve the transmission efficiency of the semiconductor device and reduce power consumption.

[0098] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A multi-core packaging structure, comprising: Multiple first core groups; each first core group includes multiple first cores arranged horizontally. At least one second core group is disposed below the first core group, the second core group comprising a plurality of vertically stacked second cores; The second core in the second core group electrically connects at least any two of the first cores in the first core group.

2. The multi-core packaging structure according to claim 1, wherein, The second core is provided with a functional module, which provides corresponding functions to the first core group and the second core group.

3. The multi-core packaging structure according to claim 1, wherein, It also includes an adapter board, in which the second core group is embedded. A first rewiring layer is provided in the adapter board near the first core group. At least one second core in the second core group is electrically connected to the first rewiring layer, and at least two first cores in the first core group are electrically connected to the first rewiring layer.

4. The multi-core packaging structure according to claim 3, wherein, The first chip is electrically connected to the first redistribution layer via a second bonding structure.

5. The multi-core packaging structure according to claim 3, wherein, The adapter plate also includes: A dielectric layer, in which the second core assembly is embedded, and a fifth bonding structure is provided in the thickness direction of the dielectric layer. The first end of the fifth bonding structure is electrically connected to the first redistribution layer, and the second end is electrically connected to the second core assembly.

6. The multi-core packaging structure according to claim 3, wherein, Also includes: The second wiring layer is disposed on the side of the adapter board away from the first core assembly; A large conductive pillar, wherein a first end of the large conductive pillar is electrically connected to the first rewiring layer, and a second end of the large conductive pillar is electrically connected to the second rewiring layer.

7. The multi-core packaging structure according to claim 3, wherein, Also includes: A substrate, wherein the adapter plate is disposed on the surface of the substrate and is electrically connected to the wires on the substrate via a third bonding structure.

8. The multi-core packaging structure according to claim 3, wherein, Also includes: A passive chip, which is embedded in the adapter board; The fourth bonding structure has a first end electrically connected to the first redistribution layer and a second end electrically connected to the passive chip.

9. The multi-core packaging structure according to claim 1, wherein, On the plane where the first core group is located, the projection of the first core group, which is electrically connected to the second core group, at least partially overlaps with the projection of the second core group.

10. The multi-core packaging structure according to claim 1, wherein, The two adjacent second cores in the second core group are electrically connected by a first bonding structure.

11. The multi-core packaging structure according to claim 1, wherein, The second chip group includes active chips and / or passive chips.

12. A semiconductor device comprising a multi-chip package structure, wherein the multi-chip package structure comprises the multi-chip package structure according to any one of claims 1 to 11.

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