A high speed double pulse superimposed circuit
Patent Information
- Application Number
- CN202522077468.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-26
- Publication Date
- 2026-09-08
- Estimated Expiration
- 2035-09-26
AI Technical Summary
现有技术的方案是单纯的在脉冲电流上再增加一个脉冲,然而,这种方式频率提升受限,不会超过2KHZ,一旦超过,会导致叠加脉冲失效,焊接质量下降
由于本实用新型的高速双脉冲叠加电路的电源VCC与开关管Q1的集电极相连,控制模块的PWM2引脚与恒流电源相连,恒流电源的输出端与开关管Q1的集电极相连,开关管Q1的发射极接正极输出端OUT+,开关管Q1的发射极与开关管Q2的集电极相连,开关管Q2的发射极与负极输出端OUT-和接地端相连,控制模块通过驱动单元与开关管Q1的栅极和开关管Q2的栅极相连。使用时,输出端OUT+和输出端OUT-均与焊枪相连,这种电路利用控制模块控制开关管Q1和开关管Q2轮流打开或关闭,从而给焊枪提供周而复始的正负脉冲,在正脉冲关闭时,由于焊枪线及搭铁线存在电感及分布电容,会产生反向电动势,此时负脉冲打开,吸收掉这一反向电动势,负脉冲关闭的同时打开正脉冲,周而复始,从而实现高速脉冲叠加目的,从而提高了频率的宽度,且,不会因单个频率过高而出现脉冲信号失效的情况,从而保证了焊接质量。
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Figure CN224725259U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of welding technology, specifically to a high-speed dual-pulse superposition circuit. Background Technology
[0002] In the welding field, it's well known that increasing the welding pulse current is necessary to improve weld quality. Current technology simply adds another pulse to the pulse current; however, this method has limitations in frequency increase, not exceeding 2kHz. Once this is exceeded, the superimposed pulse fails, leading to a decrease in weld quality. This is because during welding, the welding torch connection and ground wire are relatively long, containing inductance and distributed capacitance, forming a low-pass filter. If the frequency reaches a certain level, it will filter out the high-frequency pulse signal, causing the pulse signal to fail and thus reducing weld quality. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide a high-speed dual-pulse superposition circuit, which can ensure the welding quality.
[0004] To solve the above problems, the following technical solutions are provided: This utility model discloses a high-speed dual-pulse superposition circuit, which includes a control module connected to a host computer and receiving control signals from the host computer. Its key features are: the power supply VCC is connected to the collector of switching transistor Q1; the PWM2 pin of the control module is connected to a constant current power supply, and the output of the constant current power supply is connected to the collector of switching transistor Q1; the emitter of switching transistor Q1 is connected to the positive output terminal OUT+; the emitter of switching transistor Q1 is connected to the collector of switching transistor Q2, and the emitter of switching transistor Q2 is connected to the negative output terminal OUT- and ground; the control module is connected to the gates of switching transistors Q1 and Q2 via a driving unit, and the control module is used to drive switching transistors Q1 and Q2 to turn on or off.
[0005] The driving unit includes AND gates IC3A, IC3B, IC3C, and IC3D. The PWM1 pin of the control module is connected to input pin 1 of AND gate IC3A. Input pin 2 of AND gate IC3A is connected to power supply VCC. The output pin of AND gate IC3A is connected to input pin 5 of AND gate IC3B, input pin 9 of AND gate IC3C, and input pin 10 of AND gate IC3C, respectively. The H pin of the control module is connected to input pin 4 of AND gate IC3B. Output pin 6 of AND gate IC3B is connected to the gate of switch Q1 via driving circuit one. Output pin 8 of AND gate IC3C is connected to input pin 12 of AND gate IC3D. The L pin of the control module is connected to input pin 13 of AND gate IC3C. Output pin 11 of AND gate IC3C is connected to the gate of switch Q2 via driving circuit two.
[0006] The PWM3 pin of the control module is connected to the second drive circuit.
[0007] An absorption circuit is connected in parallel between the emitter and collector of the switching transistor Q1.
[0008] An absorption circuit 2 is connected in parallel between the emitter and collector of the switching transistor Q2.
[0009] A Hall current sensor is located between the emitter of the switching transistor Q1 and the collector of the switching transistor Q2.
[0010] A Hall current sensor is located between the emitter of the switching transistor Q2 and the ground terminal.
[0011] The above approach has the following advantages: Since the power supply VCC of the high-speed dual-pulse superposition circuit of this utility model is connected to the collector of the switching transistor Q1, the PWM2 pin of the control module is connected to the constant current power supply, the output terminal of the constant current power supply is connected to the collector of the switching transistor Q1, the emitter of the switching transistor Q1 is connected to the positive output terminal OUT+, the emitter of the switching transistor Q1 is connected to the collector of the switching transistor Q2, the emitter of the switching transistor Q2 is connected to the negative output terminal OUT- and the ground terminal, and the control module is connected to the gate of the switching transistor Q1 and the gate of the switching transistor Q2 through the driving unit. In use, both the output terminals OUT+ and OUT- are connected to the welding torch. This circuit uses a control module to control the switching transistors Q1 and Q2 to turn on and off alternately, thereby providing the welding torch with a continuous cycle of positive and negative pulses. When the positive pulse is off, a reverse electromotive force is generated due to the inductance and distributed capacitance of the welding torch wire and ground wire. At this time, the negative pulse turns on to absorb this reverse electromotive force. The negative pulse turns off at the same time as the positive pulse turns on, and so on, thereby achieving the purpose of high-speed pulse superposition, which improves the frequency width and prevents the pulse signal from failing due to excessively high single frequency, thus ensuring the welding quality. Attached Figure Description
[0012] Figure 1 This is a schematic diagram of the high-speed dual-pulse superposition circuit of this utility model; Figure 2 This is a comparison diagram of the pulse output after the switching transistors of the high-speed dual-pulse superposition circuit of this utility model are superimposed and the pulse output without superposition. Detailed Implementation
[0013] The present invention will be further described in detail below with reference to the accompanying drawings.
[0014] like Figure 1 As shown, the high-speed dual-pulse superposition circuit of this invention includes a control module connected to a host computer to receive control signals from the host computer. The power supply VCC is connected to the collector of switching transistor Q1. The PWM2 pin of the control module is connected to a constant current power supply, and the output of the constant current power supply is connected to the collector of switching transistor Q1. The emitter of switching transistor Q1 is connected to the positive output terminal OUT+. The emitter of switching transistor Q1 is connected to the collector of switching transistor Q2, and the emitter of switching transistor Q2 is connected to the negative output terminal OUT- and ground. The control module is connected to the gates of switching transistors Q1 and Q2 through a drive unit, and the control module is used to drive switching transistors Q1 and Q2 to turn on or off.
[0015] In this embodiment, the control module is an MCU chip, specifically an R5F104PJ or STM32F103, etc. Those skilled in the art can choose according to the actual situation; this is existing technology and will not be elaborated further. The constant current power supply can be a Nippon Avionics NRW-IN900P, also existing technology, and will not be elaborated further. During operation, the positive output terminal OUT+ and the negative output terminal OUT- are connected to the welding torch. The MCU chip is connected to the host computer via a 458 communication interface. When the MCU receives the welding command from the host computer, it controls the switching transistors Q1 and Q2 to alternately turn on and off through the drive unit. When Q1 is on and Q2 is off, the MCU chip sends a PWM2 signal to the constant current power supply through the PWM2 pin. The constant current power supply sends a constant current pulse to the collector of Q1. The constant current pulse is output from OUT+ through Q1 to the welding torch. When Q1 is off and Q2 is on, a negative pulse is formed at the negative output terminal OUT-, thus achieving the alternating superposition of positive and negative pulses. Switch Q1 and switch Q2 are IGBTs.
[0016] like Figure 1 As shown, the driving unit includes AND gates IC3A, IC3B, IC3C, and IC3D. The PWM1 pin of the control module is connected to input pin 1 of AND gate IC3A. Input pin 2 of AND gate IC3A is connected to the power supply VCC. The output pins of AND gate IC3A are connected to input pins 5, 9, and 10 of AND gate IC3B, respectively. The H pin of the control module is connected to input pin 4 of AND gate IC3B. Output pin 6 of AND gate IC3B is connected to the gate of switch Q1 via drive circuit one. Output pin 8 of AND gate IC3C is connected to input pin 12 of AND gate IC3D. The L pin of the control module is connected to input pin 13 of AND gate IC3C. Output pin 11 of AND gate IC3C is connected to the gate of switch Q2 via drive circuit two. The PWM3 pin of the control module is connected to drive circuit two. By using gate circuits to superimpose L pulses and H pulses, precise and rapid alternating switching of transistors Q1 and Q2 can be achieved. The superimposed pulse output is similar to the non-superimposed pulse output. Figure 2 As shown, by superimposing pulses, the switching transistors Q1 and Q2 can be precisely controlled to turn on rapidly in turn, thereby achieving high-speed dual-pulse superposition output.
[0017] Specifically, in this embodiment, the first driving circuit is a positive pulse circuit, which includes an IC chip of model TC4427 and peripheral circuits. The specific structure is prior art and will not be described in detail here. The second driving circuit is a negative pulse circuit, which includes an IC chip of model 1EDN7550U and peripheral circuits. The specific structure is prior art and will not be described in detail here.
[0018] like Figure 1 As shown, a first absorption circuit is connected in parallel between the emitter and collector of switching transistor Q1. A second absorption circuit is connected in parallel between the emitter and collector of switching transistor Q2. Absorption circuit one and absorption circuit two can be conventional RC filter circuits composed of capacitors and resistors, which are existing technologies and will not be described in detail here.
[0019] like Figure 1 As shown, in this embodiment, a Hall current sensor is located between the emitter of switch Q1 and the collector of switch Q2. A Hall current sensor is located between the emitter of switch Q2 and the ground terminal, thereby realizing current detection feedback.
[0020] In operation, the MCU chip interacts with the host computer via a 485 interface to obtain corresponding data. The MCU then analyzes and modulates the data, outputting a corresponding PWM1 signal to a 2-input AND gate circuit. This signal is then inverted, outputting two sets of square wave signals with the same frequency and complementary phase. One set enters the positive pulse drive circuit, and the other enters the negative pulse drive circuit. The IGBT module is adjusted using a current signal provided by the MCU, achieving high-speed superposition of the dual-pulse current signals. When the positive pulse is off, a reverse electromotive force is generated due to the inductance and distributed capacitance of the welding torch wire and ground wire. At this time, the negative pulse is on, absorbing this reverse electromotive force. The cycle repeats, achieving high-speed pulse superposition.
Claims
1. A high-speed dual-pulse superposition circuit, comprising a control module connected to a host computer and receiving control signals from the host computer; characterized in that, The power supply VCC is connected to the collector of the switching transistor Q1. The PWM2 pin of the control module is connected to the constant current power supply, and the output of the constant current power supply is connected to the collector of the switching transistor Q1. The emitter of the switching transistor Q1 is connected to the positive output terminal OUT+. The emitter of the switching transistor Q1 is connected to the collector of the switching transistor Q2, and the emitter of the switching transistor Q2 is connected to the negative output terminal OUT- and the ground terminal. The control module is connected to the gate of the switching transistor Q1 and the gate of the switching transistor Q2 through the driving unit. The control module is used to drive the switching transistors Q1 and Q2 to turn on or off.
2. The high-speed dual-pulse superposition circuit as described in claim 1, characterized in that, The driving unit includes AND gate IC3A, AND gate IC3B, AND gate IC3C, and AND gate IC3D. The PWM1 pin of the control module is connected to input pin 1 of AND gate IC3A, input pin 2 of AND gate IC3A is connected to power supply VCC, and the output pin of AND gate IC3A is connected to input pin 5 of AND gate IC3B, input pin 9 of AND gate IC3C, and input pin 10 of AND gate IC3C, respectively. The H pin of the control module is connected to input pin 4 of AND gate IC3B, and output pin 6 of AND gate IC3B is connected to the gate of switch Q1 through driving circuit one. The output pin 8 of AND gate IC3C is connected to input pin 12 of AND gate IC3D, the L pin of the control module is connected to input pin 13 of AND gate IC3C, and output pin 11 of AND gate IC3C is connected to the gate of switch Q2 through driving circuit two.
3. The high-speed dual-pulse superposition circuit as described in claim 1, characterized in that, The PWM3 pin of the control module is connected to the second drive circuit.
4. The high-speed dual-pulse superposition circuit as described in claim 2, characterized in that, An absorption circuit is connected in parallel between the emitter and collector of the switching transistor Q1.
5. The high-speed dual-pulse superposition circuit as described in claim 2, characterized in that, An absorption circuit 2 is connected in parallel between the emitter and collector of the switching transistor Q2.
6. The high-speed dual-pulse superposition circuit as described in claim 2, characterized in that, A Hall current sensor is located between the emitter of the switching transistor Q1 and the collector of the switching transistor Q2.
7. The high-speed dual-pulse superposition circuit as described in claim 2, characterized in that, A Hall current sensor is located between the emitter of the switching transistor Q2 and the ground terminal.