An electromagnetic interference resistant circuit for an eddy current displacement sensor

Abstract

The utility model provides an anti -electromagnetic interference circuit of electric eddy current displacement sensor relates to sensor anti -interference technical field. This anti -electromagnetic interference circuit includes: the input end of fundamental wave signal isolation module is connected with the probe lead wire electricity, the second output end of fundamental wave signal isolation module is connected with the input end of external common mode noise compensation module electricity, the first output end of fundamental wave signal isolation module and the output end of external common mode noise compensation module pass through same injection node and the input end of analog detection front end electricity connection, the output end of analog detection front end is connected with the input end of digital processing module electricity, the input end of internal digital noise suppression module connects reference clock, the output end of internal digital noise suppression module is connected with the input end of digital processing module electricity. The utility model from the circuit design dimension initiative suppression external conduction noise and internal radiation interference, avoid amplifier saturation simultaneously.

Description

Technical Field

[0001] This utility model relates to the field of sensor anti-interference technology, and in particular to an anti-electromagnetic interference circuit for an eddy current displacement sensor. Background Technology

[0002] Eddy current displacement sensors operate based on the principle of electromagnetic induction. Their internal circuitry generates a fixed-frequency fundamental excitation signal, creating an alternating magnetic field around the probe coil. This allows for non-contact measurement of the displacement and vibration of a metallic object. These sensors are widely used for condition monitoring in industrial machinery. However, in industrial settings, sensor probe leads are typically long, making them susceptible to coupling with external broadband common-mode interference. Furthermore, the high-frequency clock of the sensor's internal digital processing module can generate electromagnetic crosstalk, all of which can reduce the sensor's measurement accuracy.

[0003] To reduce the impact of electromagnetic interference and environmental factors on sensors, several improved probe structures and basic circuits have been proposed in recent years. Chinese patent CN221593775U discloses a pseudo-differential eddy current displacement sensor probe and sensor. It features an axially symmetrical closed cavity inside the probe, housing a reference coil and a reference target. A detection coil, positioned opposite the object being measured, is located outside the cavity. This design utilizes the pseudo-differential structure formed by the reference coil and the detection coil to counteract the effects of ambient temperature changes and some low-frequency physical interference, thereby improving sensor stability and measurement accuracy. Chinese patent CN223512754U discloses a non-contact eddy current sensor, which incorporates a waveform conversion circuit and a high-frequency excitation circuit. The waveform conversion circuit converts the square wave output from the main control into a sine wave for output. The high-frequency excitation circuit generates a high-frequency magnetic field accordingly, and the front-end acquisition circuit acquires the induced voltage and outputs a measurement signal. This design improves the sensor's reliability and measurement range in complex electromagnetic environments by optimizing the front-end signal generation and acquisition chain.

[0004] However, the above solutions still have significant performance limitations when dealing with complex high-frequency interference. Specifically, the pseudo-differential structure proposed by CN221593775U mainly targets temperature drift and slowly changing environmental interference, which is a physical defense measure. Since the eddy current sensor needs to be connected to the back-end equipment through a long probe lead, external broadband common-mode noise will be directly conducted into the internal signal processing circuit along the lead. This pseudo-differential structure cannot actively intercept and cancel the conducted broadband common-mode noise at the circuit level, nor can it block the high-frequency clock radiation crosstalk generated by the digital module inside the sensor itself. While the non-contact eddy current sensor proposed by CN223512754U can improve system reliability through waveform conversion and optimized acquisition circuit, it lacks frequency selection and isolation mechanisms. Since the normal operation of the sensor depends on the large amplitude high-frequency fundamental excitation signal it generates, when strong external conducted noise enters the internal circuit, the high-frequency environmental noise and the high amplitude fundamental signal are mixed together and directly sent to the subsequent amplification and processing circuit, which can easily cause the amplifier to enter deep saturation and lose its ability to linearly amplify and process weak noise.

[0005] In summary, existing technologies cannot effectively distinguish between high-frequency fundamental excitation signals and broadband noise, and are unable to actively cancel high-frequency conducted interference and internal electromagnetic crosstalk. As a result, eddy current displacement sensors still face problems of signal distortion and decreased detection accuracy in complex industrial electromagnetic environments. Utility Model Content

[0006] To address the technical shortcomings of existing eddy current displacement sensors, such as their inability to effectively distinguish between high-frequency fundamental excitation signals and broadband noise, difficulty in actively canceling high-frequency conducted interference and internal electromagnetic crosstalk, and the tendency for amplifiers to saturate, this invention provides an anti-electromagnetic interference circuit for an eddy current displacement sensor. The circuit design aims to actively suppress external conducted noise and internal radiated interference while avoiding amplifier saturation.

[0007] To solve the above technical problems, an anti-electromagnetic interference circuit for an eddy current displacement sensor is provided. The eddy current displacement sensor includes: a probe lead, an analog detection front end, and a digital processing module. The anti-electromagnetic interference circuit includes: a fundamental signal isolation module, an external common-mode noise compensation module, and an internal digital noise suppression module.

[0008] The input terminal of the fundamental signal isolation module is electrically connected to the probe leads; the fundamental signal isolation module has a first output terminal and a second output terminal; the second output terminal of the fundamental signal isolation module is electrically connected to the input terminal of the external common-mode noise compensation module; the first output terminal of the fundamental signal isolation module and the output terminal of the external common-mode noise compensation module are electrically connected to the input terminal of the analog detection front end through the same injection node; the input terminal of the internal digital noise suppression module is connected to a reference clock; the output terminal of the internal digital noise suppression module is electrically connected to the input terminal of the digital processing module.

[0009] Furthermore, the fundamental signal isolation module includes: a common-mode current sampling network and a second-order tuned notch filter;

[0010] The input terminal of the common-mode current sampling network is electrically connected to the probe lead; the output terminal of the common-mode current sampling network serves as the first output terminal of the fundamental signal isolation module and is electrically connected to the input terminal of the second-order tuned notch filter.

[0011] The output of the second-order tuned notch filter serves as the second output of the fundamental signal isolation module.

[0012] Furthermore, the center frequency of the second-order tuned notch filter is set to the fundamental excitation frequency of the eddy current displacement sensor.

[0013] Furthermore, the external common-mode noise compensation module includes, in series, a high-order lead compensation network, an operational amplifier circuit, and a high-pass current injection network; wherein the input terminal of the high-order lead compensation network is electrically connected to the second output terminal of the fundamental signal isolation module, and the output terminal of the high-pass current injection network serves as the output terminal of the external common-mode noise compensation module.

[0014] Furthermore, the higher-order lead compensation network includes: an RCR lead compensation branch and an LCR resonance suppression branch; wherein one end of the RCR lead compensation branch serves as the input of the higher-order lead compensation network and is connected to one end of the LCR resonance suppression branch; the other end of the RCR lead compensation branch serves as the output of the higher-order lead compensation network; and the other end of the LCR resonance suppression branch is grounded.

[0015] Furthermore, the RCR lead compensation branch includes a main resistor and a series branch connected in parallel with the main resistor;

[0016] The series branch is composed of a first capacitor and a secondary resistor connected in series.

[0017] Furthermore, the LCR resonance suppression branch includes an inductor, a second capacitor, and a damping resistor connected in series.

[0018] Furthermore, the internal digital noise suppression module is implemented using a low-power open-loop spread spectrum clock generator; the low-power open-loop spread spectrum clock generator includes: a multiphase clock generator, a seed phase selection unit, a current-mode logic phase interpolator, and a digital modulation logic control unit;

[0019] The input of the multiphase clock generator is connected to the output of the reference clock. The output of the multiphase clock generator is electrically connected to the input of the seed phase selection unit. The output of the seed phase selection unit is electrically connected to the phase seed input of the current-mode logic phase interpolator. The output of the digital modulation logic control unit is electrically connected to the control terminal of the current-mode logic phase interpolator. The output of the current-mode logic phase interpolator is electrically connected to the clock input of the digital processing module.

[0020] The beneficial effects of adopting the above technical solution are as follows:

[0021] (1) Effectively avoid amplifier saturation: This invention uses a second-order tuned notch filter connected in series in the bypass sampling branch to filter out high-amplitude fundamental components before signal amplification, thus blocking the fundamental signal from entering the operational amplifier circuit. The voltage swing at the output of the operational amplifier is significantly reduced, ensuring the amplifier's linear inverting amplification capability against common-mode noise, while also reducing the demand on the system's high-voltage power supply module and saving hardware costs.

[0022] (2) Improve the common-mode noise suppression capability in the high-frequency band: This utility model introduces a high-order lead compensation network in the operational amplifier circuit, and uses the LCR resonant suppression branch and the RCR lead compensation branch to actively correct the high-frequency phase response of the feedforward loop and offset the phase delay of the active device.

[0023] (3) Reduction of internal self-excited electromagnetic radiation: This invention employs a low-power open-loop spread spectrum clock generator in the digital clock network. Through phase rotation and frequency periodic broadening mechanisms, the electromagnetic radiation energy concentrated at a single frequency point is dispersed to a wider frequency band, achieving attenuation of the peak electromagnetic radiation energy at a specific frequency point. The open-loop control architecture avoids the closed-loop locking delay problem of traditional phase-locked loops, effectively blocking the radiation interference from the digital module to the analog sensitive area under low power conditions.

[0024] (4) Improve detection accuracy and stability in complex environments: This utility model adopts a composite anti-interference architecture based on pure circuit dimensions. While preserving the integrity of the high-frequency fundamental excitation signal, it achieves comprehensive filtering of external conducted common-mode noise and internal self-excited radiation noise, improves the signal-to-noise ratio of the sensor signal link, and ensures the measurement accuracy and operational stability of the eddy current displacement sensor in industrial sites with strong electromagnetic interference. Attached Figure Description

[0025] Figure 1This is a hardware structure block diagram of the anti-electromagnetic interference circuit of an eddy current displacement sensor according to the present invention.

[0026] Figure 2 This is a circuit diagram of the high-order lead compensation network of this utility model;

[0027] Figure 3 This is a flowchart illustrating the data processing and workflow of the electromagnetic interference suppression circuit described in this utility model.

[0028] In the diagram: 1: Probe lead; 2: Main signal path; 3: Fundamental signal isolation module; 4: Common-mode current sampling network; 5: Second-order tuned notch filter; 6: External common-mode noise compensation module; 7: Operational amplifier circuit; 8: High-order lead compensation network; 801: Main resistor; 802: Secondary resistor; 803: First capacitor; 804: Inductor; 805: Second capacitor; 806: Damping resistor; 9: RCR lead compensation branch; 10: LCR resonance suppression branch; 11: High-pass current injection network; 12: Injection node; 13: Internal digital noise suppression module; 14: Multiphase clock generator; 15: Seed phase selection unit; 16: Current-mode logic phase interpolator; 17: Digital modulation logic control unit; 18: Analog detection front end; 19: Digital processing module. Detailed Implementation

[0029] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0030] In this embodiment, the eddy current displacement sensor includes: a probe lead 1, an analog detection front-end 18, and a digital processing module 19. The signal output by the probe lead 1 is a mixed signal, which is physically superimposed from the pure fundamental current carrying the target displacement information and an externally coupled broadband common-mode noise current. Without an electromagnetic interference suppression circuit, the mixed signal output by the probe lead 1 is directly input to the analog detection front-end 18, allowing external electromagnetic interference to couple directly into the analog detection front-end 18 through the probe lead. After processing by the analog detection front-end 18, the interference is input to the digital processing module 19, resulting in a large amount of noise in the signal received by the digital processing module 19, severely affecting the displacement detection accuracy.

[0031] To address this issue, this embodiment provides an anti-electromagnetic interference circuit for an eddy current displacement sensor, such as... Figure 1 As shown, in accordance with the order of signal detection and processing, the electromagnetic interference suppression circuit includes: a fundamental signal isolation module 3, an external common-mode noise compensation module 6, and an internal digital noise suppression module 13.

[0032] The input terminal of the fundamental signal isolation module 3 is electrically connected to the probe lead 1; the fundamental signal isolation module 3 has a first output terminal and a second output terminal; the second output terminal of the fundamental signal isolation module 3 is electrically connected to the input terminal of the external common-mode noise compensation module 6; the first output terminal of the fundamental signal isolation module 3 and the output terminal of the external common-mode noise compensation module 6 are electrically connected to the input terminal of the analog detection front-end 18 through the same injection node 12; the output terminal of the analog detection front-end 18 is electrically connected to the input terminal of the digital processing module 19; the input terminal of the internal digital noise suppression module 13 is connected to a reference clock; the output terminal of the internal digital noise suppression module 13 is electrically connected to the input terminal of the digital processing module 19.

[0033] The fundamental signal isolation module 3 includes: a common-mode current sampling network 4 and a second-order tuned notch filter 5.

[0034] In this embodiment, the common-mode current sampling network 4 can be implemented using an integrated printed circuit board (PCB) Rogowski coil. The second-order tuned notch filter 5 is implemented using a dual-T active notch filter.

[0035] The input terminal of the common-mode current sampling network 4 is electrically connected to the probe lead 1; the output terminal of the common-mode current sampling network 4 is electrically connected to the input terminal of the second-order tuned notch filter 5.

[0036] The output of the common-mode current sampling network 4 is used as the first output of the fundamental signal isolation module 3; the output of the second-order tuned notch filter 5 is used as the second output of the fundamental signal isolation module 3.

[0037] In this embodiment, the signal transmission path between the probe lead 1 and the analog detection front end 18 in the eddy current displacement sensor is regarded as the main signal path 2, and an injection node 12 is set on the main signal path 2; the common mode current sampling network 4 is connected in series on the main signal path 2, located between the probe lead 1 and the injection node 12.

[0038] The common-mode current sampling network 4 is used to extract the mixed signal in the main signal path 2 at a fixed ratio. This mixed signal includes the high-amplitude fundamental excitation signal required for sensor detection and the broadband common-mode noise coupled externally. The fixed ratio is determined by the input dynamic range of the operational amplifier circuit 7 and the expected amplitude of the common-mode noise.

[0039] In the complex frequency domain, the mixed current signal extracted by the common-mode current sampling network 4 It can be represented as:

[0040] ;

[0041] in, It is the high-frequency fundamental excitation current; This is the wideband common-mode noise current; It is a complex frequency variable.

[0042] The mixed current signal extracted by the common-mode current sampling network 4 is transmitted in two paths. One path is directly transmitted to the injection node 12, and the other path is input to the second-order tuned notch filter 5. This signal transmission path is regarded as a bypass sampling branch.

[0043] The center frequency of the second-order tuned notch filter 5 is set to the fundamental excitation frequency of the eddy current displacement sensor; the output of the second-order tuned notch filter 5 is connected to the input of the external common-mode noise compensation module 6.

[0044] The second-order tuned notch filter 5 is used to filter out the high-amplitude fundamental component of the mixed current signal extracted by the common-mode current sampling network 4 before it enters the operational amplifier circuit 7, and only retain the common-mode noise signal to be input to the operational amplifier circuit 7.

[0045] The transfer function of the second-order tuned notch filter 5 satisfy:

[0046] ;

[0047] in, It is a complex frequency variable; For quality factor; The center angular frequency, and ; The fundamental excitation frequency of the eddy current displacement sensor is .

[0048] Based on this transfer function The second-order tuned notch filter 5 exhibits extremely high impedance attenuation at the set center frequency, while maintaining low impedance conduction in other frequency bands outside the center frequency. When the mixed current signal flows through the second-order tuned notch filter 5, the mixed current signal... The product of the transfer function and the output signal of the second-order tuned notch filter 5 is used as the output signal. And then it is fed into the subsequent operational amplifier circuit 7.

[0049] ;

[0050] At the fundamental frequency, the numerator of the transfer function is zero, making ;in, The imaginary unit is used; however, the wideband common-mode noise deviates from the center frequency, and the second-order tuned notch filter 5 maintains low impedance to it, resulting in a gain of [missing information]. .therefore, The high-amplitude fundamental component is filtered out, and only the pure common-mode noise signal enters the subsequent operational amplifier circuit 7. The fundamental signal isolation module 3 designed in this embodiment directly solves the overload saturation problem caused by the direct entry of high-amplitude fundamental signals into the amplifier in traditional active filters. In the traditional architecture, if the mixed current directly enters the amplifier with a gain of... The equivalent input impedance is The operational amplifier circuit, output voltage swing for:

[0051] ;

[0052] Because the fundamental frequency amplitude is much larger than the noise amplitude, the voltage swing... This will quickly exceed the system's power supply limit, forcing the amplifier circuit into deep saturation. This embodiment reduces the output voltage by cutting off the path of the fundamental frequency into the amplifier. The voltage swing is significantly reduced, ensuring that the amplifier circuit always operates in the optimal linear region. Meanwhile, since the second-order tuned notch filter 5 is only deployed in the bypass sampling branch, the fundamental excitation signal on the main signal path 2 is not attenuated or affected in any way.

[0053] In this embodiment, the external common-mode noise compensation module 6 adopts a feedforward current sampling-current compensation topology. Its input terminal is connected to the second output terminal of the fundamental signal isolation module 3, and its output terminal is connected to the injection node 12 on the main signal path 2, which is used to actively cancel the broadband common-mode noise coupled by the external environment.

[0054] The external common-mode noise compensation module 6 includes, in series, a high-order lead compensation network 8, an operational amplifier circuit 7, and a high-pass current injection network 11; wherein, the input terminal of the high-order lead compensation network 8 is electrically connected to the second output terminal of the fundamental signal isolation module; and the output terminal of the high-pass current injection network 11 serves as the output terminal of the external common-mode noise compensation module 6.

[0055] In this embodiment, the high-order lead compensation network 8 is used to perform phase lead compensation on the common-mode noise signal to compensate for the phase lag generated in the subsequent inverting amplification and injection path, ensuring that the external common-mode noise compensation module 6 outputs a compensation signal with a phase exactly opposite to the actual broadband common-mode noise in the main signal path 2 across the entire frequency band. The operational amplifier circuit 7 is used to invert the phase-compensated common-mode noise signal to generate an inverting compensation current with the same amplitude but opposite phase to the common-mode noise in the main path, and injects this compensation current back into the main signal path 2 through the high-pass current injection network 11 to cancel the common-mode noise; the high-pass current injection network 11 is used to couple the inverting compensation current into the main signal path 2 and isolate the fundamental signal in the main signal path 2 from entering the operational amplifier circuit 7 to avoid interference from the fundamental signal to the compensation loop.

[0056] The operational amplifier circuit 7 can be implemented using a general-purpose high-speed operational amplifier; in this embodiment, the LM6171 high-speed operational amplifier is selected. The non-inverting input of the operational amplifier circuit 7 receives the common-mode noise signal processed by the high-order lead compensation network 8, while the inverting input is grounded, forming an inverting amplification topology. The signal after inverting amplification is sent to the high-pass current injection network 11 through the output.

[0057] The higher-order lead compensation network 8 includes: an RCR lead compensation branch 9 and an LCR resonance suppression branch 10; wherein, one end of the RCR lead compensation branch 9 serves as the input terminal of the higher-order lead compensation network 8, and the other end serves as the output terminal of the higher-order lead compensation network 8; one end of the LCR resonance suppression branch 10 is connected to one end of the RCR lead compensation branch 9, and the other end of the LCR resonance suppression branch 10 is grounded.

[0058] like Figure 2 As shown, the RCR lead compensation branch 9 includes: a main resistor 801 (denoted as...). ), the first capacitor 803 (denoted as ) and secondary resistor 802 (denoted as ).

[0059] The first capacitor 803 is connected in series with the secondary resistor 802 to form a series branch; the series branch is connected in parallel with the main resistor 801.

[0060] The RCR advance compensation branch 9 is used to provide phase advance for high-frequency signals to compensate for the inherent phase lag of the operational amplifier circuit in the high-frequency band.

[0061] Specifically, for low-frequency signals, the first capacitor 803 presents a high-impedance near-open circuit, and the signal is mainly transmitted through the main resistor 801. The initial value of the main resistor is set according to the low-frequency band compensation gain requirements to maintain the basic low-frequency gain of the system. As the noise signal frequency increases and enters the target high-frequency band, the impedance of the first capacitor 803 gradually decreases, and the high-frequency signal is transmitted more through the secondary resistor branch (i.e., the series branch). The RCR lead compensation branch 9 introduces zeros and poles into the frequency response of the circuit, and utilizes its differential characteristics to generate gain and phase lead angle that increase with frequency in a specific high-frequency band.

[0062] To accurately determine the final parameters of the secondary resistor 802 and the first capacitor 803, the equivalent transimpedance gain of the system is used as the control target. Ideally, this is the filter's ideal equivalent transimpedance gain against the input noise current. It should be equal to the impedance of the injected network. Wherein, the ideal equivalent transimpedance gain Defined as the ratio of the ideal output compensation voltage to the input noise current. In the operational amplifier stage of a practical circuit, it is the actual voltage gain at the non-inverting input. Based on the actual measured output voltage Actual voltage at the non-inverting input terminal The calculation shows that, .

[0063] Since the RCR lead compensation branch 9 constitutes the key input impedance network of the operational amplifier circuit 7, according to the operational amplifier closed-loop gain principle, the change in the equivalent AC impedance of the RCR lead compensation branch 9 in the high-frequency range will directly change the actual voltage gain of the amplifier circuit. Meanwhile, the overall actual transimpedance gain of the system is determined by the equivalent transmission impedance of the front-end sampling network and this actual voltage gain. This is jointly determined. Therefore, by adjusting the values ​​of the secondary resistor 802 and the first capacitor 803 to change the equivalent impedance of the branch at a specific frequency band, the actual voltage gain of the operational amplifier can be adjusted. This allows for the synchronous adjustment of the overall actual transimpedance gain. When the overall actual transimpedance gain approaches the ideal target, i.e., the impedance injected into the network... At this point, the final parameters of the secondary resistor 802 and the first capacitor 803 can be determined.

[0064] like Figure 2 As shown, the LCR resonance suppression branch 10 includes, in series, an inductor 804 (denoted as...). ), the second capacitor 805 (denoted as ) and damping resistor 806 (denoted as ).

[0065] The LCR resonance suppression branch 10 is used to absorb and suppress high-frequency resonance spikes. In the initial stage of parameter design, to suppress the resonance caused by the front-end sensor coil and maintain the original integral characteristics, the initial value of the series capacitor is set according to the resonance characteristics of the sensor coil. The initial design value of the inductor 804 is calculated based on the inherent resonant frequency of the sensor coil itself, satisfying:

[0066] ;

[0067] in, is the inherent resonant frequency of the sensor coil.

[0068] When the frequency of the noise signal is close to At this time, the LCR resonant suppression branch 10 presents extremely low impedance, directly bypassing excess resonant energy to ground level, ensuring that the signal input to the subsequent operational amplifier is protected from resonant spike interference. The damping resistor 806 is used to adjust the quality factor of the LCR resonant suppression branch 10 to control the notch bandwidth and depth. Its resistance value is selected according to the required damping characteristics, generally in the range of a few ohms to tens of ohms.

[0069] Through signal processing via the RCR lead compensation branch 9 and the LCR resonance suppression branch 10, the high-order lead compensation network 8 utilizes the generated lead phase to actively cancel the inherent phase lag of active devices at high frequencies. After conditioning by this network, the compensation current output by the operational amplifier circuit 7 maintains an ideal amplitude equal to and opposite phase to the common-mode noise current in the main path across a wide bandwidth. This inverted compensation current is then injected back into the main signal path 2 through the high-pass current injection network 11, where it physically superimposes with and completely cancels out the original common-mode noise.

[0070] The high-pass current injection network 11 includes an injection capacitor and an injection damping resistor connected in series. One end of the series connection is connected to the output of the operational amplifier circuit 7, and the other end is connected to the injection node 12 on the main signal path 2. The injection capacitor couples the high-frequency inverting compensation current output by the operational amplifier circuit 7 to the main signal path 2, while simultaneously blocking the fundamental excitation signal on the main signal path 2 from entering the output of the operational amplifier circuit 7. The injection damping resistor limits the peak value of the injected current and improves circuit stability.

[0071] The internal digital noise suppression module 13 is implemented using a low-power open-loop spread spectrum clock generator; the low-power open-loop spread spectrum clock generator includes: a multiphase clock generator 14, a seed phase selection unit 15, a current-mode logic phase interpolator 16, and a digital modulation logic control unit 17.

[0072] The input terminal of the multiphase clock generator 14 is connected to the output terminal of the reference clock; the output terminal of the multiphase clock generator 14 is electrically connected to the input terminal of the seed phase selection unit 15; the output terminal of the seed phase selection unit 15 is electrically connected to the phase seed input terminal of the current mode logic phase interpolator 16; the output terminal of the digital modulation logic control unit 17 is electrically connected to the control terminal of the current mode logic phase interpolator 16; and the output terminal of the current mode logic phase interpolator 16 is electrically connected to the clock input terminal of the digital processing module 19.

[0073] In this embodiment, the input terminal of the multiphase clock generator 14 serves as the input terminal of the internal digital noise suppression module 13 and is connected to the output terminal of the reference clock generated by the on-chip phase-locked loop (PLL) to receive a high-frequency, low-jitter gigahertz-level reference clock. The multiphase clock generator 14 converts the received reference clock into multiple multiphase signals with fixed phase differences. The seed phase selection unit 15, in conjunction with the current-mode logic phase interpolator 16, performs frequency subdivision and aliasing on the multiphase signals, down-converting them to a megahertz-level output clock suitable for the subsequent digital processing module 19, thus cutting off crosstalk from the source of self-excited electromagnetic radiation generated by the digital clock to the sensitive analog detection front-end 18.

[0074] The digital modulation logic control unit 17 is used to generate a digital triangular wave modulation signal to dynamically control the phase step of the current mode logic phase interpolator 16, so that the instantaneous frequency of the output clock is periodically broadened within a preset frequency band, so as to disperse the electromagnetic radiation energy concentrated on a single frequency point to a wider frequency band.

[0075] The digital triangular wave modulation signal has a frequency of 33kHz and an amplitude set by the user. This digital triangular wave modulation signal is dynamically converted into a digital control word and directly input to the control terminal of the current-mode logic phase interpolator 16, changing the interpolator's internal impedance distribution and current weighting coefficients in real time. According to the phase rotation principle, when the phase step (i.e., the phase change rate) of the clock signal changes with time according to the triangular wave law, the instantaneous frequency of the clock shifts. satisfy:

[0076] ;

[0077] in, Indicates time; The unmodulated center clock frequency; This represents the instantaneous phase angle of the clock. Since the current-mode logic phase interpolator 16 introduces phase hysteresis by accumulating the control word, its physical mechanism determines the additional phase change rate. The phase change rate is always less than or equal to zero, therefore the circuit operates in downspread mode. Under triangular wave control, the phase change rate... The corresponding phase step changes linearly: at the rising edge of the triangular wave, the phase step increases linearly, and the instantaneous frequency of the output clock is linearly decreased; at the falling edge of the triangular wave, the phase step decreases linearly, and the instantaneous frequency of the output clock is linearly increased. This control mechanism ensures that the instantaneous frequency of the final output clock is within a certain range. arrive Periodic linear reciprocating frequency conversion is performed within the interval, where, This is the preset spread spectrum depth.

[0078] In this embodiment, through open-loop phase rotation and frequency periodic broadening mechanisms, the electromagnetic radiation energy originally highly concentrated on a single narrow-band frequency point is dispersed and redistributed across a wider operating frequency range. This directly reduces the peak value of narrow-band electromagnetic radiation energy at specific sensitive operating frequencies from a physical perspective, achieving electromagnetic interference energy attenuation. Due to its open-loop architecture, this spread-spectrum clock generator does not rely on the closed-loop feedback control loop of a traditional phase-locked loop, avoiding the inherent locking delay, loop instability, and large-area high power consumption problems of closed-loop systems. It establishes a frequency conversion isolation barrier at the internal digital noise generation source with low power consumption.

[0079] The following describes a single use of this utility model in conjunction with the accompanying drawings.

[0080] like Figure 3 As shown, the electromagnetic interference suppression data processing and workflow of the sensor circuit of this utility model, according to the actual signal flow direction in the physical circuit and the circuit timing logic, specifically includes the following steps:

[0081] Step 1: Signal Input and Physical Mixing. Specifically, when the eddy current displacement sensor is working normally, the internal circuit continuously sends a high-amplitude, high-frequency fundamental excitation signal to the probe coil. In an industrial environment, the sensor's long probe lead 1 acts as a receiving antenna, and various external broadband electromagnetic interferences present in the space are directly coupled into the probe lead 1 in the form of common-mode noise. In the original main signal path 2, what is actually transmitted is a mixed signal formed by the physical superposition of the pure fundamental current carrying the target displacement information and the externally coupled broadband common-mode noise current.

[0082] Step 2: Noise Bypass Sampling and Fundamental Wave Filtering. Specifically, when the mixed signal in the main signal path 2 is transmitted forward, it first flows through the common-mode current sampling network 4 of the active electromagnetic interference filter. The common-mode current sampling network 4 extracts a portion of the mixed signal indiscriminately at a fixed ratio and guides it into the bypass sampling branch. Subsequently, the mixed current signal extracted by the common-mode current sampling network 4 enters the second-order tuned notch filter 5. The center frequency of the second-order tuned notch filter 5 has been pre-locked to the fundamental frequency of the sensor. When the mixed current signal passes through, the high-amplitude fundamental frequency component is filtered out due to extremely high physical impedance, while the common-mode noise with a wide frequency distribution passes smoothly through the second-order tuned notch filter 5 with low impedance. After the frequency selection and physical blocking in Step 2, the fundamental component of the mixed current signal is successfully stripped away, and only the pure common-mode noise signal is output to the next stage circuit.

[0083] Step 3: High-frequency phase compensation and inverting amplification. Specifically, the pure common-mode noise signal output from the second-order tuned notch filter 5 is fed into the operational amplifier circuit 7 after passing through the high-order lead compensation network 8. During the amplification process, the LCR resonance suppression branch 10 first absorbs and discharges the high-frequency resonance spike energy caused by the parasitic parameters of the front-end sampling coil, ensuring a smooth input signal waveform. Next, the signal flows through the RCR lead compensation branch 9. This branch utilizes the differentiating characteristics of passive devices to actively add a lead angle to the signal that increases with frequency. This lead angle cancels out the inherent phase lag of the internal transistors of the operational amplifier at high frequencies. After completing phase pre-compensation and synchronization correction, the operational amplifier circuit 7 linearly amplifies the pure common-mode noise signal, ultimately outputting an inverting compensation current with an amplitude completely equal to that of the main path common-mode noise and a phase difference of strictly 180 degrees within an extremely wide frequency band.

[0084] Step 4: Noise Cancellation and Clean Signal Transmission. Specifically, the inverting compensation current generated by the operational amplifier circuit 7 is smoothly injected back into the main signal path 2 through the high-pass current injection network 11. At the injection node 12 on the main signal path 2, based on Kirchhoff's current law, the inverting compensation current with a phase difference of 180 degrees directly and physically superimposes with the original common-mode noise current carried in the main signal path 2, and the two cancel each other out, thus canceling the common-mode noise in the main signal path 2. Since the high-frequency fundamental signal on the main signal path 2 did not enter the operational amplifier circuit 7 in step 2, it was not subjected to any inverting cancellation effect. Finally, only the purified, high signal-to-noise ratio high-frequency fundamental excitation signal is retained in the main signal path 2, and this clean signal continues to be stably transmitted to the analog detection front-end 18 at the back end for demodulation and displacement calculation.

[0085] Step 5: Back-end Digital Noise Spread Spectrum Isolation. Specifically, while the analog detection front-end 18 demodulates the clean signal and transmits it to the digital processing module 19 for data quantization, the internal digital noise suppression module 13 operates synchronously. To prevent high-frequency spike pulses generated during high-speed switching of the digital module from secondary radiation to the purified analog circuit, a low-power open-loop spread spectrum clock generator continuously operates. The digital modulation logic control unit 17 generates a 33kHz digital triangular wave modulation signal and dynamically controls the current-mode logic phase interpolator 16 to adjust the phase step of the output clock in real time, causing the operating clock frequency of the digital module to periodically broaden within the set frequency band. By dispersing the high-amplitude electromagnetic energy originally concentrated at a single frequency point, this step weakens the self-excited radiation spikes of the back-end digital circuit from the source, establishing an electromagnetic radiation isolation barrier.

[0086] Steps 1 to 5 above form a complete closed-loop anti-interference mechanism during the operation of the eddy current displacement sensor, and are executed in a microsecond-level loop as the signal is continuously input, ensuring the high-precision detection performance of the eddy current displacement sensor in complex electromagnetic environments.

[0087] Finally, it should be noted that the solutions in the embodiments are not intended to limit the scope of protection of this utility model. All equivalent implementations or modifications that do not depart from the scope of this utility model are included within the scope defined by this utility model.

Claims

1. An electromagnetic interference suppression circuit for an eddy current displacement sensor, the eddy current displacement sensor comprising: The probe leads, analog detection front end, and digital processing module are characterized in that the electromagnetic interference suppression circuit includes: a fundamental signal isolation module, an external common-mode noise compensation module, and an internal digital noise suppression module; The input terminal of the fundamental signal isolation module is electrically connected to the probe leads; the fundamental signal isolation module has a first output terminal and a second output terminal; the second output terminal of the fundamental signal isolation module is electrically connected to the input terminal of the external common-mode noise compensation module; the first output terminal of the fundamental signal isolation module and the output terminal of the external common-mode noise compensation module are electrically connected to the input terminal of the analog detection front end through the same injection node; the input terminal of the internal digital noise suppression module is connected to a reference clock; the output terminal of the internal digital noise suppression module is electrically connected to the input terminal of the digital processing module.

2. The anti-electromagnetic interference circuit for an eddy current displacement sensor according to claim 1, characterized in that, The fundamental signal isolation module includes: a common-mode current sampling network and a second-order tuned notch filter; The input terminal of the common-mode current sampling network is electrically connected to the probe lead; the output terminal of the common-mode current sampling network serves as the first output terminal of the fundamental signal isolation module and is electrically connected to the input terminal of the second-order tuned notch filter. The output of the second-order tuned notch filter serves as the second output of the fundamental signal isolation module.

3. The anti-electromagnetic interference circuit for an eddy current displacement sensor according to claim 2, characterized in that, The center frequency of the second-order tuned notch filter is set to the fundamental excitation frequency of the eddy current displacement sensor.

4. The anti-electromagnetic interference circuit of an eddy current displacement sensor according to claim 1, characterized in that, The external common-mode noise compensation module includes, in series, a high-order lead compensation network, an operational amplifier circuit, and a high-pass current injection network; wherein the input terminal of the high-order lead compensation network is electrically connected to the second output terminal of the fundamental signal isolation module, and the output terminal of the high-pass current injection network serves as the output terminal of the external common-mode noise compensation module.

5. The anti-electromagnetic interference circuit for an eddy current displacement sensor according to claim 4, characterized in that, The higher-order lead compensation network includes: an RCR lead compensation branch and an LCR resonance suppression branch; one end of the RCR lead compensation branch serves as the input of the higher-order lead compensation network and is connected to one end of the LCR resonance suppression branch; the other end of the RCR lead compensation branch serves as the output of the higher-order lead compensation network; and the other end of the LCR resonance suppression branch is grounded.

6. The anti-electromagnetic interference circuit for an eddy current displacement sensor according to claim 5, characterized in that, The RCR lead compensation branch includes the main resistor and a series branch connected in parallel with the main resistor; The series branch is composed of a first capacitor and a secondary resistor connected in series.

7. The anti-electromagnetic interference circuit for an eddy current displacement sensor according to claim 5, characterized in that, The LCR resonance suppression branch includes an inductor, a second capacitor, and a damping resistor connected in series.

8. The anti-electromagnetic interference circuit of an eddy current displacement sensor according to claim 1, characterized in that, The internal digital noise suppression module is implemented using a low-power open-loop spread spectrum clock generator. The low-power open-loop spread spectrum clock generator includes: a multiphase clock generator, a seed phase selection unit, a current-mode logic phase interpolator, and a digital modulation logic control unit. The input of the multiphase clock generator is connected to the output of the reference clock. The output of the multiphase clock generator is electrically connected to the input of the seed phase selection unit. The output of the seed phase selection unit is electrically connected to the phase seed input of the current-mode logic phase interpolator. The output of the digital modulation logic control unit is electrically connected to the control terminal of the current-mode logic phase interpolator. The output of the current-mode logic phase interpolator is electrically connected to the clock input of the digital processing module.

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