A mass production testing device for an NFCC chip

Abstract

The utility model discloses a kind of mass production testing device of NFCC chip, including multilayer PCB test board, field intensity amplification circuit and coil.Test board adopts the structure of top layer and bottom layer longitudinal stacking, intermediate ground layer is not covered copper, realizes two coil stable electromagnetic coupling;Two measured chips are respectively installed in top layer and bottom layer adjacent station, and are connected corresponding coil by field intensity amplification circuit.The mass production testing device uses the card reader and card of chip itself to complete mutual test with analog dual function, one-time completion traditional two processes, to effectively shorten test cycle, reduce test cost.

Description

Technical Field

[0001] This utility model relates to a mass production testing device for NFCC chips, belonging to the field of integrated circuit testing technology. Background Technology

[0002] Existing NFC (Near Field Communication) chips are divided into two categories: "reader chips" and "card-end chips." These must be used in pairs to transmit and receive signals respectively. In contrast, NFCC (Near Field Communication Controller) chips integrate both reader and card emulation functions on a single silicon chip and can switch between the two modes instantly via host computer commands. This functional integration makes their verification process far more complex than that of traditional single-function chips.

[0003] Currently, the industry generally uses two independent processes to test NFCC chips: the first process places a standard card-end chip on a test board (LB) to verify the card reader function of the NFCC chip under test; the second process builds a card reader circuit on the same or another test board to verify the card emulation function of the NFCC chip under test. This segmented testing approach has significant drawbacks: firstly, the two processes lengthen the overall production cycle, directly reducing production line efficiency and failing to meet the pace of large-scale mass production; secondly, the extended cycle leads to increased overall costs in terms of manpower, equipment, and energy consumption, weakening the product's market competitiveness; and thirdly, the two processes often require different test boards, each requiring independent design and debugging of the card reader or card emulation circuit, increasing design complexity and technical barriers, as well as the workload and time costs of later maintenance.

[0004] Chinese patent application CN111737121A discloses an NFC chip testing device. Its workflow is as follows: receiving a test request → calling the corresponding function script → sending instructions to the NFC chip → collecting and parsing the test results. However, this device only performs SPC calibration testing on single-function NFC chips, relies on external standard cards, debugging tools, and fixed test scripts, and requires connection to a PC via USB and manual intervention in the testing process. It cannot simultaneously complete the verification of dual-function NFC chips in one go. Summary of the Invention

[0005] The technical problem to be solved by this utility model is to provide a mass production testing device for NFCC chips.

[0006] To achieve the above technical objectives, the present invention adopts the following technical solution:

[0007] According to an embodiment of the present invention, a mass production testing device for an NFCC chip is provided, comprising a test circuit board, a field strength amplification circuit, and a coil;

[0008] The test circuit board adopts a multi-layer PCB structure, including a top layer, at least two ground layers, and a bottom layer; wherein, the ground layer is a blank layer without copper coverage, so that the coils of the top layer and the bottom layer can achieve electromagnetic coupling through the space of the ground layer;

[0009] There are at least two chips under test, which are installed on corresponding adjacent workstations on the top and bottom layers respectively; wherein, the chips under test are mounted on the test circuit board; a predetermined pin of each chip under test is connected to the input terminal of the field strength amplification circuit on the circuit board; the output terminal of the field strength amplification circuit is connected to a coil.

[0010] The coils are set at the top and bottom layers of the corresponding workstations and are respectively connected to the field strength amplification circuit of the corresponding chip under test. The top and bottom coils are stacked vertically in the PCB layout design to achieve electromagnetic coupling. All coils are connected to impedance matching circuits.

[0011] Preferably, the multilayer structure of the test circuit board, from top to bottom, consists of: a first solder mask layer, a top layer, a first prepreg layer, a first ground layer, a core board, a second ground layer, a second prepreg layer, a bottom layer, and a second solder mask layer.

[0012] Preferably, the distance between the top coil and the bottom coil is 1.39 mm, and it is composed of 4.5 mil prepreg, 45.8 mil core board and 4.5 mil prepreg.

[0013] Ideally, the impedance matching circuit parameters of adjacent workstations should be consistent to ensure communication reliability.

[0014] Preferably, the field strength amplification circuit includes a signal shaping circuit and a filtering circuit, which are used to improve the strength of the transmitted signal and optimize the signal-to-noise ratio of the received signal.

[0015] Preferably, the test circuit board is provided with multiple stations, the chips of two adjacent stations are respectively installed on the top and bottom layers, and the coils of the top and bottom stations are stacked vertically.

[0016] Compared with existing technologies, this utility model uses a multi-layer PCB test circuit board as its core. The top and bottom coils are stacked vertically and the ground layer is not covered with copper, which ensures stable electromagnetic coupling and eliminates the need for external standard cards and card reader circuits. The field strength amplification circuit integrates signal shaping and filtering functions, and the matching circuit achieves impedance optimization, improving communication reliability. The multi-station adjacent layout supports chip mutual testing, merging the traditional two testing processes into one, shortening the production cycle, and reducing the design and maintenance complexity and hardware cost of the test board. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of a mass production testing device for an NFCC chip, as described in this embodiment of the present invention.

[0018] Figure 2 This is a circuit diagram of a mass production testing device for an NFCC chip, as described in this embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of the interlayer structure of the test circuit board in an embodiment of the present invention. Detailed Implementation

[0020] The technical content of this utility model will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] like Figure 1 and Figure 2 As shown in the figure, this utility model provides a mass production testing device for an NFCC chip, including a test circuit board, a field strength amplifier circuit, and a coil. The test circuit board has multiple stations; taking station 0 and station 1 as examples, the first NFCC chip U1 and the second NFCC chip U2 under test are respectively installed. A predetermined pin of each chip is connected to the field strength amplifier circuit on the circuit board. This field strength amplifier circuit is used to shape the transmitted signal and filter the received signal. A coil is connected to the right side of the field strength amplifier circuit for radiating or receiving electromagnetic signals.

[0022] For the U1 chip, its predetermined pins are connected sequentially to the input terminals of the field strength amplifier circuit, and the output terminal of the field strength amplifier circuit is connected to the coil on the top layer. This coil is located on the top layer of the test circuit board. Other pins of the U1 chip, such as PVDD, TVSS, IFSEL0(A1), TX2, etc., are connected to the corresponding circuits on the test circuit board to provide power, set function modes, transmit data, and connect to the machine control signal output, etc.

[0023] The U2 chip's designated pins are also connected to the input of the field strength amplifier circuit, whose output is connected to a coil on the bottom layer of the circuit board. The relevant functional pins of the U2 chip, such as PVDD, Tvs s 1, IFSEL0(A1), TX2, etc., are also connected to corresponding circuits on the test board to perform functions such as power supply, function configuration, and data transmission.

[0024] like Figure 3 As shown, in one embodiment of this utility model, the test circuit board adopts a multi-layer PCB structure, including at least a top layer, a first ground layer, a second ground layer, and a bottom layer. The top and bottom layers are used to lay out the circuits and coils of the chips under test at adjacent workstations, respectively. The ground layer is a blank layer without copper coverage, so that the coils of the top and bottom layers can achieve electromagnetic coupling through the ground layer space.

[0025] The coils on the top and bottom layers are stacked vertically, meaning the two coils are located on the top and bottom layers of the circuit board, respectively, and correspond to each other vertically. The multilayer structure of the circuit board, from top to bottom, is as follows: a 1mil first solder mask layer, a 1.9mil top layer, a 4.5mil first prepreg layer, a 1.2mil first ground layer, a 45.8mil core board, a 1.2mil second ground layer, a 4.5mil second prepreg layer, a 1.9mil bottom layer, and a 1mil second solder mask layer. Because the first and second ground layers are not copper-clad, the distance between the top and bottom layers is only a few millimeters. This design ensures stable electromagnetic coupling between the two coils, thus providing the hardware foundation for near-field communication between chips at adjacent workstations.

[0026] In one embodiment of this invention, each coil is connected to an impedance matching circuit, which is identical to the chip's matching circuit (i.e., the impedance matching circuit parameters of adjacent stations are identical). This is used to achieve impedance matching of the signal, ensuring minimal signal loss during transmission and improving the stability and reliability of communication. The matching circuit mainly includes components such as capacitors and inductors. Through reasonable parameter design, a good matching relationship is formed between the coil and the NFCC chip.

[0027] The testing procedure for the mass production testing device for the NFCC chip provided by this utility model is described below:

[0028] The test items should include at least:

[0029] SET_SITE0_2_READER_E: Sets the NFCC chip under test at stations 0 and 2 to READER mode. In the layout design of the test board, the coils of station 0 and station 1 are stacked, and the coils of station 2 and station 3 are stacked. Therefore, after stations 0 and 2 are set to READER mode, they can perform communication tests with the corresponding chips at stations 1 and 3.

[0030] SET_SITE 1_3_CARD_E: Sets the NFCC chip under test in stations 1 and 3 to CARD mode, forming a communication pair with the READER mode chips in stations 0 and 2, and performs reader function testing.

[0031] JUDGE_SITE 1_3_CARD_E: Reads the communication results of workstations 1 and 3 to determine whether its function as a CARD has passed the test (PASS).

[0032] JUDGE_SITE0_2_READER_E: Reads the communication results of workstations 0 and 2 to determine whether their function as READER has passed the test.

[0033] SET_SITE 1_3_READER_E: Switches the chip under test in stations 1 and 3 to READER mode.

[0034] SET_SITE0_2_CARD_E: Switches the chip under test at stations 0 and 2 to CARD mode, enabling the interchange of function modes so that the test card can simulate functions.

[0035] JUDGE_SITE0_2_CARD_E: Reads the communication results when workstations 0 and 2 are used as CARDs, and determines whether the card simulation function is PASS.

[0036] JUDGE_SITE 1_3_READER_E: Reads the communication results when workstations 1 and 3 are used as READERs, and determines whether their card reader functions have passed the test.

[0037] First, the NFCC chip under test is installed at the corresponding station on the test circuit board. After the machine's test program starts, the test items are executed in a preset order. Next, stations 0 and 2 are set to READER mode, and stations 1 and 3 are set to CARD mode. At this time, the coils of station 0 and station 1 communicate via electromagnetic coupling, and the coils of station 2 and station 3 also achieve coupled communication. The chip in READER mode sends signals to the chip in CARD mode, and the chip in CARD mode receives and responds to the signals. The test program reads the communication results to determine whether the READER and CARD functions are normal. After completing this round of testing, the program switches stations 1 and 3 back to READER mode and stations 0 and 2 back to CARD mode, and performs the communication test again to determine whether the function in the other direction is normal. Only when both tests pass is the chip considered good and proceeds to the next testing stage; otherwise, the chip is considered faulty, and the test program ends.

[0038] The above testing process fully utilizes the dual-function characteristics of the NFCC chip itself. By merging the two traditional testing steps into one through mutual testing between chips at adjacent workstations, it significantly improves testing efficiency and shortens the production cycle. Furthermore, since there is no need to place additional standard card-end chips or build complex reader circuits on the test board, only mutual testing between the chips under test is required, reducing the complexity of test board design, debugging, and maintenance, and effectively lowering production costs.

[0039] It should be noted that the above embodiments are merely illustrative examples. The technical solutions of the various embodiments can be combined, and all are within the scope of protection of this invention.

[0040] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0041] The above provides a detailed description of the mass production testing device for the NFCC chip provided by this utility model. Any obvious modifications made to this utility model by those skilled in the art without departing from its essential content will constitute an infringement of the patent rights of this utility model and will incur corresponding legal liability.

Claims

1. A mass production testing device for an NFCC chip, characterized in that... Includes test circuit board, field strength amplifier circuit and coil; The test circuit board adopts a multi-layer PCB structure, including a top layer, at least two ground layers, and a bottom layer; wherein, the ground layer is a blank layer without copper coverage, so that the coils of the top layer and the bottom layer can achieve electromagnetic coupling through the space of the ground layer; There are at least two chips under test, which are installed on corresponding adjacent workstations on the top and bottom layers respectively; wherein, the chips under test are mounted on the test circuit board; a predetermined pin of each chip under test is connected to the input terminal of the field strength amplification circuit on the circuit board; the output terminal of the field strength amplification circuit is connected to a coil. The coils are set at the top and bottom layers of the corresponding workstations and are respectively connected to the field strength amplification circuit of the corresponding chip under test. The top and bottom coils are stacked vertically in the PCB layout design to achieve electromagnetic coupling. All coils are connected to impedance matching circuits.

2. The mass production testing device as described in claim 1, characterized in that... The multilayer structure of the test circuit board, from top to bottom, consists of: a first solder mask layer, a top layer, a first prepreg layer, a first ground layer, a core board, a second ground layer, a second prepreg layer, a bottom layer, and a second solder mask layer.

3. The mass production testing device as described in claim 1, characterized in that... The distance between the top and bottom coils is 1.39 mm, and it consists of 4.5 mil prepreg, 45.8 mil core board, and 4.5 mil prepreg.

4. The mass production testing device as described in claim 1, characterized in that... The impedance matching circuit parameters of adjacent workstations are consistent to ensure communication reliability.

5. The mass production testing device as described in claim 1, characterized in that... The field strength amplification circuit includes a signal shaping circuit and a filtering circuit, which are used to improve the strength of the transmitted signal and optimize the signal-to-noise ratio of the received signal.

6. The mass production testing device as described in claim 1, characterized in that... The test circuit board is equipped with multiple stations, with chips in two adjacent stations installed on the top and bottom layers respectively, and the coils of the top and bottom stations are stacked vertically.

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